TWI856541B - Silicon-containing layers with reduced hydrogen content and processes of making them - Google Patents

Abstract

Exemplary methods of making silicon-containing layer with low hydrogen content are described. The methods include flowing deposition gases into a substrate processing region of a processing chamber, where the deposition gases include a silicon-containing gas and a hydrogen gas. A deposition plasma is generated from the deposition gases in the substrate processing region. The methods further include depositing a silicon-containing layer on a substrate form the deposition plasma, where the silicon-containing layer is characterized by a hydrogen content of less than or about 6 mol.% hydrogen. The methods also include forming an amorphous silicon layer on the silicon-containing layer, where the amorphous silicon layer includes less than or about 1 wt.% microcrystalline silicon.

Description

Silicon-containing layer with reduced hydrogen content and its manufacturing process

This application claims the benefit of and priority to U.S. Provisional Application No. 63/316,479, filed on March 4, 2022, entitled “SILICON-CONTAINING LAYERS HAVING REDUCED HYDROGEN CONTENT AND PROCESS FOR MANUFACTURING SAME,” the contents of which are incorporated herein by reference in their entirety for all purposes.

The present technology relates to deposition processes, structures and systems. More particularly, the present technology relates to methods of producing silicon-containing layers having reduced hydrogen content.

Integrated circuits are made possible by processes that produce complex patterned layers of material on substrate surfaces. Producing patterned materials on substrates requires controlled methods to form and remove materials. Material properties can affect how the device operates and can also affect how several films are removed relative to each other. Plasma enhanced deposition can produce films with certain properties. Many of the formed films require additional processing to tune or enhance the material properties of the film to provide the appropriate properties.

Therefore, there is a need for improved systems and methods that can be used to produce high quality components and structures. The present technology addresses these and other needs.

Embodiments of the present technology include a processing method for making a silicon-containing layer having a low hydrogen content. The method includes flowing a deposition gas into a substrate processing region of a processing chamber, wherein the deposition gas includes a silicon-containing gas and a hydrogen gas. A deposition plasma is generated from the deposition gas in the substrate processing region. The method further includes depositing a silicon-containing layer on a substrate to form a deposition plasma, wherein the silicon-containing layer is characterized by a hydrogen content of less than or about 6 atomic percent (at.%) hydrogen. The method also includes forming an amorphous silicon layer on the silicon-containing layer, wherein the amorphous silicon layer includes less than or about 1 volume percent (vol.%) of microcrystalline silicon.

In other embodiments, the silicon-containing layer includes greater than or about 20 volume percent microcrystalline silicon. In further embodiments, the silicon-containing gas includes silane or disilane. In further embodiments, the deposition gas is characterized by a flow rate ratio of hydrogen to the silicon-containing gas of greater than or about 50:1. In other embodiments, the deposition of the silicon-containing layer on the substrate is characterized by a deposition rate of greater than or about 150 angstroms per minute (Å/min). In some other embodiments, the deposition of the silicon-containing layer on the substrate is characterized by a deposition temperature of less than or about 380° C. In more embodiments, the thickness ratio of the silicon-containing layer to the amorphous silicon layer is greater than or about 1:1. In some other embodiments, the method further includes reducing the hydrogen content of the silicon-containing layer by greater than or about 10% prior to forming the amorphous silicon layer, wherein the reduction in hydrogen content is characterized by a removal temperature of less than or about 380°C.

Embodiments of the present technology include additional processing methods. These methods include depositing a silicon-containing layer on a substrate, wherein the as-deposited silicon-containing layer is characterized by a deposited hydrogen content of less than or about 6 at.%. The method also includes forming an amorphous silicon layer on the deposited silicon-containing layer, wherein the amorphous silicon layer has less than or about 1 vol.% microcrystalline silicon. The method also includes reducing the hydrogen content in the as-deposited silicon-containing layer to form a silicon-containing layer with reduced hydrogen content. The silicon-containing layer with reduced hydrogen content is characterized by a reduced hydrogen content of less than or about 5 at.%.

In other embodiments, depositing the as-deposited silicon-containing layer on the substrate is characterized by a deposition rate of greater than or about 150 angstroms per minute. In further embodiments, depositing the silicon-containing layer on the substrate includes forming a deposition plasma from a deposition gas mixture including a silicon-containing gas and a hydrogen gas, wherein the flow rate ratio of the hydrogen gas to the silicon-containing gas is greater than or about 50:1. The deposition plasma deposits the silicon-containing layer on the substrate, wherein the deposition is characterized by a deposition temperature of less than or about 380° C. In further embodiments, a reduction in hydrogen content in the as-deposited silicon-containing layer is characterized by a hydrogen content reduction temperature of less than or about 380° C. In other embodiments, the formation of the amorphous silicon layer includes forming an amorphous silicon deposition plasma from an amorphous silicon deposition gas mixture that does not contain hydrogen. The amorphous silicon layer is deposited from the amorphous silicon deposition plasma. In more embodiments, the silicon-containing layer with reduced hydrogen content includes greater than or about 20 volume percent microcrystalline silicon.

Embodiments of the present technology also include a silicon-containing structure. The structure includes a substrate and a silicon-containing layer located on the substrate, wherein the silicon-containing layer includes less than or about 6 at.% hydrogen. The structure further includes an amorphous silicon layer located on the silicon-containing layer, wherein the amorphous silicon layer is characterized by less than or about 1 volume percent microcrystalline silicon.

In other embodiments, the silicon-containing layer comprises greater than or about 20 vol.% microcrystalline silicon. In further embodiments, the ratio of the thickness of the silicon-containing layer to the amorphous silicon layer is greater than or about 1:1. In further embodiments, the amorphous silicon layer is characterized by a thickness of less than or about 200 angstroms. In other embodiments, the amorphous silicon layer comprises less than or about 6 at.% hydrogen. In more embodiments, the substrate comprises silicon-containing glass.

Such techniques can provide many advantages over conventional processing methods for producing silicon-containing layers having low hydrogen contents. Contrary to intuition, a high flow rate ratio of hydrogen gas to silicon-containing gas in the deposition gas combined with a high deposition rate forms a deposited silicon-containing layer having less than or about 6 at. of hydrogen. In contrast, processing methods using lower flow rate ratios and deposition rates deposit silicon-containing layers having greater than or about 8 at. of hydrogen. In addition, processing methods according to the present technology can be performed at deposition temperatures of less than 400°C. The low hydrogen content in the deposited silicon-containing layer also allows any subsequent dehydrogenation operations to be performed at lower dehydrogenation temperatures and in a short period of time. The silicon-containing layers formed have low hydrogen content without exceeding the reduced thermal budget, which is increasingly becoming a feature of electronic component (e.g., display) manufacturing processes. These and other embodiments (along with their many advantages and features) are described in more detail in conjunction with the following description and accompanying drawings.

Silicon-based transistors are found in the control electronics of most electronic displays. Silicon-based transistors act as switches and conduits for electrical current, turning pixels on and off in electronic displays, among other functions. As these displays increase in complexity and incorporate new heat-sensitive materials, the thermal budget for manufacturing silicon-based transistors and other silicon-containing components continues to decrease.

A conventional method of making a silicon-containing layer for silicon-based electronic components involves depositing the layer using plasma enhanced chemical vapor deposition and performing a dehydrogenation operation on the as-deposited material. The dehydrogenation operation is necessary to reduce the hydrogen content in the layer to a level where few voids are formed due to hydrogen gas formation in subsequent deposition operations. For example, the low hydrogen content reduces the number of voids and defects formed by hydrogen gas during laser annealing of a transistor channel in the silicon-containing layer.

Unfortunately, the dehydrogenation temperatures used in conventional dehydrogenation operations increasingly exceed the thermal budget for manufacturing electronic components, including electronic displays. Conventional dehydrogenation temperatures typically reach or exceed 500°C. A significant reduction in dehydrogenation temperature results in a longer time for the silicon-containing layer to reach a specific hydrogen content. Therefore, reducing the dehydrogenation temperature to stay within the thermal budget significantly increases the processing time and reduces the processing efficiency.

The present technology solves this problem by forming an as-deposited silicon-containing layer having a significantly lower hydrogen content than layers formed by conventional methods. In an embodiment, the present processing method can form an as-deposited silicon-containing layer having less than or about 6 at% hydrogen, compared to a conventional PECVD deposition method that forms a layer having greater than or about 8 mol%. In further embodiments, the reduction in at% hydrogen is characterized by greater than or about 30%, greater than or about 40%, greater than or about 50%, or more. The reduced hydrogen content in the as-deposited silicon-containing layer allows a fixed time dehydrogenation operation to reduce the hydrogen content to a specific amount at a lower dehydrogenation temperature. In embodiments, the temperature can be reduced to less than or about 500° C., compared to conventional methods that conduct dehydrogenation operations at greater than 500° C. The present method allows the dehydrogenation operation to be maintained within a reduced thermal budget without increasing the time to reduce the hydrogen content to a particular level.

The present technology can also reduce processing time and improve processing efficiency by depositing a silicon-containing layer at a faster deposition rate than conventional processing methods. In an embodiment, the present technology uses a faster deposition rate and a higher hydrogen gas to silicon-containing gas flow rate ratio to form a deposited silicon-containing layer with a lower hydrogen content. The faster deposition rate allows the silicon-containing layer to be formed in a shorter deposition time.

Embodiments of the present technology include methods of forming a silicon-containing layer having a reduced hydrogen content on a substrate. In other embodiments, an amorphous silicon layer can be formed on the silicon-containing layer to slow down or prevent hydrogen from penetrating into the silicon-containing layer. Embodiments further include structures made by the method. The following description begins with an embodiment of a system of the present technology, on which the method can be performed. Although specific deposition and processing processes utilizing the present technology are described, it is readily understood that these systems and methods are equally applicable to other deposition and processing systems, as well as processes that may occur in the systems. Therefore, the present technology should not be limited to the specific processes, structures, and systems described herein. System embodiments are first described, including chambers in a system for performing deposition and processing processes according to embodiments of the present technology.

FIG. 1A shows a top view of an embodiment of a processing system 100 according to an embodiment of the present technology. In an embodiment, the processing system 100 may include deposition chambers, processing chambers, etching chambers, baking chambers, and curing chambers, among other types of chambers. As shown in FIG. 1A , a pair of front-opening wafer cassettes 102 supply substrates of various sizes, which are received by a robot 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f (located in series 109a-c). A second robot 110 may be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f may be configured to perform one or more substrate processing operations, including deposition and processing of barrier layer materials as described herein. In embodiments, the substrate processing chambers 108a-f may be configured to perform plasma enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processing, including annealing, ashing, and the like.

The substrate processing chambers 108a-f may include one or more system components for depositing, treating, annealing, curing and/or etching barrier layer materials on substrates. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit and treat barrier layer materials on substrates, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited and treated barrier layer materials. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit a multi-layer stack of barrier material layers on a substrate. Any one or more of the processes described may be performed in a chamber separate from the fabrication system shown in the various embodiments. It should be understood that system 100 contemplates additional configurations of chambers for deposition, processing, etching, annealing, and curing of barrier layer materials.

Figure 1B shows a schematic cross-sectional view of an exemplary plasma system according to an embodiment of the present technology. In the embodiment shown in Figure 1B, the system includes a plasma enhanced chemical vapor deposition (PECVD) chamber (processing chamber) 110, in which a silicon-containing layer and an amorphous silicon layer can be formed on a substrate.

In an embodiment, the chamber 110 includes walls 142, a bottom 114, and a lid 112 that help create a processing volume 128. In additional embodiments, a gas distribution plate 115 and a substrate support assembly 130 also help create the processing volume 128. In further embodiments, the processing volume 128 may be accessed through a gate 126 formed through the wall 142 such that the substrate 102 may be transferred in and out of the chamber 100.

In further embodiments, the substrate support assembly 130 may include a substrate receiving surface 132 to support the substrate 102. In further embodiments, a rod 134 may couple the substrate support assembly 130 to a lift system 136 operable to raise and lower the substrate support assembly 130 between a substrate transfer position and a processing position. In embodiments, a shadow frame 133 may be placed over the periphery of the substrate 102 during processing to prevent deposition on the edges of the substrate 102. In further embodiments, lift pins 138 may be movably disposed through the substrate support assembly 130 and operable to lift the substrate 102 from the substrate receiving surface 132. In further embodiments, the substrate support assembly 130 may include a heating and/or cooling element 139 operable to maintain the substrate support assembly 130 at a particular temperature. In further embodiments, the substrate support assembly 130 may include a ground strap 131 to provide an RF return path around the perimeter of the substrate support assembly 130.

In further embodiments, the gas distribution plate 115 may be connected to the lid 112 or wall 142 of the chamber 115 at its periphery via a hanger 117. In yet another embodiment, the gas distribution plate 115 may be connected to the lid 112 via one or more center supports 116 to help prevent sagging and/or control the straightness/curvature of the gas distribution plate 115. In embodiments, the gas distribution plate 115 may have different configurations with different sizes. In more embodiments, the gas distribution plate 115 may have a quadrilateral planar shape. In yet other embodiments, the gas distribution plate 115 has a downstream surface 150 having a plurality of holes 113 formed therein, the downstream surface 150 facing the upper surface 118 of the substrate 102 disposed on the substrate support assembly 130. The holes 113 may have different shapes, quantities, densities, sizes, and distributions on the gas distribution plate 115. In further embodiments, the diameter of the holes 113 may be greater than or about 0.01 inches, greater than or about 0.1 inches, greater than or about 1 inch, or more.

In yet other embodiments, a gas source 120 may be coupled to the lid 112 to provide gas through the lid 112 and then through holes 113 formed in the gas distribution plate 115 to the processing volume 128. In further embodiments, a vacuum pump 119 may be coupled to the chamber 110 to maintain the gas in the processing volume 128 at a specific pressure.

In an embodiment, the RF power source 122 can be coupled to the lid 112, the gas distribution plate 115, or both to provide RF power that generates an electric field between the gas distribution plate 115 and the substrate support assembly 130 so that plasma can be generated from the gas present between the gas distribution plate 115 and the substrate support assembly 130. In other embodiments, the RF power can be applied at various RF frequencies. For example, the RF power can be applied at a frequency between about 0.3 MHz and about 200 MHz. In another embodiment, the RF power is provided at a frequency of 13.56 MHz.

In further embodiments, the edges of the downstream surface 150 of the gas distribution plate 115 can be curved so that a spacing gradient is defined between the edges and corners of the gas distribution plate 115 and the substrate receiving surface 232 (and therefore, between the gas distribution plate 115 and the upper surface 118 of the substrate 102). In embodiments, the shape of the downstream surface 150 can be selected to meet specific processing requirements. For example, the shape of the downstream surface 150 can be convex, flat, concave, or other suitable shapes. In further embodiments, the edge-to-corner spacing gradient can be used to adjust the uniformity of film properties across the entire substrate edge to correct for property non-uniformities at the corners of the substrate. In further embodiments, the edge-to-center spacing can be controlled so that the uniformity of film property distribution between the edge and the center of the substrate can be controlled. In an embodiment, a concave curved edge of the gas distribution plate 115 may be used such that a central portion of the edge of the gas distribution plate 115 is spaced further from the upper surface 118 of the substrate 102 than the corners of the gas distribution plate 115. In another embodiment, a convex curved edge of the gas distribution plate 115 may be used such that the corners of the gas distribution plate 115 are spaced further from the upper surface 118 of the substrate 102 than the edges of the gas distribution plate 115.

In further embodiments, a remote plasma source 124 (e.g., an inductively coupled remote plasma source) can be coupled between the gas source and the gas distribution plate 115. In embodiments, a cleaning gas can be excited in the remote plasma source 124 to remotely provide a cleaning plasma for cleaning chamber components. The cleaning gas can be further excited by RF power provided to the gas distribution plate 115 by the power source 222. In further embodiments, the cleaning gas can include one or more fluorine-containing gases, such as NF ₃ , F _{2 ,} and SF ₆ .

FIG2 illustrates the operations of an exemplary processing method 200 according to some embodiments of the present technology. The method 200 forms an as-deposited silicon-containing layer having a reduced hydrogen content. The reduced hydrogen content in the layer reduces the temperature and time of the dehydrogenation operation to further reduce the hydrogen content to a specific level. This allows the deposited and dehydrogenated silicon-containing layer to be formed at a lower temperature that does not exceed the reduced thermal budget of a complex electronic component including heat-sensitive materials.

Method 200 includes providing a deposition gas for depositing a silicon-containing layer in operation 205. In an embodiment, the deposition gas may include one or more silicon-containing gases and hydrogen (H ₂ ). In further embodiments, the silicon-containing gas may include at least one of silane (SiH ₄ ) and disilane (Si ₂ H ₆ ) and other silicon-containing gases. In other embodiments, the deposition gas may be free of inert gases, such as nitrogen (N ₂ ), helium, and argon, and other inert gases. In other embodiments, the deposition gas may be free of oxygen.

In an embodiment, the deposition gas may be provided to a substrate processing region of a substrate processing chamber. In further embodiments, the silicon-containing gas may be provided at a flow rate of greater than or about 10 sccm, greater than or about 20 sccm, greater than or about 30 sccm, greater than or about 40 sccm, greater than or about 50 sccm, greater than or about 60 sccm, greater than or about 70 sccm, greater than or about 80 sccm, greater than or about 90 sccm, greater than or about 100 sccm, or more. In further embodiments, the hydrogen gas may be provided at a flow rate greater than or about 1000 sccm, greater than or about 2000 sccm, greater than or about 3000 sccm, greater than or about 4000 sccm, greater than or about 5000 sccm, greater than or about 6000 sccm, greater than or about 7000 sccm, greater than or about 8000 sccm, greater than or about 9000 sccm, greater than or about 10,000 sccm, or more. In yet more embodiments, the relative flow rates of hydrogen gas and the silicon-containing gas can be characterized by a flow rate ratio of H2 gas to Si gas of less than or about 400:1, less than or about 350:1, less than or about 300:1, less than or about 250:1, less than or about 200:1, less than or about 175:1, less than or about 150:1, less than or about 125:1, less than or about 100:1, or less.

In further embodiments, a deposition gas may be provided to a substrate processing region of a processing chamber. In embodiments, the deposition gas may pressurize the processing chamber to greater than or about 5000 mTorr, greater than or about 6000 mTorr, greater than or about 7000 mTorr, greater than or about 8000 mTorr, greater than or about 9000 mTorr, greater than or about 10,000 mTorr, or more.

The method 200 also includes generating a deposition plasma from the deposition gas in operation 210. The deposition plasma may be generated by energizing a pair of capacitively coupled plates located in a substrate processing region of the processing chamber. As shown in FIG. 1B , the pair of capacitively coupled plates may include a cover 112 or a gas distribution plate 115 as a first plate, and a substrate support assembly 130 as a second plate. A power source may energize the plates to generate an electric field that ionizes the deposition gas flowing between the plates into the deposition plasma.

In embodiments, the power source may apply power to the capacitive coupling plate at a power level of greater than or about 5000 W, greater than or about 6000 W, greater than or about 7000 W, greater than or about 8000 W, greater than or about 9000 W, greater than or about 10,000 W, or more. In further embodiments, the power source may apply RF power to the capacitive coupling plate at one or more RF frequencies. In further embodiments, the RF frequency may be greater than or about 1 MHz, greater than or about 5 MHz, greater than or about 10 MHz, greater than or about 25 MHz, greater than or about 50 MHz, greater than or about 100 MHz, greater than or about 150 MHz, greater than or about 200 MHz, or more. In further embodiments, the frequency of the RF power may be 13.56 MHz.

In further embodiments, the deposition plasma can produce a deposition temperature in the processing chamber characterized by less than or about 450° C., less than or about 400° C., less than or about 375° C., less than or about 350° C., less than or about 325° C., less than or about 300° C., less than or about 275° C., less than or about 250° C., or less. In more embodiments, the deposition plasma produces a deposition temperature in the processing chamber that is less than or about a maximum temperature allowed by the thermal budget of the deposition process.

The method 200 further includes depositing a silicon-containing layer on the substrate in the processing chamber at operation 215. In embodiments, the silicon-containing layer is deposited from the deposition plasma at a deposition rate of greater than or about 150 angstroms/minute, greater than or about 150 angstroms/minute, greater than or about 160 angstroms/minute, greater than or about 170 angstroms/minute, greater than or about 180 angstroms/minute, greater than or about 190 angstroms/minute, greater than or about 200 angstroms/minute, greater than or about 210 angstroms/minute, greater than or about 220 angstroms/minute, greater than or about 230 angstroms/minute, greater than or about 240 angstroms/minute, greater than or about 250 angstroms/minute, or more. The fast deposition rate is combined with a flow rate ratio of hydrogen gas to silicon-containing gas to deposit a silicon-containing layer characterized by a reduced hydrogen content. In other embodiments, the hydrogen content of the deposited silicon-containing layer can be less than or about 7 at.%, less than or about 6.5 at.%, less than or about 6 at.%, less than or about 5.75 at.%, less than or about 5.5 at.%, or less.

In further embodiments, the deposited silicon-containing layer may include microcrystalline silicon. In embodiments, the amount of microcrystalline silicon in the silicon layer may be characterized as a crystalline volume fraction (vol.%), which represents the intensity ratio of the crystalline phase to the amorphous phase as measured by, for example, Raman spectroscopy. In other embodiments, the deposited silicon-containing layer may include greater than or about 20 vol.%, greater than or about 25 vol.%, greater than or about 30 vol.%, greater than or about 35 vol.%, greater than or about 40 vol.%, greater than or about 45 vol.%, greater than or about 50 vol.%, or more of microcrystalline silicon. In further embodiments, the deposited silicon-containing layer may be characterized as a microcrystalline silicon layer. In yet more embodiments, the deposited silicon-containing layer may be characterized by a thickness of greater than or about 100 angstroms, greater than or about 200 angstroms, greater than or about 300 angstroms, greater than or about 400 angstroms, greater than or about 500 angstroms, greater than or about 600 angstroms, greater than or about 700 angstroms, greater than or about 800 angstroms, greater than or about 900 angstroms, greater than or about 1000 angstroms, or more.

The method 200 may further include forming an amorphous silicon layer on the silicon-containing layer in operation 220. In an embodiment, the amorphous silicon layer may be used as a capping layer on the previously formed silicon-containing layer to reduce or prevent hydrogen absorption into the silicon-containing layer. In further embodiments, the amorphous silicon layer may be thinner than the silicon-containing layer, and the relative thickness ratio of the silicon-containing layer to the amorphous silicon layer may be greater than or about 2:1, greater than or about 3:1, greater than or about 4:1, greater than or about 5:1, greater than or about 6:1, greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, or more. In further embodiments, the amorphous silicon layer is characterized by a thickness of less than or about 200 angstroms, less than or about 175 angstroms, less than or about 150 angstroms, less than or about 125 angstroms, less than or about 100 angstroms, less than or about 75 angstroms, less than or about 50 angstroms, or less.

In an embodiment, the amorphous silicon layer may be formed by plasma enhanced chemical vapor deposition of amorphous silicon on a silicon-containing layer. In a further embodiment, the deposition operation may include providing an amorphous silicon deposition gas to a substrate processing region of a processing chamber and generating an amorphous silicon deposition plasma. In a further embodiment, the amorphous silicon deposition gas may include a silicon-containing gas and a carrier gas. In a further embodiment, the silicon-containing gas may include one or more of silane and disilane. In a further embodiment, the carrier gas may include helium or argon. In another embodiment, the amorphous silicon deposition gas may not contain hydrogen ( _H2 ) gas.

In other embodiments, the amorphous silicon layer can be deposited at a deposition rate lower than that of the silicon-containing layer. In further embodiments, the amorphous silicon layer can be deposited at a deposition rate of less than or about 100 angstroms/minute, less than or about 90 angstroms/minute, less than or about 80 angstroms/minute, less than or about 70 angstroms/minute, less than or about 60 angstroms/minute, less than or about 50 angstroms/minute, or less. In more embodiments, the amorphous silicon layer can include amorphous silicon, wherein the amount of microcrystalline silicon is less than or about 5 wt.%, less than or about 4 wt.%, less than or about 3 wt.%, less than or about 2 wt.%, less than or about 1 wt.%, or less. In more embodiments, the amorphous silicon layer may have a hydrogen content of less than or about 5 mol%, less than or about 4 mol%, less than or about 3 mol%, less than or about 2 mol%, less than or about 1 mol%, or less. As described above, in embodiments, the amorphous silicon layer may be formed on the dehydrogenated silicon-containing layer after the dehydrogenation operation.

In some embodiments, method 200 may further include reducing the hydrogen content of the as-deposited silicon-containing layer at operation 225. An optional dehydrogenation operation further reduces the hydrogen content of the silicon-containing layer to a specific level. In other embodiments, the as-deposited silicon-containing layer may already have a hydrogen content equal to or less than a specified hydrogen content, and a dehydrogenation operation is not performed. In an embodiment, the dehydrogenation operation reduces the hydrogen content of the silicon-containing layer to less than or about 6 at.%, less than or about 5.5 at.%, less than or about 5 at.%, less than or about 4.5 at.%, less than or about 4 at.%, less than or about 3.5 at.%, less than or about 3 at.%, less than or about 2.5 at.%, or less. In more embodiments, the dehydrogenation operation reduces the hydrogen content of the deposited silicon-containing layer by greater than or about 10%, greater than or about 15%, greater than or about 20%, greater than or about 25%, greater than or about 30%, greater than or about 35%, greater than or about 40%, greater than or about 45%, greater than or about 50%, or more.

In embodiments, the dehydrogenation operation may include quenching the deposition plasma and removing the deposition gas from the substrate processing region of the processing chamber prior to heating the as-deposited silicon-containing layer. In further embodiments, the dehydrogenation temperature of the silicon-containing layer is characterized by less than or about 450° C., less than or about 400° C., less than or about 380° C., less than or about 350° C., less than or about 325° C., less than or about 300° C., less than or about 275° C., less than or about 250° C., or less. In still other embodiments, the dehydrogenation temperature is less than or about the maximum temperature allowed by the thermal budget of the deposition process. In more embodiments, the dehydrogenation temperature is the same as the deposition temperature when the silicon-containing layer is formed. In further embodiments, the dehydrogenation operation can last for less than or about 60 minutes, less than or about 45 minutes, less than or about 30 minutes, less than or about 15 minutes, less than or about 10 minutes, less than or about 5 minutes, less than or about 2 minutes, less than or about 1 minute, or less. The dehydrogenation operation can have the same or shorter duration as conventional dehydrogenation operations performed at higher dehydrogenation temperatures (e.g., greater than or about 500° C.). This is made possible by the lower initial hydrogen content in the deposited silicon-containing layer formed by the present process.

3A-B illustrate a manufacturing process for a structure 300 formed according to an embodiment of the present technology. As shown in FIG. 3A , an embodiment of the structure 300 includes a substrate 302 having a silicon-containing layer 304 formed thereon. In an embodiment, the substrate 302 may include silicon-containing glass, such as glass used in electronic displays. In other embodiments, the substrate 302 may include other silicon-containing materials, such as amorphous silicon, polycrystalline silicon, or crystalline silicon, as well as other silicon-containing materials. In further embodiments, the substrate 302 may include inorganic dielectric materials such as silicon oxide or silicon nitride, as well as other inorganic dielectric materials. In further embodiments, the substrate 302 may include an organic polymer material.

FIG. 3B shows an amorphous silicon layer 306 located on the silicon-containing layer 304. In an embodiment, both the silicon-containing layer 304 and the amorphous silicon layer may be characterized by having silicon layers with different levels of amorphous silicon and microcrystalline silicon. In a further embodiment, the silicon-containing layer 304 may be characterized by including greater than or about 20 vol.% microcrystalline silicon. In more embodiments, the amorphous silicon layer may be characterized by having less than or about 5 vol.% microcrystalline silicon. In still other embodiments, the silicon layers 304 and 306 may be characterized by having less than or about 6 at.% hydrogen, less than or about 5.5 at.% hydrogen, less than or about 5 at.% hydrogen, or less.

Embodiments of the present technology provide silicon-containing layers with reduced hydrogen content formed at reduced deposition and dehydrogenation temperatures. This allows these reduced hydrogen-containing silicon layers to be incorporated into electronic products, such as electronic displays, without exceeding the thermal budget for product manufacturing. Among other benefits, the processing methods of the present technology allow electronic products to be manufactured using more heat-sensitive materials, including display glass and organic luminescent materials.

In the previous description, for the purpose of explanation, many details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with other details.

Several embodiments have been disclosed, and those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, many well-known processes and components have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be considered to limit the scope of the present technology.

Where a range of values is provided, it is understood that each intervening value (unless the context clearly dictates otherwise, accurate to the smallest fraction of the lower limit unit) also specifically discloses the intervening values between the upper and lower limits of the range. Any narrower range between any specified value or unspecified intervening value in a specified range and any other specified or intervening value in the specified range is included. The upper and lower limits of these smaller ranges may be independently included or excluded in the range, and each range (where one, neither, or both of the limits are included in the smaller range) is also included in the technology, subject to the range specified by any explicitly excluded limits. If the range includes one or both of the limits, then those ranges excluding one or both of the limits are also included.

As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a material" includes a plurality of such chambers and reference to "a precursor" includes reference to one or more openings and equivalents thereof known to those skilled in the art, and so forth.

In addition, when the words "comprises," "includes," "including," and "includes" are used in this specification and below, the claim items are intended to specify the existence of the stated features, integers, components, or operations, but do not preclude the existence or addition of one or more other features, integers, components, operations, actions, or groups.

100: Processing system 102: Front-opening wafer transfer box 104: Robot arm 108a-f: Processing chamber 109a-c: Cascade section 106: Holding area 110: Chamber 142: Wall 114: Bottom 112: Cover 128: Processing volume 115: Gas distribution plate 130: Substrate support assembly 126: Gate 102: Substrate 134: Rod 136: Lift system 133: Shadow frame 138: Lift pins 132: Substrate receiving surface 139: Cooling element 131: Ground strap 117: Suspension 115: Chamber 116: Center support 119: vacuum pump 150: downstream surface 113: hole 118: upper surface 120: gas source 122: RF power source 232: substrate receiving surface 124: remote plasma source 222: power source 200: method 205: operation 210: operation 215: operation 220: operation 225: operation 300: structure 304: silicon-containing layer 302: substrate 306: amorphous silicon layer

A further understanding of the nature and advantages of the disclosed technology can be achieved by reference to the remainder of the specification and the accompanying drawings.

Figure 1A shows a top view of an exemplary processing system according to an embodiment of the present technology.

Figure 1B shows a schematic cross-sectional view of an exemplary plasma system according to an embodiment of the present technology.

FIG. 2 illustrates the operation of an exemplary processing method according to an embodiment of the present technology.

3A-B illustrate an exemplary structural development according to an embodiment of the present technology.

Several of the drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes only and should not be considered to be drawn to scale unless specifically indicated to be drawn to scale. Furthermore, as schematic diagrams, these drawings are provided to aid understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

In the drawings, similar components and/or features may have the same reference numeral. In addition, various components of the same type may be distinguished by adding letters to the reference numerals that distinguish the similar components. If only the first reference numeral is used in the specification, the description applies to any similar component having the same first reference numeral, regardless of the letter.

Domestic storage information (please note in the order of storage institution, date, and number) None Foreign storage information (please note in the order of storage country, institution, date, and number) None

102: Front-opening wafer transfer box

110: Chamber

142: Wall

114: Bottom

112: Cover

128: Processing volume

115: Gas distribution plate

130: Substrate support assembly

126: Gate

134: Rod

136: Lifting system

133:Shadow frame

138: Lifting pin

132: Substrate receiving surface

139: Cooling element

131: Grounding zone

117: Suspension

115: Chamber

116: Center support

119: Vacuum pump

150: Downstream surface

113: Hole

118: Upper surface

120: Gas source

122:RF power supply

124: Remote plasma source

Claims (20)

A processing method includes the following steps: Flowing a deposition gas into a substrate processing region of a processing chamber, wherein the deposition gas includes a silicon-containing gas and a hydrogen gas; Producing a deposition plasma from the deposition gas in the substrate processing region; Depositing a silicon-containing layer on a substrate from the deposition plasma, wherein the silicon-containing layer is characterized by having a hydrogen content of less than or about 6 at.%; and Forming an amorphous silicon layer on the silicon-containing layer, wherein the amorphous silicon layer contains less than or about 1 vol.% microcrystalline silicon. The processing method of claim 1, wherein the silicon-containing layer comprises greater than or about 20 vol.% microcrystalline silicon. The processing method of claim 1, wherein the silicon-containing gas comprises silane or disilane. The process of claim 1, wherein the deposition gas is characterized by a flow rate ratio of hydrogen gas to silicon-containing gas of greater than or about 50:1. The process of claim 1, wherein depositing the silicon-containing layer on the substrate is characterized by a deposition rate greater than or about 150 Å/min. The process of claim 1, wherein depositing the silicon-containing layer on the substrate is characterized by having a deposition temperature of less than or about 380°C. The processing method of claim 1, wherein a thickness ratio of the silicon-containing layer to the amorphous silicon layer is greater than or approximately 1:1. The processing method of claim 1, wherein the method further comprises reducing a hydrogen content in the silicon-containing layer by greater than or about 10% after forming the amorphous silicon layer, wherein the reduction in hydrogen content is characterized by a removal temperature of less than or about 380°C. A processing method includes the following steps: Depositing a silicon-containing layer on a substrate, wherein the deposited silicon-containing layer is characterized by having a deposited hydrogen content of less than or about 6 at.%; Forming an amorphous silicon layer on the deposited silicon-containing layer, wherein the amorphous silicon layer contains less than or about 1 vol.% microcrystalline silicon; and Reducing the hydrogen content in the silicon-containing layer to form a silicon-containing layer with reduced hydrogen content, wherein the silicon-containing layer with reduced hydrogen content is characterized by having a reduced hydrogen content of less than or about 5 at.%. The process of claim 9, wherein depositing the as-deposited silicon-containing layer on the substrate is characterized by a deposition rate greater than or about 150 angstroms/minute. The processing method of claim 9, wherein the step of depositing the silicon-containing layer on a substrate comprises: forming a deposition plasma from a deposition gas mixture comprising a silicon-containing gas and a hydrogen gas, wherein a flow rate ratio of the hydrogen gas to the silicon-containing gas is greater than or approximately 50:1; and depositing the silicon-containing layer on the substrate, wherein the deposition of the silicon-containing layer on the substrate is characterized by a deposition temperature of less than or approximately 380°C. The process of claim 9, wherein the reducing the hydrogen content of the silicon-containing layer is characterized by a hydrogen content reduction temperature of less than or about 380°C. A processing method as described in claim 9, wherein the formation of the amorphous silicon layer comprises: forming an amorphous silicon deposition plasma from an amorphous silicon deposition gas mixture that does not contain hydrogen; and depositing the amorphous silicon layer from the amorphous silicon deposition plasma. The processing method of claim 9, wherein the silicon-containing layer with reduced hydrogen content comprises greater than or about 20 vol.% microcrystalline silicon. A silicon-containing structure includes: a substrate; a silicon-containing layer on the substrate, wherein the silicon-containing layer contains less than or about 6 at.% hydrogen; and an amorphous silicon layer on the silicon-containing layer, wherein the amorphous silicon layer is characterized by having less than or about 1 vol.% microcrystalline silicon. The silicon-containing structure of claim 15, wherein the silicon-containing layer comprises greater than or about 20 vol% microcrystalline silicon. The silicon-containing structure of claim 15, wherein a thickness ratio of the silicon-containing layer to the amorphous silicon layer is greater than or approximately 1:1. The silicon-containing structure of claim 15, wherein the amorphous silicon layer is characterized by having a thickness of less than or about 200 angstroms. The silicon-containing structure of claim 15, wherein the amorphous silicon layer contains less than or about 6 at.% hydrogen. A silicon-containing structure as described in claim 15, wherein the substrate comprises silicon-containing glass.

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