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WO1992011638A3 - Rafraichissement synchrone d'une memoire ram dynamique - Google Patents

Rafraichissement synchrone d'une memoire ram dynamique Download PDF

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Publication number
WO1992011638A3
WO1992011638A3 PCT/EP1991/002386 EP9102386W WO9211638A3 WO 1992011638 A3 WO1992011638 A3 WO 1992011638A3 EP 9102386 W EP9102386 W EP 9102386W WO 9211638 A3 WO9211638 A3 WO 9211638A3
Authority
WO
WIPO (PCT)
Prior art keywords
refresh
row
memory cells
data access
dram
Prior art date
Application number
PCT/EP1991/002386
Other languages
English (en)
Other versions
WO1992011638A2 (fr
Inventor
Gerald Lee Frenkil
Steven E Golson
Original Assignee
Vlsi Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vlsi Technology Inc filed Critical Vlsi Technology Inc
Priority to EP92900267A priority Critical patent/EP0563082B1/fr
Priority to DE69104498T priority patent/DE69104498T2/de
Priority to JP04500385A priority patent/JP3140461B2/ja
Priority to KR1019930701858A priority patent/KR930703684A/ko
Publication of WO1992011638A2 publication Critical patent/WO1992011638A2/fr
Publication of WO1992011638A3 publication Critical patent/WO1992011638A3/fr

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

Mémoire RAM dynamique (DRAM) assurant un rafraîchissement synchrone de ses cellules de mémoire. Le rafraîchissement s'effectue pendant un segment de rafraîchissement du cycle d'horloge. Selon un mode préféré de réalisation, la DRAM sélectionne, immédiatement avant le début de chaque cycle d'horloge, une ligne de mots pour une ligne de cellules de mémoire pour lesquelles un accès à l'information doit se produire. La DRAM sélectionne également au moins une ligne de mots pour au moins une ligne de cellules de mémoire pour lesquelles un rafraîchissement doit se produire. Au cours du cycle de rafraîchissement, chaque ligne de cellules de mémoire sélectionnée pour l'accès à l'information ou pour le rafraîchissement subit un rafraîchissement. Après ledit cycle de rafraîchissement, et pendant un segment d'accès à l'information dudit cycle d'horloge, la DRAM continue à sélectionner la ligne de mots pour la ligne de cellules de mémoire pour lesquelles l'accès à l'information doit se produire. Cependant, la DRAM ne sélectionne plus ladite ligne de mots pour ladite ligne de cellules de mémoire sélectionnée pour le rafraîchissement. Pendant le segment d'accès à l'information du cycle d'horloge, ledit accès à l'information s'effectue sur la ligne de cellules de mémoire qui demeure sélectionnée.
PCT/EP1991/002386 1990-12-21 1991-12-10 Rafraichissement synchrone d'une memoire ram dynamique WO1992011638A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP92900267A EP0563082B1 (fr) 1990-12-21 1991-12-10 Rafraichissement synchrone d'une memoire ram dynamique
DE69104498T DE69104498T2 (de) 1990-12-21 1991-12-10 Synchrone auffrischung eines dynamischen ram-speichers.
JP04500385A JP3140461B2 (ja) 1990-12-21 1991-12-10 ランダム・アクセス・メモリ
KR1019930701858A KR930703684A (ko) 1990-12-21 1991-12-10 은폐 재생을 위한 동적임의접근 기억장치 및 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/631,618 US5193072A (en) 1990-12-21 1990-12-21 Hidden refresh of a dynamic random access memory
US631,618 1990-12-21

Publications (2)

Publication Number Publication Date
WO1992011638A2 WO1992011638A2 (fr) 1992-07-09
WO1992011638A3 true WO1992011638A3 (fr) 1992-09-17

Family

ID=24532007

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1991/002386 WO1992011638A2 (fr) 1990-12-21 1991-12-10 Rafraichissement synchrone d'une memoire ram dynamique

Country Status (6)

Country Link
US (1) US5193072A (fr)
EP (1) EP0563082B1 (fr)
JP (1) JP3140461B2 (fr)
KR (1) KR930703684A (fr)
DE (1) DE69104498T2 (fr)
WO (1) WO1992011638A2 (fr)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5335202A (en) * 1993-06-29 1994-08-02 Micron Semiconductor, Inc. Verifying dynamic memory refresh
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
US5748554A (en) * 1996-12-20 1998-05-05 Rambus, Inc. Memory and method for sensing sub-groups of memory elements
AU9798798A (en) 1997-10-10 1999-05-03 Rambus Incorporated Power control system for synchronous memory device
US6707743B2 (en) 1998-10-01 2004-03-16 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
US6898140B2 (en) 1998-10-01 2005-05-24 Monolithic System Technology, Inc. Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
US6504780B2 (en) * 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
TW430793B (en) * 1999-05-20 2001-04-21 Ind Tech Res Inst Self-row identification hidden-type refresh-circuit and refresh method
US6195303B1 (en) 1999-10-25 2001-02-27 Winbond Electronics Corporation Clock-based transparent refresh mechanisms for DRAMS
US7500075B1 (en) * 2001-04-17 2009-03-03 Rambus Inc. Mechanism for enabling full data bus utilization without increasing data granularity
US6825841B2 (en) * 2001-09-07 2004-11-30 Rambus Inc. Granularity memory column access
US6671218B2 (en) 2001-12-11 2003-12-30 International Business Machines Corporation System and method for hiding refresh cycles in a dynamic type content addressable memory
US6625078B2 (en) * 2002-02-11 2003-09-23 United Memories, Inc. Look-ahead refresh for an integrated circuit memory
US6795364B1 (en) * 2003-02-28 2004-09-21 Monolithic System Technology, Inc. Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
JP4357249B2 (ja) * 2003-09-22 2009-11-04 株式会社ルネサステクノロジ 半導体記憶装置
US8190808B2 (en) * 2004-08-17 2012-05-29 Rambus Inc. Memory device having staggered memory operations
US7280428B2 (en) * 2004-09-30 2007-10-09 Rambus Inc. Multi-column addressing mode memory system including an integrated circuit memory device
US8595459B2 (en) 2004-11-29 2013-11-26 Rambus Inc. Micro-threaded memory
CN1870873A (zh) * 2005-05-28 2006-11-29 深圳富泰宏精密工业有限公司 铰链装置及应用该铰链装置的便携式电子装置
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8077535B2 (en) * 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US20080028136A1 (en) 2006-07-31 2008-01-31 Schakel Keith R Method and apparatus for refresh management of memory modules
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US7386656B2 (en) 2006-07-31 2008-06-10 Metaram, Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8090897B2 (en) * 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US7274618B2 (en) * 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
KR101303518B1 (ko) * 2005-09-02 2013-09-03 구글 인코포레이티드 Dram 적층 방법 및 장치
US7292490B1 (en) 2005-09-08 2007-11-06 Gsi Technology, Inc. System and method for refreshing a DRAM device
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20070260841A1 (en) 2006-05-02 2007-11-08 Hampel Craig E Memory module with reduced access granularity
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
DE202010017690U1 (de) 2009-06-09 2012-05-29 Google, Inc. Programmierung von Dimm-Abschlusswiderstandswerten
JP4660613B2 (ja) * 2009-07-24 2011-03-30 株式会社東芝 磁気ディスクドライブにおけるデータリフレッシュ方法
US9268719B2 (en) 2011-08-05 2016-02-23 Rambus Inc. Memory signal buffers and modules supporting variable access granularity
US8938573B2 (en) 2012-06-30 2015-01-20 Intel Corporation Row hammer condition monitoring
US9236110B2 (en) 2012-06-30 2016-01-12 Intel Corporation Row hammer refresh command
US9032141B2 (en) 2012-11-30 2015-05-12 Intel Corporation Row hammer monitoring based on stored row hammer threshold value
US9384821B2 (en) 2012-11-30 2016-07-05 Intel Corporation Row hammer monitoring based on stored row hammer threshold value
US9286964B2 (en) 2012-12-21 2016-03-15 Intel Corporation Method, apparatus and system for responding to a row hammer event
CN104900240B (zh) 2014-03-04 2018-03-23 株式会社东芝 硬盘装置及数据刷新方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3685027A (en) * 1970-08-19 1972-08-15 Cogar Corp Dynamic mos memory array chip
US3737879A (en) * 1972-01-05 1973-06-05 Mos Technology Inc Self-refreshing memory
US4207618A (en) * 1978-06-26 1980-06-10 Texas Instruments Incorporated On-chip refresh for dynamic memory
US4631701A (en) * 1983-10-31 1986-12-23 Ncr Corporation Dynamic random access memory refresh control system
US4831594A (en) 1986-09-25 1989-05-16 Texas Instrument, Inc. Process and device for refreshing an array of dynamic memory cells during precharge of the column lines

Also Published As

Publication number Publication date
JPH06503914A (ja) 1994-04-28
EP0563082B1 (fr) 1994-10-05
DE69104498T2 (de) 1995-05-24
KR930703684A (ko) 1993-11-30
EP0563082A1 (fr) 1993-10-06
WO1992011638A2 (fr) 1992-07-09
JP3140461B2 (ja) 2001-03-05
US5193072A (en) 1993-03-09
DE69104498D1 (de) 1994-11-10

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