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WO1992017045A1 - Module hybride multiniveau/multicouche - Google Patents

Module hybride multiniveau/multicouche Download PDF

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Publication number
WO1992017045A1
WO1992017045A1 PCT/US1992/002295 US9202295W WO9217045A1 WO 1992017045 A1 WO1992017045 A1 WO 1992017045A1 US 9202295 W US9202295 W US 9202295W WO 9217045 A1 WO9217045 A1 WO 9217045A1
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WO
WIPO (PCT)
Prior art keywords
substrates
layer
disposed
interconnect
active
Prior art date
Application number
PCT/US1992/002295
Other languages
English (en)
Inventor
Richard Hiram Womack
Original Assignee
Richard Hiram Womack
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Richard Hiram Womack filed Critical Richard Hiram Womack
Publication of WO1992017045A1 publication Critical patent/WO1992017045A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention pertains in general to packages and, more particularly, to a hybrid microelectronic package using multiple layers and multiple levels.
  • Integrated circuits have seen a significant increase in density due to advances in technology.
  • interconnection of the chip to supporting circuitry is still required regardless of how dense the chip is.
  • this interconnection can be achieved in a planar manner or in a three-dimensional manner.
  • Present technology that exists for building three-dimensional packages or “modules” involves disposing separate chips on single layers and laminating the layers together with various separating or insulating layers disposed therebetween.
  • the manner in which the layers are put together determines the resultant packaging configuration, and also the interconnection scheme.
  • the Gogal device utilizes a plurality of layers with some layers having a chip associated therewith and some layers functioning as interconnects. Plated- through holes are utilized to interconnect the various layers and form the overall circuit structure.
  • the layers are fabricated from ceramics, which have patterns formed thereon.
  • a flexible multi-layered system In another multi-layered package technique, that disclosed in U.S. Patent No. 4,064,552, issued to Angelucci, et. al. on September 20, 1977, a flexible multi-layered system is disclosed.
  • This flexible system consists of a flexible tape layer having a conductor pattern formed thereon which can be disposed over another flexible tape having another pattern formed thereon.
  • Various interconnect schemes are provided for connecting the two layers.
  • the Angelucci device is devised primarily as a flexible printed circuit carrier that functions to support active circuit components and form an overall electronic module.
  • the basic interconnect scheme utilizes apertures formed in each of the layers through which connections are made.
  • the present invention disclosed and claimed herein comprises a method and apparatus for forming a multi-level integrated circuit package.
  • the package includes a plurality of substrates having upper and lower surfaces.
  • Each of the substrates has formed on the upper surface thereof an interconnection layer for providing interconnects to carry signals thereon.
  • the interconnects are formed by patterning the interconnect layer.
  • At least one active component is disposed proximate to the upper surface of one of the plurality of substrates and interfaced with the associated interconnect layer.
  • the substrates are then configured to substantially overly each other and a spacing layer of encapsulant material disposed between the substrates to hold the substrates together and space them apart at a predetermined distance.
  • an intermediate attachment layer is disposed on the lower sides of each of the substrates to provide an intermediate surface that has adherence properties that differ from the surface of the substrate.
  • the encapsulate material that is disposed between the substrates is such that it will adhere better to the intermediate layer.
  • the intermediate layer can be fabricated from a conductive layer for carrying signals and patterned to form a second interconnect layer. The intermediate layer is disposed on the substrate prior to disposing the active component proximate thereto.
  • the intermediate layer on the lower side of the substrate and the interconnect layer on the upper side of the substrate are formed on the substrate with a high pressure lamination process.
  • the encapsulate material utilizes a low pressure encapsulant material. Therefore, the high pressure lamination process is performed prior to mounting the active components on the surface of the substrate, whereas the low pressure encapsulate is utilized to encapsulate the entire active component and interconnect structure on the substrates in a single module.
  • the active component includes optical elements disposed on the active surface thereof for carrying optical signals.
  • An optical conductor is provided on the upper surface of each of the substrates having associated therewith an active component with active elements on the surface thereof, and abutted with the optical elements on the active component. Further, the active surface of the active component is disposed in substantially the same plane as the upper surface of the substrate.
  • FIGURE 1 illustrates a perspective cut-away view of the multi-layered module of the present invention illustrating two active components and two separate and distinct layers;
  • FIGURE 2 illustrates an exploded view of a multi-layered module in accordance with the present invention
  • FIGURE 3 illustrates a cross-sectional view of two layers of a multi- layered module in accordance with the present invention
  • FIGURE 4 illustrates a cross-sectional view of a plated-through hole that has one end buried in the module
  • FIGURE 5 illustrates an alternate embodiment of the present invention illustrating the use of optical fibers formed on one of the layers; and FIGURE 6 illustrates a cross-sectional view of the optical fiber interface of FIGURE 5.
  • FIGURE 1 there is illustrated a perspective view of a multi-layered/multi-level module fabricated in accordance with the present invention, illustrating two active component layers. Although only two layers are illustrated, it should be understood that any number of layers can be incorporated.
  • a first active component 10 is illustrated in one layer with a second active component 12 disposed in a second and higher layer. In the first layer, the active component 10 is disposed in substantially the same plane as a layer of Kapton 14.
  • the layer of Kapton 14 has an opening 16 disposed therein for receiving the active component 10.
  • the active component 10 has a plurality of bonding pads 18 disposed on the active surface thereof for interfacing with tabs 20 that extend outward from the surface of the layer of Kapton 14 into the opening 16.
  • the active component 10 is illustrated as being disposed in the opening 16, it should be understood that the active component 10 could be disposed above the surface of the Kapton layer 14 with the active surface thereof directed downward, the active component 10 mounted in a "flip chip" configuration with no opening required.
  • Kapton is described as the material utilized for the substrates, it should be understood that an epoxy material or other thermal set plastic material could be utilized.
  • the layer of Kapton 14 has an interconnect pattern disposed on the upper side thereof from which the tabs 20 extend.
  • the tabs 20 are a part of the interconnect pattern.
  • the interconnect pattern is essentially fabricated by laminating a layer of copper onto the surface of the Kapton 14, utilizing a high pressure adhesive in a high pressure laminating process.
  • the interconnect layer on the upper surface of Kapton layer 14 is then patterned and etched to form the interconnect pattern as illustrated in FIGURE 1. Therefore, the high pressure laminating process results in a metallization layer that has very good adhesion for all temperatures.
  • one problem with Kapton is the adhesion of low pressure insulating layers, etc., thereto for forming multi- layered systems.
  • the interconnect layer is formed in the same way as that on the mounting side; that is, a conductive copper layer is first laminated onto the surface of the Kapton layer 14 with a high pressure laminating process prior to mounting of the active component 10 and then patterned and etched.
  • the interconnect layer on the interconnect side of the Kapton layer 14 is illustrated by a single metal "run" 22 that extends outward from a cut-away portion.
  • the interconnect side of the Kapton layer 14 is disposed adjacent a layer of low pressure epoxy 24.
  • the low pressure epoxy 24 is applied after mounting of the component 10 in the opening 16, this layer forming a good adhesion with the interconnect side of the Kapton layer 14.
  • An important aspect of the present invention is the utilization of a low- temperature, low-pressure layer adjacent to the surface of the Kapton layer 14 to provide an adhesion between multiple levels of the resultant module.
  • conventional high pressure adhesives can be utilized, the high pressure nature results in damage to the relatively fragile active components 10. Therefore, use of the low-pressure, low-temperature epoxy layer 24 provides an adhesive between two adjacent layers which can be formed therebetween with relatively low pressure.
  • the pattern on the interconnect side and on the mounting side of the Kapton layer 14 assists in adhesion, since some epoxy materials have poor adhesion with the surface of the Kapton 14.
  • the low-pressure adhesive material that provides important aspects of the present invention in conjunction with both active components and associated substrates and interconnect layers.
  • the active component 12 is disposed in the same plane as a Kapton layer
  • the active component 12 is disposed within an opening 28 within a Kapton layer 26 and separated from the edges thereof.
  • the active component 12 has bonding pads 18 disposed thereon with tabs 20 extending from the mounting surface of the Kapton layer 26 across the gap between the opening 28 and the edge of the active component 12 to interface with the bonding pads 18.
  • the tabs 20 are part of an interconnect pattern on the mounting side of the Kapton layer 26.
  • a layer of epoxy 30 is disposed between the mounting surface of the Kapton layer 14 and the interconnect side of the Kapton layer 26.
  • the interconnect side of the Kapton layer 26 has an interconnect pattern disposed thereon, which is illustrated with two runs 34 and 36, illustrated in a cut-away view. These are similar to the run 22 on the interconnect side of the Kapton layer 14.
  • a layer of epoxy 38 is disposed on the mounting side of the Kapton layer 26, it being understood that additional layers can be disposed above the Kapton layer 26.
  • the interconnect patterns on both the mounting side and the interconnect side of both of the Kapton layers 14 and 26 can be interconnected through various plated- through holes.
  • the run 22 has a plated-through hole 39 disposed therethrough and, adjacent thereto, another metal run 40 is illustrated as interfacing with a plated-through hole 44 through the Kapton layer 14.
  • the run 40 extends back under the interconnect side of the Kapton layer 14.
  • a run 42 on the mounting side of the Kapton layer 14 interfaces through the plated-through hole 44 that extends through the Kapton layer 14 interconnecting both the run 42 and the run 40.
  • the plated-through holes can extend between multiple layers. This is illustrated with a plated-through hole 46 that extends from a run 48 on the mounting surface of the layer of Kapton 14 to a run 50 that is disposed on the interconnect surface side of the Kapton layer 26. This plated-through hole 46 can extend upward to multiple layers. As will be described hereinbelow, this plated- through hole can be either completely filled or just hollow with the sides thereof conductive.
  • FIGURE 2 there is illustrated an exploded view of the module of the present invention illustrating one of the Kapton layers and the overlying and underlying epoxy layers.
  • the general module is referred to by a reference numeral 60.
  • An upper Kapton layer 62 is illustrated as having an opening 64 disposed therein for receiving an active component.
  • the active component is referred to by a reference numeral 66.
  • the Kapton layer 62 has a mounting side and an interconnect side, as described above. On the mounting side, an interconnect pattern of runs 68 are provided, some of which terminate in tabs 20 that extend into the opening 64 for interface with the bonding pads 18 on the active surface of the active component 66.
  • the layer of Kapton 62 further has a plurality of holes 70 disposed therethrough, which interface with portions of the run 68, for example, a portion 72, to provide for plated-through holes, as described hereinabove.
  • the interconnect side of the Kapton layer 62 has an interconnect pattern disposed thereon, which interconnect pattern is formed with a plurality of runs 74.
  • the runs 74 are similar to the runs 68 with the exception that they do not have tabs 20 disposed on terminating ends thereof.
  • the runs 68 and 74 are fabricated by first high pressure laminating a layer of copper to the respective surfaces of the Kapton layer 62 and then patterning and etching the copper layers, all prior to mounting of the active component 66.
  • a layer of epoxy 76 is formed on the mounting surface of the Kapton layer 62 above the run 68 after mounting of the active component 66.
  • the epoxy layer 76 is formed with low pressure epoxy materials.
  • an epoxy layer 78 is disposed on the opposite side of the Kapton layer 62 from the epoxy layer 76 on the interconnect side thereof. This epoxy layer 78 contacts on the other side thereof another Kapton layer 80, which also may contain active components.
  • the epoxy layer 78 has disposed therethrough plated-through holes 82 that extend upward through the Kapton layer 62 and the holes 70.
  • the plated-through holes 82 form a wall that extends down through the epoxy layer 78 into underlying Kapton layers 80 and the various runs disposed on either the mounting side or the interconnect sides thereof.
  • the runs 74 have two end portions 84 and 86 for interfacing with the plated-through holes 82 and the metal disposed therein.
  • each of the Kapton layers is illustrated as having a conductor disposed on the mounting side and on the interconnect side. Also, these are patterned to form various runs.
  • the Kapton layer 26, for example, has a run 88 disposed on one side thereof and attached to the mounting side of the Kapton layer 26 with a layer of high-pressure adhesive 90.
  • a run 92 is disposed and attached thereto with a layer of high pressure adhesive 94.
  • the run 92 could be an entire shielding layer of copper.
  • the Kapton layer 14 also has metal runs disposed on the mounting and interconnect sides thereof.
  • a run 96 is illustrated that is attached thereto by a layer of high pressure adhesive 98.
  • a run 100 is disposed thereon and attached with a layer of high pressure adhesive 102.
  • Each of the runs 88 and 96 have disposed thereon the tabs 20 that extend over the openings 16 and 28, respectively.
  • the Kapton substrates 14 and 26 have a thickness of approximately 5 mils.
  • the runs 88, 92, 96 and 100 have a thickness of approximately 1.5 mils.
  • the adhesive layers 90, 94, 98 and 102 have a thickness of approximately 1 mil.
  • the active components 10 and 12 have a thickness of approximately 20 mils.
  • the distance between the bottom of the active component 12 and the uppermost portion of the underlying layer, i.e., the upper surface of the runs 88 or 96, is on the order of 1-2 mils. Therefore, each layer would have a thickness of approximately 22-25 mils, this being determined primarily by the thickness of the active components 10 and 12.
  • the active components 10 and 12 when fabricated from a semi-conductor material, have a co-efficient of around four.
  • the Kapton layers 14 and 26 have a co-efficient of expansion of around thirty and the epoxy layers 24 and 30 have a co-efficient of expansion of around twenty.
  • the epoxy is disposed such that it will fill virtually all voids between the layers.
  • the Kapton substrate is first formed by using a high pressure lamination procedure wherein layers of copper or similar metal are disposed on either side of the Kapton layer. These are then patterned and etched to form the various interconnect patterns and the tabs 20. The opening is pre- formed in the Kapton substrate for disposing the active component.
  • the Kapton substrate is on a "tape" which is a series of interconnect patterns.
  • the substrate is then turned upside down and an active component then disposed in the opening and aligned with the tabs.
  • a raised “bump” is disposed on the chip or active component during fabrication, which requires only heat processing to form the bond between the bonding pad 18 and the tab 20.
  • This is conventional technique.
  • any automated bonding technique that allows the bonding pad 18 to be adhered to the tab 20 could be utilized.
  • wire bonding could be utilized from the tab 20 onto the bonding pad 18, wherein the tab would not extend past the edge of the opening 28, or would only extend a very short distance.
  • the pattern is defined thereon and the active components disposed in the openings and bonded to the tabs 20, the layers then assembled.
  • a low temperature epoxy which, in the preferred embodiment, is a low stress glob top semiconductor encapsulate FP4401, manufactured under the trademark HYSOL by Dexter Electronics Materials Division. The specifications are described in a Bulletin No. E3-434B, which is incorporated herein by reference.
  • the encapsulate is a thixotropic, high-purity epoxy encapsulate. This material has a high-glass transition temperature and low co-efficient of thermal expansion.
  • the product has a viscosity between 73-77, with a co-efficient of linear thermal expansion of 22 x 1& 6 IN/IN°C.
  • the glass transition is approximately 160°C with a hardness of 90 Shore D.
  • the thermal conductivity is 16 x 10 "14 CAL/SEC x CM x °C.
  • the specific gravity is 1.78-1.82 with a flammability of 94HB.
  • the product is cured for approximately three hours at 170°C or six hours at 160°C.
  • the epoxy When the epoxy is applied, it is only necessary to sandwich the multiple layers together with the epoxy and move them in a lateral motion to ensure that the epoxy has filled all voids. Thereafter, the epoxy is cured to form the layers 24 and 30.
  • the layer 30 adheres to the mounting surface of the Kapton layer 14 and the run 96 disposed thereon, and also to the interconnect side of the Kapton layer 26 and the run 92 disposed thereon. Due to the use of the particular epoxy for the layer 30 and the layer 24, the run 92 is needed for two reasons. First, it provides an interconnect layer and second, it provides an adhesive surface for the epoxy 30. However, it should be understood that other materials may be utilized that will provide good adhesion with the surface of the Kapton layer 26.
  • the specific material utilized in the present invention may adhere to the Kapton layer 26, the use of the run 92 and the remaining portions of the interconnect layer provide better adhesion.
  • the important aspect of the present invention is the use of a low temperature low pressure thermal set plastic material for the adhesion layer or insulating layer between the various active layers.
  • FIGURE 4 there is illustrated a cross-sectional view of a plated-through hole, illustrating a buried termination therefor.
  • Three Kapton layers 106, 108 and 110 are illustrated with layer 106 separated from layer 108 by an epoxy layer 112, and layer 108 separated from layer 110 by an epoxy layer 114.
  • An epoxy layer 116 is disposed on the opposite side of layer 110 from the epoxy layer 114.
  • Each of the Kapton layers 106, 108 and 110 have conductive layers disposed on either side thereof.
  • Kapton layer 106 has a conductive layer 118 disposed on the upper side thereof and a conductive layer 120 disposed on the lower side thereof.
  • Kapton layer 108 has a conductive layer 122 disposed on the upper side thereof and a conductive layer 124 disposed on the lower side thereof.
  • Kapton layer 110 has a conductive layer 126 disposed on the upper side thereof and a conductive layer 128 disposed on the lower side thereof.
  • a hole is formed through the layers 106-110 and the epoxy layers 112 and
  • the hole is referred to by the reference numeral 130.
  • the sides of the hole are lined with a conductive material 132 with conventional plating processes. Although illustrated as a lining, it should be understood that this also could be a plug wherein the entire hollow cavity 130 is filled.
  • the lining 132 contacts all of the conductive layers 118-128, such that they conduct therewith. As this is a cross-sectional diagram, each of the conductor layers 126-128 could represent a thin run and it is not necessary that each run terminate at the lining 132. Therefore, one of the conductive layers 118 could conduct with the conductive layer 128 without conducting with the intermediate conductive layers 120-126.
  • the layers 106-110 are first formed and then a hole drilled therethrough with a conventional drilling mechanism. If it is to be a buried layer, the module is assembled in multiple steps with only a few layers assembled, the hole drilled, the hole plated through and then subsequent layers disposed on the upper end thereof. This can be done multiple times to achieve the entire effect. It is only necessary that when the hole is drilled, the edge of the conductive layer that terminates at the hole be exposed. This is the reason that the portion at the end of each of the runs that terminates at the plated-through hole has an expanded area. By drilling through the expanded area, metal that is a portion of the run will be adjacent to and surround the potential plated-through hole. When the plating material is disposed within the hole, a conductive path is formed.
  • a Kapton layer 134 is illustrated that is separated from another Kapton layer 136 by an epoxy layer 138.
  • An active component 140 is disposed in an opening 142 in the Kapton layer 134.
  • an active component 144 is disposed in an opening 146 on the Kapton layer 136.
  • the active component 140 has a plurality of optical waveguides 148, disposed on the upper surface thereof, in addition to the bonding pads 18.
  • Tabs 20 extend from an interconnect pattern formed with metal runs 150 disposed on the mounting surface of the Kapton layer 134.
  • optical fibers 152 are provided on the mounting surface of the Kapton layer 134 that are butted up against an optical junction on the optical waveguides 148.
  • This optical junction is typically an optical diode that makes the conversion from an optical waveguide to an optical fiber.
  • This is conventional in fabricating optical semiconductor devices.
  • One of the primary disadvantages to forming optical semiconductor devices is the alignment of the optical fibers 152 and the optical waveguides 148 on the surface of the chip. The reason that this is difficult, is that typically the surface of the chip is higher than the mounting surface on which it is disposed.
  • the surface of the chip is disposed in approximately the same plane as the mounting surface of the Kapton layer 134 on which the optical fibers are disposed. Therefore, the optical fibers 152 can be disposed on the mounting surface of the Kapton layer 134 after the active component 140 has been mounted thereon with the tabs 20 interfaced with the mounting pads 18. The optical fibers 152 then can be laminated to the mounting surface of the Kapton layer 134 with an appropriate adhesive.
  • the optical device 144 also has associated therewith optical devices such as waveguides.
  • An optical fiber 154 is disposed on the mounting surface of the Kapton layer 136 that interfaces with the upper surface of the active component 144 and extends over to an optical coupler 156.
  • the optical coupler 156 can be laminated onto the surface of the Kapton layer 136.
  • FIGURE 6 there is illustrated a cross-sectional view of the Kapton layer 134 and the epoxy layer 138.
  • the active component 140 is illustrated as having a surface that is essentially co-planar with the upper surface of the Kapton layer 134, but slightly disposed therebeneath.
  • the optical fiber 152 is adhered to the surface of the Kapton layer 134 and the mounting side thereof, with an adhesive layer 159.
  • the end of the optical fiber is then aligned with respect to the optical waveguide 144, or similar optical component on the active surface of active component 140, and then a glass epoxy adhesive applied thereto.
  • An interface device 160 is provided for this purpose, which interface device 160 could be a diode.
  • a multi-layered, multi-level hybrid package utilizing two substrates having an interconnect layer and active components disposed on one surface thereof.
  • the combined active components and interconnect layers and associated substrate are disposed adjacent to similar structures to form a multi-layer module with active components imbedded in the middle of the modules.
  • the layers are adhered together with a low pressure epoxy rosin.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Module de circuit intégré comprenant une pluralité de couches (14, 26) dont chacune possède un ou plusieurs composants actifs (10, 12) ainsi qu'une structure d'interconnexion (34). La structure d'interconnexion est portée par un substrat (30) et les composants actifs sont disposés soit sur le substrat soit sur la structure d'interconnexion elle-même. On empile les substrats (30) avec la structure d'interconnexion et les composants actifs associés, à l'aide d'une résine époxy à faible pression (24) servant à maintenir les couches à une distance prédéterminée les unes des autres. La couche de résine époxy sert à la fois d'adhésif, de matière d'enrobage et de couche isolante. On place une structure d'interconnexion également sur le côté opposé du substrat où elle sert de couche intermédiaire à laquelle la résine époxy peut se coller au cas où elle se collerait mal à la couche de substrat. Par conséquent, on peut former la couche d'interconnexion sur le substrat avant les composants actifs au moyen d'un procédé qui ne convient pas aux composants actifs. La couche de résine époxy convient mieux aux composants actifs disposés sur les substrats puisqu'elle se colle à la couche d'interconnexion plutôt qu'à la surface-même du substrat. On ménage des trous métallisés (44) entre les structures d'interconnexion des deux côtés des substrats et entre divers substrats voisins.
PCT/US1992/002295 1991-03-25 1992-03-20 Module hybride multiniveau/multicouche WO1992017045A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US675,081 1976-04-08
US67508191A 1991-03-25 1991-03-25

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US5745339A (en) * 1994-04-30 1998-04-28 Braumann; Gundokar Packing element including a foam plastic body and a device relating to this packing element
WO1998044557A1 (fr) * 1997-03-27 1998-10-08 Ppc Electronic Ag Carte de circuits multicouche pour tensions et intensites elevees, et procede de production correspondant
EP1041624A1 (fr) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Methode de transfert de substrates ultra-minces et mis en oeuvre de sa methode dans la fabrication de dispositifs de type couches minces
EP1041620A3 (fr) * 1999-04-02 2005-01-05 Interuniversitair Microelektronica Centrum Vzw Methode de transfere de les substrats ultra-minces et application dans la fabrication d'un dispositif de multi-couches minces

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JPH01309362A (ja) * 1988-06-08 1989-12-13 Hitachi Ltd マルチチツプ半導体装置
JPH0286159A (ja) * 1988-09-22 1990-03-27 Hitachi Ltd 半導体装置
US5019946A (en) * 1988-09-27 1991-05-28 General Electric Company High density interconnect with high volumetric efficiency
US5028986A (en) * 1987-12-28 1991-07-02 Hitachi, Ltd. Semiconductor device and semiconductor module with a plurality of stacked semiconductor devices

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US5745339A (en) * 1994-04-30 1998-04-28 Braumann; Gundokar Packing element including a foam plastic body and a device relating to this packing element
WO1998044557A1 (fr) * 1997-03-27 1998-10-08 Ppc Electronic Ag Carte de circuits multicouche pour tensions et intensites elevees, et procede de production correspondant
CH690806A5 (de) * 1997-03-27 2001-01-15 Ppc Electronic Ag Mehrlagiger Leiterplattenkörper für hohe Spannungen und hohe Ströme sowie Verfahren zur Herstellung eines solchen Leiterplattenkörpers.
EP1041624A1 (fr) * 1999-04-02 2000-10-04 Interuniversitair Microelektronica Centrum Vzw Methode de transfert de substrates ultra-minces et mis en oeuvre de sa methode dans la fabrication de dispositifs de type couches minces
US6506664B1 (en) 1999-04-02 2003-01-14 Imec Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layer thin film device
US6730997B2 (en) 1999-04-02 2004-05-04 Imec Vzw Method of transferring ultra-thin substrates and application of the method to the manufacture of a multi-layered thin film device
EP1041620A3 (fr) * 1999-04-02 2005-01-05 Interuniversitair Microelektronica Centrum Vzw Methode de transfere de les substrats ultra-minces et application dans la fabrication d'un dispositif de multi-couches minces

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