WO1993010557A1 - Method for processing silicon wafer - Google Patents
Method for processing silicon wafer Download PDFInfo
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- WO1993010557A1 WO1993010557A1 PCT/JP1992/000662 JP9200662W WO9310557A1 WO 1993010557 A1 WO1993010557 A1 WO 1993010557A1 JP 9200662 W JP9200662 W JP 9200662W WO 9310557 A1 WO9310557 A1 WO 9310557A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
Definitions
- the present invention relates to defects in semiconductor silicon wafers used in semiconductor manufacturing, and in particular to SPD (Surface Particle and Surface Particles).
- the present invention relates to a wafer processing technique called “defect” for making the surface of the wafer defective and fouling with a low tear.
- SPD is a semiconductor silicon wafer which is observed on the surface by a part counter after washing a semiconductor silicon wafer with NH (NH4OM2O2-H2O). Say anything more than 0 ".
- Sections to be solved by the invention Therefore, as an easy way to reduce SPD, it is only necessary to slow down the pulling speed in the production of single crystals, but naturally this will reduce productivity. However, it affects its physical properties, such as oxygen-induced defects and oxygen precipitation ability.
- the present invention provides a new technology that can reduce SPD even for a wafer obtained from a single crystal grown at an increased pulling speed.
- an unheated semiconductor silicon wafer having an oxygen concentration of X L0 17 to 2 X I 0 18 atoms / cc and a carbon concentration of tx 10 16 atomsZcc or less is subjected to 1000 x 1000 in an oxidizing atmosphere. ° C to L300. It is heat-treated at a temperature of C for 0.5 to 5 hours.
- the oxygen saturation t X ⁇ 0 17 to 2 x I 0 18 atoms / cc, the carbon agitation LO x LO 16 atonisZ The unheated semiconductor silicon wafer of CC or less is subjected to L000 in an inert atmosphere. Heat-treat at a temperature of ° C to 1300 ° C for 0.5 to 5 hours.
- an unheated semiconductor silicon nanometer having an oxygen concentration ix 10 17 to 2 X 10 18 atoms cc carbon concentration LX lOT 6 atoms After heat treatment at 1300 ° C at 0-5 to 5 o'clock, the main surface is polished.
- an unheat-treated semiconductor silicon wafer having an oxygen agitation t X ⁇ 0 17 to 2 ⁇ L 0 18 atoms / cc and a carbon concentration L ⁇ L 0 16 atoms / eC or less is placed in an inert atmosphere. After heat treatment at a temperature of 1000 ° C to 1300 ° C for 0.5 to 5 hours, the main surface is polished.
- FIG. 1 is a graph showing the relationship between the heat treatment temperature and the SPDO in silicon wafer.
- Fig. 2 shows the relationship between the oxide film breakdown voltage failure rate and SPD.
- Figure 3 shows the relationship between the single crystal pulling rate by the Chiral Sky method and the SPD teaching in the crystal.
- SPD is thought to be a type of defect formed during the crystal cooling process during single crystal growth, but it is not yet clear at this time.
- the oxygen disturbance IX 10 17 to 2 X I 0 1 toms / cc and the carbon concentration is I x I 0 16 atoms / cc or less: t 000 as in the present invention . It is considered that these may be dissolved by the temperature treatment of C or more.
- U00 was used for 25 wafers each obtained from a silicon single crystal having the same physical properties. Heat treatment was performed at C and 1000 ° C.
- FIG. 1 plots the average values of the SPD teaching of the wafers obtained in Example L and Reference Example I above for each processing temperature. As can be seen, the SPD education in the wafer has been drastically reduced due to the heat treatment at 1000 ° C or higher.
- Wafer in / out speed to heat treatment furnace ⁇ 2 ⁇ 77 ⁇ min
- the percentage of non-defective products that have changed from Z wafers has increased to 90%.
- heat treatment at L000 ° C or more in oxidizing or inert atmosphere By using the heat treatment method of the present invention, the breakdown voltage of the oxide film can be greatly increased. Further, after this heat treatment, the main surface of the wafer is mirror-polished, whereby the yield i can be further improved. Therefore, when a device is formed, productivity can be significantly improved.
- the unheated wafer that has been ejected is usually first subjected to a heat treatment at about 650 ° C. for erasing thermal donors.
- the treatment is also necessary because it also has the function of eliminating thermal damage.
- the present invention is intended to reduce defects in semiconductor silicon wafers used in semiconductor manufacturing, and in particular, to reduce the scrutiny and contamination of the wafer surface called SPD (Surface Particle and Defect). Applies to wafer processing technology.
- SPD Surface Particle and Defect
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Abstract
A semiconductor silicon wafer having an oxygen concentration of 1x1017 to 2x1018 atoms/cc and a carbon concentration of 1x1016 atoms/cc is heated in an oxidizing atmosphere or in an inert atmosphere at 1,000 to 1,300 °C for 0.5 to 5 hours. Alternatively, the wafer main surface is further mirror-polished after this heat-treatment. The present invention aims at reducing defects in the semiconductor wafer and improving a production yield of devices.
Description
明 細 書 Specification
シ リ コ ン ウ ェハの処理方法 Silicon wafer processing method
技銜分野 Skill bite field
本発明は半導体製造に用い られる半導体シ リ コ ソ ゥ ェ ハ中の欠陥、 と く に S P D ( Surface Particle and The present invention relates to defects in semiconductor silicon wafers used in semiconductor manufacturing, and in particular to SPD (Surface Particle and Surface Particles).
Defect) と称される、 ウ ェハ表面の欠陷及び汚損を低涙 させるための ウ ェハ処理技術に関する。 The present invention relates to a wafer processing technique called “defect” for making the surface of the wafer defective and fouling with a low tear.
¾お、 本発明において S P D とは、 半導体シ リ コ ン ゥ ェハ.を NH (NH4OM2O2-H2O) 洗净 したのち、 パ ー テ イ ク ルカ ウ ン タ 一に よ 表面に観察される、 し 0 " 以上の も のを言う 。 Meanwhile, in the present invention, SPD is a semiconductor silicon wafer which is observed on the surface by a part counter after washing a semiconductor silicon wafer with NH (NH4OM2O2-H2O). Say anything more than 0 ".
背景技術 Background art
半導体デバイ スの製造に当 、 その特性の簡易的評価 方法と して、 M O S ダイ オ ー ド'を作成 し、 酸化腠耐圧を 測定する も のが従来か ら採用されている 。 第 2 図に示 し たよ う に、 この ¾化嫫耐圧に よ る不良率 と S P D との関 係が最近明 らかになって き た。 In the manufacture of semiconductor devices, as a simple method of evaluating the characteristics, a method of creating a MOS diode and measuring the oxidation / breakdown voltage has been conventionally used. As shown in Fig. 2, the relationship between the failure rate and the SPD due to the increase in the breakdown voltage has recently been clarified.
す ¾わ ち、 S P Dが増加する程、 酸化膜耐圧不良が増 加する。 これは、 デバイ ス歩留. J でも確認されてお ]5 、 S P Dが増加する程、 デバイ ス歩留 も 同様に悪 く るる 。 —方、 この S P Dは第 3 図に示すよ う に結晶成長条件の 一つである引上げ速度 と も相関関係がある こ とが分かつ ている。 するわち、 引上げ速度を速 く して引上げた単結 晶から得られたゥ ェ S P Dは多 く る That is, as the SPD increases, the oxide film breakdown voltage defect increases. This has been confirmed in Device Yield. J] 5, and as SPD increases, the device yield similarly worsens. On the other hand, as shown in Fig. 3, it is clear that this SPD has a correlation with the pulling speed, which is one of the crystal growth conditions. In other words, there are many PSPs obtained from a single crystal pulled at a high pulling speed.
発明が解決しよう とする課鍰
したがって、 S P D を減少させる手つ取 ぱやい手段 と しては、 単結晶製造の際に、 引上げ速度を遅 く してや れば良いこ とに るが、 当然これでは生産性が低下する こ とにも る し、 その の物性、 たとえば漦素誘起欠陥 や酸素析出能等に影響を与える。 Sections to be solved by the invention Therefore, as an easy way to reduce SPD, it is only necessary to slow down the pulling speed in the production of single crystals, but naturally this will reduce productivity. However, it affects its physical properties, such as oxygen-induced defects and oxygen precipitation ability.
本凳明は引上げ速度を上げて育成した単結晶 よ 得た ウ ェハであっても、 S P D を滅少させる こ とのでき る新 た ¾技術を提供する も のである。 The present invention provides a new technology that can reduce SPD even for a wafer obtained from a single crystal grown at an increased pulling speed.
癸明の開示 Disclosure of Kishi
すなわち、 第一の発明においては、 酸素濃度 〖 X L017 〜 2 X I018atoms/cc、 炭素饞度 t x 1016 atomsZcc以下の未熱 処理の半導体シ リ コ ンウ ェハを酸化雰囲気中で 1000°C 〜 L300。Cの温度で 0.5〜 5 時間熱処理する も のである。 That is, in the first invention, an unheated semiconductor silicon wafer having an oxygen concentration of X L0 17 to 2 X I 0 18 atoms / cc and a carbon concentration of tx 10 16 atomsZcc or less is subjected to 1000 x 1000 in an oxidizing atmosphere. ° C to L300. It is heat-treated at a temperature of C for 0.5 to 5 hours.
第二の発明は、 酸素漫度 t X ί017〜2 x I018atoms/cc, 炭 素擾度 〖 x LOl6atonisZCC以下の未熱処理の半導体シ リ コ ン ウェハを不活性雰囲気中で L000 °C 〜 1300 °C の溫度で 0.5 〜 5 時間熱処理する。 In the second invention, the oxygen saturation t X ί0 17 to 2 x I 0 18 atoms / cc, the carbon agitation LO x LO 16 atonisZ The unheated semiconductor silicon wafer of CC or less is subjected to L000 in an inert atmosphere. Heat-treat at a temperature of ° C to 1300 ° C for 0.5 to 5 hours.
第三の発明は、 酸素漫度 i x 1017〜 2 X l018atoms cc 炭 素蘧度 L X lOT6atomsZcc以下の未熱処理の半導体シ リ コ ン ウ エ ノ、を酸化雰囲気中で L000 °C〜 1300 °Cの温度で 0- 5 〜 5 時 熱処理した後、 主表面を研磨する。 In the third invention, an unheated semiconductor silicon nanometer having an oxygen concentration ix 10 17 to 2 X 10 18 atoms cc carbon concentration LX lOT 6 atoms After heat treatment at 1300 ° C at 0-5 to 5 o'clock, the main surface is polished.
第四の発明は、 酸素擾度 t X ί017〜 2 x L018atoms/cc, 炭 素 Λ度 L x L0l6atoms/eC以下の未熱処理の半導体シ リ コ ン ウェハを不活性雰囲気中で 1000 °C〜 1300 °C の溫度で 0.5 〜 5 時間熱処埕した後、 主表面を研磨する 。
図面の簡単 ¾説明 According to a fourth aspect of the present invention, an unheat-treated semiconductor silicon wafer having an oxygen agitation t X ί0 17 to 2 × L 0 18 atoms / cc and a carbon concentration L × L 0 16 atoms / eC or less is placed in an inert atmosphere. After heat treatment at a temperature of 1000 ° C to 1300 ° C for 0.5 to 5 hours, the main surface is polished. Brief description of drawings
第 1 図は、 熱処理温度 と シ リ コ ン ウ ェハ 中の S P D O 関係を示す図 。 苐 2 図は、 酸化膜耐圧不良率 と S P D の 関係を示す図 。 苐 3 図は、 チ ヨ ク ラ ル ス キ ー法に よ る単 結晶引上げ速度 と 結晶 中の S P D教の関係を示す図であ FIG. 1 is a graph showing the relationship between the heat treatment temperature and the SPDO in silicon wafer. Fig. 2 shows the relationship between the oxide film breakdown voltage failure rate and SPD. Figure 3 shows the relationship between the single crystal pulling rate by the Chiral Sky method and the SPD teaching in the crystal.
Ό 0 Ό 0
発明を実施するための最良の形態 BEST MODE FOR CARRYING OUT THE INVENTION
〔 作 用 〕 [Operation]
S P D は、 単結晶育成中の結晶降温過程において形成 される あ る種の欠陥では ¾ いか と考え られるが、 現在の と こ ろ未だ明確る こ と は分かってい る い 。 しか し、 酸素 擾度 I X 1017〜 2 X I01 o toms/cc、 炭素濃度 I x I016atoms/cc 以下の ：ン リ コ ン ウ ェハ る らば、 本発明の よ う に t 000。C 以上の温度処理に よ i? こ れ らが溶態化するのでは いか と考え られる 。 SPD is thought to be a type of defect formed during the crystal cooling process during single crystal growth, but it is not yet clear at this time. However, if the oxygen disturbance IX 10 17 to 2 X I 0 1 toms / cc and the carbon concentration is I x I 0 16 atoms / cc or less: t 000 as in the present invention . It is considered that these may be dissolved by the temperature treatment of C or more.
〔 実施例 I 〕 [Example I]
チ ヨ ク ラ ル ス キ ー法に よ J 製造 したシ リ コ ン 単結晶か ら得た、 導電型 N型、 結晶 ^ ( 100) 、 抵抗率 5〜 10 Ω - cm、 酸素濃度 15 X I017atoms/cc (常温 法に よ る ） 、 炭素 瘦度 L X I016atoms/cc (常葸 FTIR 法に よ る検出限界） 以下、 直径 5〃の ウ ェハ 25 枚を酸化雰囲気で、 〖200°Cの温度で、 2 時間の熱処理を した。 Conductive N-type, crystal ^ (100), resistivity 5-10 Ω-cm, oxygen concentration 15 X I0 obtained from silicon single crystal manufactured by the chiral square method. 17 (depending on the room temperature method) atoms / cc, carbon瘦度LX I0 16 atoms / cc (detection limit that by the normal葸FTIR method) or less, the c E c 25 sheets diameter 5〃 in an oxidizing atmosphere, 〖200 Heat treatment was performed at a temperature of ° C for 2 hours.
条件の詳細は、 下記の と お であ る 。 Details of the conditions are as follows.
素 ガス流量 ： 6 Li t terZ分 Elemental gas flow rate: 6 Liters
熱処适炉へのウ ェハの入出速度 ： 〖 2 «72 分
昇温速度 ： 8°Cノ分 Wafer in / out speed to heat treatment furnace: 2 «72 minutes Heating rate: 8 ° C min
降温速度 ： 3 °C/分 Cooling rate: 3 ° C / min
1200 °C での保持時間 ： 2時間 Hold time at 1200 ° C: 2 hours
さ らに同一の物性を有するシ リ コ ン単結晶から得 られ たウェハ 2 5 枚ずつを、 U00。C及び 1000 °C で も熱処理 figした。 Furthermore, U00 was used for 25 wafers each obtained from a silicon single crystal having the same physical properties. Heat treatment was performed at C and 1000 ° C.
〔参考例 L 〕 (Reference example L)
チ ヨ ク ラルスキ ー法に よ 製造 したシ リ コ ン単結晶か ら得た、 導電！^ N型、 結晶輔 （L00) 、 抵抗军 5〜 t0 Ω - 77i、 該素濃度 15 X L017atoms/cc ¾ 炭素癢度 ί x 1016 atoms/cc (常 FTIE法による検出限界） 以下、 直径 5 の ウ ェハ 25 枚 を酸化雰囲気で、 900 °Cの温度で、 2 時間の熱処理を し 。 - 条件の詳細は、 下記の とお である。 Conductivity obtained from a silicon single crystal manufactured by the Chiral Clarke method! ^ N-type, crystal Kosuke (L00), the resistance Army 5~ t0 Ω - 77i, (limit of detection by normal FTIE method) the plain concentration 15 X L0 17 atoms / cc ¾ carbon癢度ί x 10 16 atoms / cc or less, Twenty-five wafers with a diameter of 5 were heat-treated in an oxidizing atmosphere at 900 ° C for 2 hours. -Details of the conditions are as follows.
讓素力、、ス流量 ： 6 Litter ,分 Substitution power, flow rate: 6 Litter, min
熟処理炉へのウェハの入出逯度 ： 〖2 OT/分 Temperature of wafer entering / exiting ripening furnace: 〖2 OT / min
昇 M速度 ： 8°CZ分 Ascending M speed: 8 ° CZ min
ί 渥速度 ： 3°CZ分 ί Atsushi speed: 3 ° CZ min
900 °C での保持時間 ： 2 時間 Hold time at 900 ° C: 2 hours
さ らに同一の 性を有する ウェハ 2 5 枚ずつを、 800 °C及び 700 °C でも熱処理を^ した。 Further, 25 wafers each having the same properties were heat-treated at 800 ° C. and 700 ° C.
上記実 ¾例 L 及び參考例 I で得られたウ ェハの S P D 教の平均値を、 処理温度毎でプロ ッ 卜 したのが第 L 図で ある。 これよ わかる よ う に、 1000°C以上の熱処涅に よ ウェハ中の S P D教は、 激減している。
〔 実施例 2 〕 Figure L plots the average values of the SPD teaching of the wafers obtained in Example L and Reference Example I above for each processing temperature. As can be seen, the SPD education in the wafer has been drastically reduced due to the heat treatment at 1000 ° C or higher. [Example 2]
チ ヨ ク ラ ル ス キ ー法に よ 製造 したシ リ コ ン単結晶か ら得た、 導電型 P 型、 結晶軸 （100 )、 抵抗率 6〜 10 Ω- OT、 ¾素 ¾度 15 X 1017atomsZcc、 炭素漫度 ί x 〖016atoms/cc 以 下、 直径 6〃の ウ ェハ 25 枚の酸化膜耐圧を測定 した と こ ろ、 不良率 6 0 であ 、 S P D は平均 300個ノウ ェ ハ であった。 これに不活性雰囲気中で t000°C、 4 時間の熱 処理を旅 した と こ ろ、 S P D は平均 〖 0 個 ウ ヱハ以下 減少 し、 酸化膜耐圧不良は 5 と ¾つた。 Conductive P-type, crystal axis (100), resistivity 6-10 Ω- OT , silicon oxide 15X obtained from silicon single crystal manufactured by the chiral square method. 10 17 atomsZcc, carbon漫度I x 〖0 16 atoms / cc hereinafter, this filtrate and was measured c E c 25 sheets of oxide dielectric breakdown voltage of the diameter 6〃, defective rate 6 0 der, SPD average 300 It was know-how. After traveling through a heat treatment at t000 ° C for 4 hours in an inert atmosphere, the SPD decreased by an average of less than 0 wafers and the oxide film breakdown voltage defect was 5 points.
不活性雰囲気に よ る具体的条件 Specific conditions due to inert atmosphere
望素 ガス流量 ： 6 Li tter ,分 Gas element gas flow rate: 6 Liters, min
熱処理炉への ウェハの入出速度 ： 〖 2 ί77Ζノ分 Wafer in / out speed to heat treatment furnace: 〖2 ί77Ζ min
昇温速度 ： 8 °C /分 Heating rate: 8 ° C / min
洚温速度 ： 3 °C /分 洚 Temperature rate: 3 ° C / min
1000 °C での保持時間 ： 4 時間 Hold time at 1000 ° C: 4 hours
〔 実施例 3 〕 [Example 3]
チ ヨ ク ラ ル ス キ ー法に よ j 製造 した シ リ コ ン 单 ^晶か ら得た、 導電型 P 型、 結晶 ¾ ( 100 )、 抵抗军 1 〜 2 0 - £772、 裟素擾度 18 X l017atomsZcc、 炭素擾度 ί x l016atoms cc以 下、 直径 6 "の ウ ェハ 25 枚を、 C -M0Sデバ イ ス形成工程 を通逼させ、 酸化膜耐圧試験を行 つた 。 酸化腠耐圧試 験では、 良品率 7 0 で、 ウ ェハ 中の S P D は平均 350 個 Zウェハであった。 こ の ウ ェハ を、 1250°C、 3 0 分、 15ィ匕雰 S気中で熱処理 した と こ ろ良品率は 8 5 に、 S P D m は平均 I 0 個ノ ウ ェハであった。 さ らに、 これ らの ゥ ェ
ハの主表面を鏡面研磨 したと ころ S P Dは平均 · I 0 個Conductive P-type, crystal (100), resistance 军 1-20- £ 772 , obtained from silicon 晶 ^ crystals manufactured by the chiral square method. degrees 18 X l0 17 atomsZcc, l0 16 atoms cc hereinafter carbon擾度i x, the c E c 25 sheets of diameter 6 ", C the -M0S Device Lee scan forming step is Tsu逼, the oxide dielectric breakdown voltage test row ivy In the oxidation and withstand voltage test, the non-defective rate was 70, and the average SPD in the wafer was 350 wafers Z. The wafer was subjected to 15 minutes at 1250 ° C for 30 minutes. When heat-treated in air, the yield rate was 85 and the SPD m was an average of I 0 pieces per wafer. When the main surface of C is mirror-polished, the average SPD is I 0
Zウェハ と変化し ¾かったも のの 良品率は 9 0 に向 上した。 The percentage of non-defective products that have changed from Z wafers has increased to 90%.
¾お、 実^例 t ， 2 においても 熱処理後に鏡面研磨 を施しても同様の結果が得られた。 In addition, in Examples t and 2, similar results were obtained even if mirror polishing was performed after the heat treatment.
酸素濃度 [ X L017〜 2 X L018atomsZcc 炭素籩度 t x 1016 atoms/cc 下の半導体シ リ コ ン ウ エ ノ の場合、 酸化性ま たは不活性雰囲気中で L000°C以上の熱処理を ½す本発明 の熱処理方法を用いる こ とによ り 、 漦化膜耐圧を大幅に ί¾上させるこ とができ る。 またさ らに、 この熱処理後ゥ ェハの主表面を鏡面研磨する こ とでさ らに歩留 i? を向上 させるこ とができ る。 したがって、 デバイ スを形成した 場合、 生溼性を大幅に向上させる こ とができ る。 Oxygen concentration [X L0 17 ~ 2 X L 0 18 atoms Zcc Carbon concentration tx 10 16 atoms / cc In the case of silicon silicon, heat treatment at L000 ° C or more in oxidizing or inert atmosphere By using the heat treatment method of the present invention, the breakdown voltage of the oxide film can be greatly increased. Further, after this heat treatment, the main surface of the wafer is mirror-polished, whereby the yield i can be further improved. Therefore, when a device is formed, productivity can be significantly improved.
お、 イ ン ゴッ 卜 よ 切 j? 出された未熱処理の ウェハ は、 まず最初にサーマ ル ドナー消去のための 650°C程度 の熱処理を さ れ る の が通常であるが、 本発明の熱処 垤は、 サー マ ル ド'ナー消去作用 も併せもつので、 必要は o In addition, the unheated wafer that has been ejected is usually first subjected to a heat treatment at about 650 ° C. for erasing thermal donors. The treatment is also necessary because it also has the function of eliminating thermal damage.
産業上の利用可能性' Industrial applicability '
本凳明は半導体製造に用い られる半導体シ リ コ ン ゥ ェ ハ中の欠陷、 と く に S P D ( Surface Particle and Defect) と称される、 ウェハ表面の欠酷及び汚損を低滅 させるための ウェハ処理技術に適用する 。
The present invention is intended to reduce defects in semiconductor silicon wafers used in semiconductor manufacturing, and in particular, to reduce the scrutiny and contamination of the wafer surface called SPD (Surface Particle and Defect). Applies to wafer processing technology.
Claims
請 求 の 範 s Range of claims
し 酸素籩度 I X 10 7~ 2 X l0 8atomS//ccゝ 炭素養度 I
以下の未爇処理の半導体シ リ コ ン ウ ェハ を 酸化雰囲気中で 1000 °C 〜 L 300 °C の温度で 0. 5 〜 5 時間 熱処理する こ と を特徵 とする シ リ コ ン ウ ェハの処理方法 Oxygen concentration IX 10 7 ~ 2 X l0 8 atom S / / cc ゝ Carbon nutrition I A silicon wafer characterized in that the following unprocessed semiconductor silicon wafer is heat-treated in an oxidizing atmosphere at a temperature of 1000 ° C to 300 ° C for 0.5 to 5 hours. C processing method
2. 酸素擾度 〖 x l017〜 2 x
、 炭素漫度 ί x I01 6 atoms/ec以下の未熱処理の半導体 シ リ コ ン ウ ェハ を 不活性雰囲気中で 1000 °C 〜 1300 °C の温度で 0.5 〜 5 時 間熱処理する こ と を卷徵 とす る シ リ コ ン ウ ェ ハの処理方 法。 2. Oxygen agitation 〖x l0 17 ~ 2 x Heat-treating an unheated semiconductor silicon wafer having a carbon content of ίx10 16 atoms / ec or less in an inert atmosphere at a temperature of 1000 ° C to 1300 ° C for 0.5 to 5 hours. A method for processing silicon wafers with a wrapper.
3. 酸素濃度 t X 1017〜 2 X 〖 018 atoms/cc、 炭素 ¾度 I x I016atoms/cc 以下の未熱処理の半導体シ リ コ ン ウ ェハを 酸化雰囲気中で 1000 °C 〜 L300 °C の温度で 0. 5 〜 5 時間 熱処理 した後、 主表面を研磨する こ と を特钕 と する シ リ コ ン ウ ェハの処埕方法。 3. Unheated semiconductor silicon wafer with oxygen concentration t X 10 17 to 2 X 〖0 18 atoms / cc, carbon concentration I x I 0 16 atoms / cc or less, in an oxidizing atmosphere at 1000 ° C L A silicon wafer processing method characterized by polishing the main surface after heat treatment at a temperature of 300 ° C for 0.5 to 5 hours.
酸素籩度 t X 1017〜 2 X lO^atoms/cc、 炭素邊度 I x 1016 atoms/cc 以下の未熱処埕の半導体シ リ コ ン ウ ェ ハ を 不活性雰囲気中で L000 °C 〜 〖300 °C の温度で 0. 5 〜 5 時 間爇処埕 した後、 主表面を研磨する こ と を特徵 とする シ リ コ ン ウ ェハの処理方法。
Oxygen concentration t X 10 17 to 2 X lO ^ atoms / cc, carbon side temperature I x 10 16 atoms / cc or less Unheated semiconductor silicon wafer in inert atmosphere at L000 ° C A silicon wafer processing method characterized by polishing the main surface after treating for 0.5 to 5 hours at a temperature of about 300 ° C.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3/332779 | 1991-11-22 | ||
| JP3332779A JP2770091B2 (en) | 1991-11-22 | 1991-11-22 | Silicon wafer processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1993010557A1 true WO1993010557A1 (en) | 1993-05-27 |
Family
ID=18258735
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1992/000662 WO1993010557A1 (en) | 1991-11-22 | 1992-05-22 | Method for processing silicon wafer |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2770091B2 (en) |
| WO (1) | WO1993010557A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0948037A4 (en) * | 1996-07-29 | 2000-02-02 | Sumitomo Metal Ind | EPITAXIAL SILICON WAFER AND MANUFACTURING METHOD THEREOF |
| WO2004073057A1 (en) * | 2003-02-14 | 2004-08-26 | Sumitomo Mitsubishi Silicon Corporation | Method for manufacturing silicon wafer |
| JP2008133171A (en) * | 2006-10-04 | 2008-06-12 | Siltronic Ag | Silicon wafer and manufacturing method thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5893982A (en) * | 1997-01-08 | 1999-04-13 | Seh America, Inc. | Prevention of edge stain in silicon wafers by oxygen annealing |
| US6573159B1 (en) | 1998-12-28 | 2003-06-03 | Shin-Etsu Handotai Co., Ltd. | Method for thermally annealing silicon wafer and silicon wafer |
| US7160385B2 (en) | 2003-02-20 | 2007-01-09 | Sumitomo Mitsubishi Silicon Corporation | Silicon wafer and method for manufacturing the same |
| WO2004008521A1 (en) * | 2002-07-17 | 2004-01-22 | Sumitomo Mitsubishi Silicon Corporation | High-resistance silicon wafer and process for producing the same |
| US8426297B2 (en) | 2008-08-08 | 2013-04-23 | Sumco Techxiv Corporation | Method for manufacturing semiconductor wafer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184345A (en) * | 1989-12-13 | 1991-08-12 | Nippon Steel Corp | Silicon wafer and manufacture thereof |
-
1991
- 1991-11-22 JP JP3332779A patent/JP2770091B2/en not_active Expired - Lifetime
-
1992
- 1992-05-22 WO PCT/JP1992/000662 patent/WO1993010557A1/en active Application Filing
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03184345A (en) * | 1989-12-13 | 1991-08-12 | Nippon Steel Corp | Silicon wafer and manufacture thereof |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0948037A4 (en) * | 1996-07-29 | 2000-02-02 | Sumitomo Metal Ind | EPITAXIAL SILICON WAFER AND MANUFACTURING METHOD THEREOF |
| WO2004073057A1 (en) * | 2003-02-14 | 2004-08-26 | Sumitomo Mitsubishi Silicon Corporation | Method for manufacturing silicon wafer |
| EP1513193A4 (en) * | 2003-02-14 | 2007-02-28 | Sumco Corp | PROCESS FOR PRODUCING A SILICON WAFER |
| CN100397595C (en) * | 2003-02-14 | 2008-06-25 | 三菱住友硅晶株式会社 | Manufacturing method of silicon wafer |
| US7563319B2 (en) | 2003-02-14 | 2009-07-21 | Sumitomo Mitsubishi Silicon Corporation | Manufacturing method of silicon wafer |
| JP2008133171A (en) * | 2006-10-04 | 2008-06-12 | Siltronic Ag | Silicon wafer and manufacturing method thereof |
| US7964275B2 (en) * | 2006-10-04 | 2011-06-21 | Siltronic Ag | Silicon wafer having good intrinsic getterability and method for its production |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2770091B2 (en) | 1998-06-25 |
| JPH05144827A (en) | 1993-06-11 |
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