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WO1994022167A1 - Structure a semiconducteur et procede pour fabriquer cette structure - Google Patents

Structure a semiconducteur et procede pour fabriquer cette structure Download PDF

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Publication number
WO1994022167A1
WO1994022167A1 PCT/GB1994/000475 GB9400475W WO9422167A1 WO 1994022167 A1 WO1994022167 A1 WO 1994022167A1 GB 9400475 W GB9400475 W GB 9400475W WO 9422167 A1 WO9422167 A1 WO 9422167A1
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor structure
isolating
structure according
barrier
Prior art date
Application number
PCT/GB1994/000475
Other languages
English (en)
Inventor
Alan Gordon Robert Evans
Mohammad Mateen Farooqui
Original Assignee
British Technology Group Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by British Technology Group Limited filed Critical British Technology Group Limited
Priority to EP94909181A priority Critical patent/EP0689719A1/fr
Priority to JP6520752A priority patent/JPH08507904A/ja
Priority to GB9518447A priority patent/GB2290661B/en
Publication of WO1994022167A1 publication Critical patent/WO1994022167A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76289—Lateral isolation by air gap

Definitions

  • This Invention relates to semiconductor structures in general, and more particularly to such a structure incorporating electrical devices such as Complementary Metal Oxide Silicon (CMOS) transistors in which each device 1s electrically isolated from other such devices.
  • CMOS Complementary Metal Oxide Silicon
  • the invention also relates to a method of manufacturing such a structure.
  • Such structures typically comprise an epitaxial layer of Silicon covering a substrate of bulk Silicon, with a number of electrical devices formed adjacent the upper surface of the epitaxial layer.
  • SOI Silicon-On- Insulator
  • SOS Si11con-On-Sapphire
  • SIMOX Separation by Implanted Oxygen
  • Wafer Bonding this technique is described, for example, in the paper by Maszara, W.P.
  • the technique comprises forming a Silicon dioxide isolating layer on a Silicon substrate, preparing a separate single-crystal Silicon wafer, and then bonding the wafer to the substrate.
  • the wafer is then ground down using a precision- controlled lapping machine from an initial thickness of perhaps 500 ⁇ to an ultimate thickness of possibly only 1 or 2 ⁇ .
  • the electrical devices are formed in this 1 or 2 ⁇ m thick single- crystal Silicon semiconductor layer.
  • Wafer Bonding technique Whilst the basic Wafer Bonding technique as described above provides electrical isolation beneath the electrical devices (between each device and the Silicon substrate), it does not provide isolation between the electrical devices themselves.
  • An article by Watanabe, . e_t ___.. entitled "A Bonded-SOI Bipolar Process Technology" (Proc. 1st Symposium on Silicon Wafer Bonding, Electrochemical Society, U.S.A., 1991, p. 443) provides the solution to this problem In the form of shallow isolating grooves extending from the top surface of the semiconductor layer through to the Silicon dioxide Isolating layer, thus forming a semiconductor island which is completely isolated from other such islands (except possibly for purpose-built electrical connections).
  • US-A-4070230 and US-A-4072982 describe techniques which use an etch stop and require a support. Wide isolation channels are formed and this gives rise to an imprecise etch stop. Furthermore p-n junction isolation is used.
  • the present invention allows an isolated layer to be fabricated, which can be very much thinner than the layers described in either of the aforementioned US Patents. Sub-micron isolation is possible with low leakage dielectrics.
  • n+ provides only limited selectivity between n+ and n etching. Thin uniform layers cannot be obtained by this technique over a substantial area of a slice and it is almost impossible to obtain sub-micron thick layers using either technique, in contrast to the present invention.
  • Patent Abstracts of Japan Vol 8 No. 176 (E-260) (1613) 14th August 1984 describes a technique of selective etching of an n+ layer. This does not provide enough selectivity to form thin isolation layers between devices by diffusion. However, in the present invention precise etch stop, with very high selectivity is used; as is dielectric isolation. Whilst the Wafer Bonding technique has achieved some commercial success, it suffers from the drawbacks firstly that the precision lapping required to reduce the wafer from, say, 500 to l ⁇ m is a complex, difficult and expensive task, and secondly that the bond between the substrate and wafer is difficult to make and may not be perfect. Bonding needs to be carried out in exceptionally clean and contaminant free conditions in order to avoid voids and unbonded areas. Such conditions can be expensive and difficult to maintain.
  • Barth proposes the use of a preferential etching technique commonly used in the fabrication of thin semiconductor membranes to fabricate a device comprising, in sequence, a Poly-Si 1 ⁇ con substrate, a layer of Silicon dioxide, and a layer of eoitaxially grown single-crystal Silicon.
  • the epitaxial layer is processed by preferential etching of a starting material comprising a heavily doped Silicon wafer and the lightly doped epitaxial layer, thus leaving the epitaxial layer.
  • Complete dielectric isolation is afforded by layers of Silicon dioxide extending from the main Silicon dioxide layer upwardly and outwardly to the upper surface of the epitaxial layer.
  • the technique proposed by Barth suffers from the drawbacks that it is complicated and time consuming (many process steps being involved) and that it is a necessary feature of the technique that the epitaxial layer is doped throughout its entire thickness, which may be problematical for certain applications, especially those involving CMOS devices. Furthermore, the preferential etching technique employed 1s not sufficiently selective to provide thin epitaxial layers.
  • the present invention seeks to overcome the problems both of the Wafer Bonding and of the Barth techniques.
  • a semiconductor structure comprising a layer of semiconducting material having first and second opposing surfaces, an electrical device at least a portion of which is adjacent the first surface, and an isolating barrier for the electrical device extending through the semiconducting material towards the second surface, there being an isolating region to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direct contact with the ambient medium.
  • the term "surface” includes both external surfaces (faces ) of the structure and also internal surfaces (boundaries between different portions of the structure).
  • the second surface may be at the boundary between the semiconducting material and a layer of insulating material.
  • the term "electrical device” includes any kind of active or passive device, including a simple strip of conductor.
  • the term "region” may refer, for instance, both to a two-dimensional area and to a three-dimensional portion of the structure (one having finite thickness) .
  • the structure of the present invention can provide complete electrical isolation for the electrical device. Furthermore, since the isolating region of the present Invention is in direct contact with the ambient medium, manufacturing of the structure can be greatly simplified. Either isolation can be provided in the isolating region by the ambient medium itself, thus completely obviating the need for any insulating material, or else any insulating material which is applied in this region can be applied at a late stage of manufacture, when it need not interfere with the other manufacturing steps.
  • An additional advantage of the present invention is that it can obviate the need to carry out any removal of semiconducting material from above the structure to form the first surface, adjacent which the electrical device is fabricated.
  • Such removal in the known techniques is necessary to the formation of a thin, isolated layer of semiconducting material, but is, however, disadvantageous.
  • the removal is effected by a precision lapping process, whose disadvantages have already been discussed.
  • the removal is effected by selective etching up to a doped epitaxial layer. As discussed previously, doping of the epitaxial layer can cause problems, and the selective etching technique is in any case not sufficiently selective to provide a suitably thin epitaxial layer.
  • the present invention can obviate such problems by allowing that any removal which may be necessary to the formatio of a thin, isolated layer of semiconducting material can be carried out underneath the structure, usually up to or adjacent the second surface. This is rendered possible by having the isolating region in direct contact with the ambient medium. rather than internal to the structure (which latter would effectively prevent processing of the structure from underneath).
  • the isolating barrier suitably takes the form of one or more possibly criss-crossing, isolating trenches of considerable depth (typically more than 5 ⁇ m) and preferably extending right from the first surface to the second surface.
  • the isolating barrier may extend directly to the ambient medium (which would often be air), so that the electrical device may be isolated from neighbouring devices by a combination of the barrier and the ambient medium.
  • the barrier may extend to a layer of electrically insulating material in the isolating region, so that the electrical device may be isolated from neighbouring devices by a combination of the barrier, the insulating material and, beyond that, the ambient medium.
  • the insulating material suitably has a very high resistivity (above, and preferably one or indeed many (for example, 5 or 10) orders of magnitude above, that of pure undoped single or poly- crystalline Silicon).
  • the insulating material preferably has a chemical formula which is related to that of a semiconductor material, and is more preferably a compound of, even more preferably an oxide or nitride of, Silicon. Most preferably, it is Silicon dioxide or Silicon nitride.
  • the layer of insulating material is formed from a compound of Silicon and the layer of semiconducting material is formed from Silicon, this can render the manufacturing process cheaper and simpler than if the isolating material were a material such as Sapphire (as is the case in the known Silicon-on-Sapphire (SOS) technique). It can also obviate the problems encountered using the SOS technique of crystal imperfections arising in the Silicon due tc incompatibilities between the crystal structures of the two materials and of a mismatch between their thermal expansion coefficients.
  • the semiconducting material is substantially free from crystallographic defects, for optimal performance of the electrical device.
  • the thickness of any material in the isolating region beyond the layer of semiconducting material is less than the thickness of the layer of semiconducting material, more preferably less than half the thickness of the layer of semiconducting material. It will be appreciated that usually either such material will be insulating material in direct contact with the ambient medium, or else no material will be present at all, only the ambient medium. By only having a small amount of material beyond the layer of semiconducting material, the structure can be fabricated as a thin membrane and access to the rear of the structure can be afforded. This offers several concomitant advantages.
  • the structure can easily be cooled by one of several means such as conduits bearing coolant. This can be particularly important if the structure constitutes a VLSI circuit for use in, for example, a supercomputer. Cooling can be particularly effective because the structure can have minimal thermal resistance due to its small thickness.
  • the structure can be sufficiently thin that it can be used as a force, pressure, acceleration or radiation sensitive device, optionally with a CMOS circuit actually on the diaphragm.
  • the structure could be rendered photo- or electro-luminescent by forming a light emitter on the back (second) surface of the semiconductor layer.
  • an important advantage is that the electrical device or devices on the structure can be optically addressed from the rear, via the second surface. Such addressing could, for instance, be utilised for controlling the electrical device.
  • the structure can be fabricated as a relatively thin membrane, it can be rendered resistant to radiation.
  • the structure preferably includes a relatively thick portion supporting the relatively thin portion.
  • the relatively thick portion supports the relatively thin portion around substantially its entire periphery. This embodiment can be appropriate for a fabrication process in which back-etching is employed for forming the thin membrane.
  • the relatively thin portion is elongate and is supported by the relatively thick portion adjacent at least one of its ends.
  • This embodiment can be appropriate for a fabrication process in which the thin membrane is etched from in front, by etching around the sides of the thin, elongate portion and then under-cutting it.
  • Front etching can be advantageous over back etching fcr the following reasons. Firstly, back etching re ⁇ uires r-ec.se back-alignment of the etch mask. This requires an inf-a-rec viewer to observe and align the mask on the back surface in relation to the pattern on the front surface, which can be difficult and time-consuming. Secondly, typically back etching requires the removal of relatively large amounts of material (typically a depth of 500 ⁇ m may need to be removed). This can be very time consuming. Front etching, by contrast, requires the removal of only relatively small amounts of material (typically a depth of less than 30 ⁇ m). Front etching can also provide a more robust structure than can be provided by back etching.
  • the thin, elongate portion may be supported adjacent both of its ends, in which case it forms a beam, or it may be supported adjacent only one of its ends, in which case it forms a cantilever.
  • the cantilever can be used, for example, for stress or acceleration sensing.
  • At least one cavity is formed in the semiconductor structure extending from the first surface to the second surface. This cavity will have been employed to afford the etchant access to undercut the second surface.
  • the semiconductor structure includes a layer of etch stop material adjacent the second surface.
  • etch stop material adjacent the second surface.
  • the electrical device may take many forms, it is preferably a CMOS device. Usually several thousands or even hundreds of thousands of such devices would be provided, each with its own isolating barrier.
  • the invention extends to a method of manufacturing a semiconductor structure, comprising providing a layer of semiconducting material having first and second opposing surfaces, fabricating an electrical device, at least a portion of the device being adjacent the first surface, providing an isolating barrier for the electrical device extending through the semiconducting material towards the second surface, and Dro icir.c an isolating region to which the barrier extends where there is no electrically non-insulating material spanning the barrier, the isolating region being in direct contact with the ambient medium.
  • the method steps may take place in any appropriate order.
  • the* provision of semiconducting material in the form of a layer having the aforementioned first and second surfaces may (and in the preferred embodiment does) take place after the fabrication of the electrical device.
  • a member incorporating the semiconducting material is preferably provided, and a portion of this member removed to form the second surface. This enables a layer of thin and electrically good quality semiconducting material to be produced, without the problems of the Wafer Bonding and Barth techniques associated with removal of material to form the first surface being encountered.
  • the portion is removed from beyond the second surface towards the second surface.
  • the removal is suitably by back-etching.
  • the portion is removed progressing from a region of the first surface towards the second surface and then progressing behind the second surface so as to undercut the second surface.
  • the removal is suitably by front-etching.
  • the region may be defined by a boundary arrangement (suitably an etch boundary arrangement) extending from the first surface to the second surface.
  • this layer is preferably provided subsequent to the removal step. Providing the layer of insulating material after the removal step (and hence at a relatively late stage in the manufacturing process) can considerably simplify manufacture, as suggested previously.
  • the isolating barrier is preferably provided before the removal step, whilst the member is in its thicker and hence stronger and more stable state. This can be an important feature in assuring the structural integrity of the final semiconductor structure.
  • the electrical device may be fabricated before the removal step.
  • the second surface may be passivated subsequent to the removal step. This passivated surface may then be in direct contact with the ambient medium, or may be covered with a further layer of insulating material itself in direct contact with the ambient medium.
  • the portion of the member may be removed to form the second surface by a low damage lapping technique such as chemical-mechanical (Syton - trade mark) polishing.
  • the portion is preferably removed either by etching alone, or by a combination first of lapping and then of etching.
  • the etching is preferably effected up to an etch stop layer defining the second surface, again for manufacturing simplicity.
  • the step of providing a layer of semiconducting material includes providing a substrate, forming an etch stop layer on a surface of the substrate, and covering (preferably by epitaxy) the etch stop layer with semiconducting material. This technique can be utilised to provide good quality semiconducting material on which the electrical device may be fabricated.
  • the layer of semiconducting material is grown epitaxially from a substrate to which the epitaxially grown material is lattice-matched; more preferably, the material of the epitaxially grown portion is substantially the same as that from which the substrate is formed.
  • the portion of semiconducting material can have good electrical properties.
  • SOS Silicon-On- Sapphire
  • Figures 1 are schematic diagrams showing the stages of production of a semiconductor structure according to the present invention
  • Figures 2 are similar schematic diagrams illustrating a specific process for producing the semiconductor structure
  • Figure 3 is a schematic perspective view of an alternative embodiment of semiconductor structure according to the present invention.
  • Figures 4 are schematic diagrams showing the stages of production of the alternative embodiment of semiconductor structure.
  • the stages of production of a semiconductor structure 10 are first illustrated in general with reference to Figures 1.
  • the production process commences with the diffusion of a Boron etch stop layer 100 into the surface of a single crystal Silicon slice 102.
  • the stop layer in this embodiment is between 0.5 and 1 ⁇ m thick, but may be as thick as 2 ⁇ m.
  • the Silicon slice has a ⁇ 100> crystal orientation, and may be either p- or n- type.
  • the etch stop layer 100 may be grown epitaxially on the Silicon slice 102.
  • an epitaxial layer 104 of single crystal Silicon is grown on top of the Boron etch stop layer 100 using a Chemical Vapour Deposition (CVD) technique.
  • the epitaxial layer is undoped. Autodoping from the etch stop layer is restricted by growing the epitaxial layer at low temperature
  • the epitaxial layer is typically about 2 ⁇ m thick, but may be, for example, as thin as 0.5 ⁇ m, or indeed thicker than 3 ⁇ m, depending upon requirements.
  • the stop layer is typically about 2 ⁇ m thick, but may be, for example, as thin as 0.5 ⁇ m, or indeed thicker than 3 ⁇ m, depending upon requirements.
  • a semiconductor layer 106 having an upper surface 108 and a lower surface 110 defined by the lower extent of the stop layer 100. It will be appreciated that the term "surface” is used to include reference to any internal surface (or boundary) of the structure.
  • trenches 112 are etched in the structure using a Chlorine chemistry anisotropic plasma etching technique.
  • Chlorine chemistry anisotropic plasma etching technique Other techniques, possibly involving Chlorine and Silicon tetrachloride in a Nitrogen plasma, are also feasible.
  • the trenches 112 are refilled with successive layers of low temperature Silicon dioxide, Poly-SiHcon and Silicon nitride so as to form an electrically insulating barrier.
  • the quality of the refilling needs to be good since the strength of the eventual structure depends on it.
  • the trenches 112 extend downwardly from the upper surface 108 of the semiconductor layer 106 through the stop layer 100 and the lower surface 110 and project downwardly somewhat from this surface. Thus the trenches are typically 3.5 ⁇ m deep. To avoid using up space on the semiconductor layer, and to avoid weakening the structure excessively, the trenches are as thin as possible (about 1 to 2 ⁇ ). They are etched in a criss-cross pattern to form islands 114 of semiconductor material completely encircled by the isolating trenches. Only some of the trenches are apparent in Figures 1 (which are cross- sectional views of the structure).
  • CMOS devices 116 are fabricated in the islands 114, individual components of each device being formed at or near the upper surface 108 and also possibly further down in each island " ⁇ , & .
  • the CMOS devices may be of an suitable type: indeed, otne * " electrical devices may be fabricated to suit requirements.
  • SJCP devices may, for example, be other types of transistors, resistive devices to sense pressure or strain in the semiconductor structure, or thermally sensitive devices. If CMOS devices are fabricated, they may be alternately p- and n- channel devices in alternate islands. As discussed later, the present invention can ensure that these devices are electrically isolated from each other.
  • a protective coating 115 is formed on top of the CMOS devices 116.
  • the coating is made of Low Temperature (200 to
  • a low temperature is chosen in order to prevent heat damage to the CMOS devices and metallisation.
  • the semiconductor structure 10 is back-etched up to the Boron etch stop layer 100 using a Potassium hydroxide (KOH) wet etch or any suitable anisotropic etch such that the etch stops at the stop layer.
  • KOH Potassium hydroxide
  • the exposed etch stop layer is then back surface passivated by depositing an insulating layer 117 of Silicon dioxide or Silicon dioxide plus nitride. This gives the lower surface 110 of the semiconductor layer 106 immunity against environmental attack. Although the insulating layer 117 could be grown, it is usually deposited at low temperature in order to avoid degradation of the electrical device.
  • an isolating region 118 is provided beneath the lower surface 110 at an external boundary of the semiconductor structure which is free from any conducting or semiconducting material (although it will be understood that there may be other regions beneath the lower surface which may contain electrical components or perhaps conducting strips connecting adjacent islands).
  • the islands 114 are generally completely isolated from each other, first by the isolating trenches 112 and secondly by a combination of the insulating layer 117 and the non-conducting ambient medium (usually air).
  • the areas 120 of the structure 10, peripheral of the isolating region 118, which have not been etched are used ⁇ or bonding the structure to a header (not shown).
  • Circuit bond pads 122 are located on the upper surface 108 of the thicker periphery of the semiconductor layer 106.
  • Cooling channels 124 for conveying coolant to the structure are formed in the peripheral areas 120.
  • a number of alternative cooling means may be employed.
  • metallic (for instance lead) columnar or nodal cooling fins may be deposited on the back of the structure, care being taken to ensure that the electric isolation of the islands is not impaired.
  • a dendritic coating of a noble metal might be employed, or Silicon could be anodised to form a porous layer on the back of the structure.
  • the semiconductor structure 10 in its eventual form constitutes a Silicon chip Integrated circuit having electrical devices formed on a thin (roughly 3.5 ⁇ m) Silicon membrane.
  • Figures 1 show schematically only a small number of electrical devices, the invention would typically be used to form VLSI circuits comprising many thousands or hundreds of thousands of electrical devices.
  • LT0 Temperature Silicon Oxide
  • the alternative embodiment of semiconductor structure comprises generally a Silicon slice 302 made of ⁇ 100> oriented Silicon, there being a hollow 303 formed in the top of the slice, and three beams 307 of semiconductor material spanning the hollow and constituting the semiconductor layer 306. Because the beams 307 are supported at both ends, they can be made thinner than in the original embodiment of semiconductor structure, shown in Figure 1; a typical thickness for the beams is l ⁇ m or less. Bonding pads (not shown) and the like are formed on the Silicon slice.
  • Figures 4(a) to 4(e) are schematic cross-sections taken along a longitudinal axis x-x of a beam 307
  • Figure 4(f) (which is not on the same scale as Figures 4(a) to 4(e)) is a schematic cross-section taken along axis y-y (and showing only two beams 307).
  • the production process commences (see Figure 4(a)) with the diffusion of a Boron etch stop layer 300 into the surface of a Silicon slice 302, which has a ⁇ 100> crystal orientation and may be p- or n- type.
  • the trench 309 is etched and refilled by the same techniques as described earlier In relation to Figures 1.
  • the perimeter trench is rectangular 1n plan view. It serves not only to provide dielectric isolation but also as an etch boundary, as is explained later.
  • an epitaxial layer 304 is grown on top of the etch stop layer 300 in the same way as described previously in relation to Figures 1. It is to be noted that the bulk of the epitaxial layer comprises single crystal silicon. However, that portion of the layer above the perimeter trench 309 is of Poly- crystalline Silicon because of the influence of the material of the trench on the epitaxial growth process.
  • a protective coating 305 of Low Temperature Silicon Oxide is formed on the upper surface 308 of the structure 10.
  • CMOS devices 316 are fabricated in the islands 314 formed by the refilled isolating trenches.
  • the trench fabrication and CMOS device fabrication is carried out as described in relation to Figures 1(c) and Kd).
  • the CMOS devices 316 are then coated with a protective layer 315, again in the manner described in relation to Figures 1.
  • trenches 317 parallel to the perimeter trench 309, adjacent but interior to that trench, are etched away from the upper surface 308 to, or somewhat beyond, the depth of the Boron etch stop layer 300 to define the sides of each beam 307. Note that, for clarity, only two beams are shown in Figure 4(f).
  • etch boundaries 319 are fabricated by passivating the sides of the beams 307 using Silicon nitride.
  • etching is then carried out, to undercut the beam 307 completely.
  • This etching is carried out using an anisotropic alkali etch such as Potassium Hydroxide, or possibly Ethylene Diamine, Pyrocathecol and Pyrazine, or other anisotropic etchants.
  • the etch boundary arrangement formed by the etch boundary 319 and perimeter trench 309 limits the lateral extent of this further etching.
  • the Boron etch stop layer 300 may be stripped away using an appropriate etchant.
  • the present invention has been described above purely by way of example, and modifications of detail can be made with the scope of the invention.
  • the semiconductor layer 306 being in the form of one or more beams 307, it could be in the form of one or more cantilevers (supported at only one end instead of both).
  • the cantilevers could be used, with appropriate electrical devices, to measure strain or acceleration.

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Abstract

Une structure à semiconducteur (10) comprend une couche d'un matériau semiconducteur (106) ayant une première et une seconde surfaces opposées (108, 110), un dispositif électrique (116) dont au moins une partie est adjacente à la première surface (108), et une barrière isolante (112) pour le dispositif électrique s'étendant à travers le matériau semiconducteur, vers la seconde surface (110), où se trouve une zone isolante (118) vers laquelle s'étend la barrière et où il n'y a pas de matériau non électro isolant entourant la barrière, la zone isolante étant en contact direct avec le milieu ambiant. Un procédé de fabrication de la structure à semiconducteur est également décrit, ainsi qu'une version alternative de la structure.
PCT/GB1994/000475 1993-03-17 1994-03-11 Structure a semiconducteur et procede pour fabriquer cette structure WO1994022167A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP94909181A EP0689719A1 (fr) 1993-03-17 1994-03-11 Structure a semiconducteur et procede pour fabriquer cette structure
JP6520752A JPH08507904A (ja) 1993-03-17 1994-03-11 半導体構造およびその製造方法
GB9518447A GB2290661B (en) 1993-03-17 1994-03-11 Semiconductor structure, and method of manufacturing same

Applications Claiming Priority (2)

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GB939305448A GB9305448D0 (en) 1993-03-17 1993-03-17 Semiconductor structure and method of manufacturing same
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WO2002025700A2 (fr) 2000-09-21 2002-03-28 Cambridge Semiconductor Limited Dispositif semi-conducteur et procede de fabrication
US6962792B1 (en) 1996-05-08 2005-11-08 Cyclacel Limited Methods and means for inhibition of Cdk4 activity
US7679160B2 (en) 2004-09-03 2010-03-16 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
US8017497B2 (en) 2009-02-10 2011-09-13 Freescale Semiconductor, Inc. Method for manufacturing semiconductor
US11049788B2 (en) 2019-10-18 2021-06-29 Microsoft Technology Licensing, Llc Integrated circuit chip device with thermal control

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WO1999036941A2 (fr) * 1998-01-15 1999-07-22 Cornell Research Foundation, Inc. Isolation en tranchee pour dispositifs micromecaniques
JP2011044667A (ja) * 2009-08-24 2011-03-03 Shin Etsu Handotai Co Ltd 半導体装置の製造方法
JP6237515B2 (ja) * 2014-07-17 2017-11-29 株式会社デンソー 圧力センサおよびその製造方法

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US6962792B1 (en) 1996-05-08 2005-11-08 Cyclacel Limited Methods and means for inhibition of Cdk4 activity
US6432792B1 (en) 1998-05-08 2002-08-13 Infineon Technologies Ag Substrate and method for manufacturing the same
WO1999059203A1 (fr) * 1998-05-08 1999-11-18 Infineon Technologies Ag Substrat et procede de fabrication correspondant
AU2001290068B2 (en) * 2000-09-21 2006-03-02 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
US6703684B2 (en) 2000-09-21 2004-03-09 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
US6900518B2 (en) 2000-09-21 2005-05-31 Cambridge Semiconductor Limited Semiconductor device
US6927102B2 (en) 2000-09-21 2005-08-09 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
WO2002025700A3 (fr) * 2000-09-21 2002-06-06 Cambridge Semiconductor Ltd Dispositif semi-conducteur et procede de fabrication
WO2002025700A2 (fr) 2000-09-21 2002-03-28 Cambridge Semiconductor Limited Dispositif semi-conducteur et procede de fabrication
RU2276429C2 (ru) * 2000-09-21 2006-05-10 Кембридж Семикондактор Лимитед Полупроводниковое устройство и способ формирования полупроводникового устройства
US7235439B2 (en) 2000-09-21 2007-06-26 Cambridge Semiconductor Limited Method of forming a MOS-controllable power semiconductor device for use in an integrated circuit
KR100841141B1 (ko) * 2000-09-21 2008-06-24 캠브리지 세미컨덕터 리미티드 반도체 장치 및 반도체 장치의 형성 방법
US7411272B2 (en) 2000-09-21 2008-08-12 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
US7679160B2 (en) 2004-09-03 2010-03-16 Cambridge Semiconductor Limited Semiconductor device and method of forming a semiconductor device
US8017497B2 (en) 2009-02-10 2011-09-13 Freescale Semiconductor, Inc. Method for manufacturing semiconductor
US11049788B2 (en) 2019-10-18 2021-06-29 Microsoft Technology Licensing, Llc Integrated circuit chip device with thermal control

Also Published As

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JPH08507904A (ja) 1996-08-20
GB9305448D0 (en) 1993-05-05
GB9518447D0 (en) 1995-11-08
GB2290661B (en) 1997-05-14
GB2290661A (en) 1996-01-03
EP0689719A1 (fr) 1996-01-03

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