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WO1996002122A1 - Electroless method of forming contact bumps - Google Patents

Electroless method of forming contact bumps Download PDF

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Publication number
WO1996002122A1
WO1996002122A1 PCT/FI1995/000392 FI9500392W WO9602122A1 WO 1996002122 A1 WO1996002122 A1 WO 1996002122A1 FI 9500392 W FI9500392 W FI 9500392W WO 9602122 A1 WO9602122 A1 WO 9602122A1
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WO
WIPO (PCT)
Prior art keywords
contact pad
pad areas
electroless
conducting layer
layer
Prior art date
Application number
PCT/FI1995/000392
Other languages
French (fr)
Inventor
Ahti Aintila
Original Assignee
Picopak Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FI943276A external-priority patent/FI943276A0/en
Application filed by Picopak Oy filed Critical Picopak Oy
Publication of WO1996002122A1 publication Critical patent/WO1996002122A1/en

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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Definitions

  • the invention is related to a method according to the preamble of claim 1 for forming contact bumps through an electroless deposition method.
  • Both the electroless zincate process and the electroless nickel process are very critical with regard to the correct process parameters of the baths.
  • the bath condi ⁇ tions can easily be adjusted for optimum results on a uniform aluminum surface having known properties. In practice, however, it is the wafer manufacturer and layout designer that set the constraints as regards variations of surface quality and alloying of aluminum, geometry and internal leakage paths between the pads.
  • this protective coating greatly reduces the difficulties caused by electrochemical corrosion currents and related potential differences between the pads and the substrate material in electroless nickel bumping. In most cases good results have been achieved.
  • this process may be called “maskless", because no exposure of the resist through a mask is needed.
  • the maskless process Since the time of the first experiments, the maskless process has recently become more complicated to use, because in modern wafer processes a great number of test pads are placed close to the dicing lanes. If not masked out by a photoresist layer, bumps around the dice would form a potential short circuit in the bonding operation. For this practical matter, the benefits of a maskless process have been abandoned, and instead, the use of a photolithographically patterned, thin, protective coating on the active side of the wafer has been adopted.
  • the mask alignment is not critical, because large free areas around the contact pads are desirable for lateral growth. This practice has considerably widened the process window, because now less silicon substrate area is exposed to the electrolyte.
  • the goal of the invention is achieved by depositing a thin seed metal film onto the wafer prior to the bumping process.
  • the invention offers significant benefits.
  • the process according to the invention involves more processing steps and material costs than a normal maskless, electroless bumping process, it has the benefit of saving process analyzing and control costs and facilitating denser bumping through improved control of bump height variation as compared with the results of galvanic plating processes. Furthermore, the method according to the invention can be applied to any layouts and any internal circuits with wide variations in the pad alloy materials.
  • Figure 1 is a longitudinally sectioned side view of bump structures formed using prior-art electroless processes
  • Figure 2 is a longitudinally sectioned side view of a third bump structure formed using a prior-art process
  • Figure 3 is a longitudinally sectioned side view of a process step of the method according to the invention.
  • Figures 4a - 4e are longitudinally sectioned side views of different process steps of the method according to the invention.
  • the bumps are formed onto a substrate 1 conventionally made from silicon.
  • a passiva ⁇ tion layer 3 is deposited to prevent short circuits between the bumps.
  • the passiva ⁇ tion layer 3 is typically of silicon dioxide.
  • a zinc layer 4 is formed onto the aluminum contact pad areas 2.
  • the actual contact bumps 5 are formed onto the zinc layer 4 using an electroless process, and to improve the electrical contact, the bumps are further coated with a gold layer 6.
  • the nickel layer 5 of the left-side bump in the diagram has a thickness of 20 ⁇ m with the gold layer 6 having a thickness of 0.1 ⁇ m.
  • the nickel layer 5 of the right-side bump has a thickness of 16 ⁇ m with the gold layer 6 having a thickness of 4 ⁇ m.
  • the embodiment illustrated therein has in accordance with prior-art techniques a thin photoresist 10 placed on the wafer with a pattern protecting the electroless process from the disturbing effect of test pads and dicing lanes.
  • a process step of the method according to the invention is shown having the passivation layer 3 coated over the entire area of the wafer by a continuous, thin seed metal layer 7 in order to form a constant potential surface.
  • a suitable material for the metallic layer 7 is aluminum, for instance.
  • the nickel bumps 9 are now formed onto areas where the photoresist 8 is patterned for bumping holes. By virtue of this approach, the bumps 9 are formed with steep sides.
  • the photoresist is removed and the metallic layer 7 is etched away. Also the bump 9 is subjected to etching during this process step, this, however, involving no practical meaning as the ratio of height of the bump 9 to the thickness of the seed metal layer 7 typically is in the order of approx.
  • the thickness of the seed metal layer 7 is typically approx. 10 - 100 nm, advantageously approx. 50 nm.
  • the first step of the method according to the invention comprises sputtering a thin metallic layer 7 onto contact pad areas 2 and the passivation layer 3 on the substrate 1.
  • the photoresist 8 is formed about the contact pad areas 2 using conventional photolithography methods.
  • the holes made to the photoresist 8 are made slightly larger than those of the contact pad areas 2.
  • the bumps 9 are formed to a height of approx. 25 ⁇ m using an electroless process.
  • the photoresist is removed and the metallic layer 7 is etched away as shown in Fig. 4e.
  • a uniform but very thin "seed" layer 7 is sputtered on the wafer to hold all the contact pad areas at the same potential and to standardize the surface layer of the wafer 1 to a known alloy for more practical plating process parameter settings.
  • the metallic layer 7 is made of aluminum, while other materials may offer more interesting benefits, like zinc as an active catalyst to initiate the electroless nickel process.
  • a full photolithography process has to be carried out using a thick photoresist layer 8 with vertical sidewalls. The purpose of the high vertical sidewalls is to prevent the lateral growth of nickel.
  • the photoresist is removed.
  • the seed metal layer 7 is etched away.
  • a zincate process is preferred to a palladium process as the pretreatment preceding the electroless process.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention relates to a method of forming contact bumps (9) on metallic contact pad areas (2) on the surface of a substrate (1) by means of an electroless process, in which method a passivation layer (3) is formed onto the substrate (1) and partially onto the contact pad areas (2) in order to minimize galvanic currents. According to the invention, after forming the passivation layer (3), the entire substrate (1) is coated with a thin conducting layer (7), the conducting layer (7) is covered by a photoresist (8) with the exclusion of said contact pad areas (2), contact bumps (9) are formed onto the contact pad areas (2) using an electroless method, the photoresist (8) is removed, and the conducting layer (7) is etched away.

Description

Electroless method of forming contact bumps
The invention is related to a method according to the preamble of claim 1 for forming contact bumps through an electroless deposition method.
As discussed in a plurality of prior-art publications [1-5], selective nickel deposition on aluminum bonding pads can be initiated after a palladium or zincate treatment. Typically the maskless process gives an almost isotropic metal deposition with slightly less lateral growth than the height of the bump due to less chemical reaction activity along the edge of the bump. The result is a smooth bump with rounded sides. Conventionally, the number of such bumps formed onto a single silicon wafer is from hundreds to thousands.
Both the electroless zincate process and the electroless nickel process are very critical with regard to the correct process parameters of the baths. The bath condi¬ tions can easily be adjusted for optimum results on a uniform aluminum surface having known properties. In practice, however, it is the wafer manufacturer and layout designer that set the constraints as regards variations of surface quality and alloying of aluminum, geometry and internal leakage paths between the pads.
After forming contact bumps on a number of different kind of wafers from many
( manufacturers, it appears that no single set of parameters can be predicted. Even the variations between wafers of one and the same lot may need individual fine tuning of the process. The phenomena reported by A.M.T. van der Putten et al. [6-7] have been verified. Said phenomena are related to stabilizer poisoning around very small pads and at the edges of large pads where the chemical activity is low. Starting from the very first experiments, the applicants have been using protective photoresist coating on the back side and edges of the wafer as suggest¬ ed by R. Sard and Y. Okinaka et al. [8-9] for preventing uneven growth of dif- ferent contact pad areas in electroless gold plating. As reported later by J. Simon et al. [10-11], this protective coating greatly reduces the difficulties caused by electrochemical corrosion currents and related potential differences between the pads and the substrate material in electroless nickel bumping. In most cases good results have been achieved. Despite the protective photoresist used, this process may be called "maskless", because no exposure of the resist through a mask is needed.
Since the time of the first experiments, the maskless process has recently become more complicated to use, because in modern wafer processes a great number of test pads are placed close to the dicing lanes. If not masked out by a photoresist layer, bumps around the dice would form a potential short circuit in the bonding operation. For this practical matter, the benefits of a maskless process have been abandoned, and instead, the use of a photolithographically patterned, thin, protective coating on the active side of the wafer has been adopted. Here, the mask alignment is not critical, because large free areas around the contact pads are desirable for lateral growth. This practice has considerably widened the process window, because now less silicon substrate area is exposed to the electrolyte.
Even after all these precautions, however, there are still difficulties with electro¬ chemical potential differences between different pads of the most critical wafers. There seem to be several reasons for the potential variations: a) the potential change due to the electrochemical reaction is smaller if the pads are connected to large internal metal areas or internal capacitors (power supply and filter capacitor pads), b) uneven leakage resistances and/or threshold voltages across pn junctions, and c) alloying profile of pad metallization over the entire wafer or local "impurity" diffusion to the pad from the underlying structure.
As an example of the electrochemical sensitivity to minute alloying differences, a partial list is given below of the corrosion potentials of different materials in a 2000 ppm NH4C1 solution, A.J. Griffin et al. [12]: Al-Cu 0.5%-Si 1% on CVD W -6 mV
Al-Cu 2%-Si 1% -171 mV
Al-Cu 2% -368 mV
Si (bare wafer) -722 mV
Al-Si 1% on CVD W -783 mV
Al on CVD W -800 mV
Al on W-Ti 10% -948 mV
Al -1030 mV
It is plausible to assume that microscopic unevenness of the composition of the alloying material can cause local corrosion within the area of a single pad and thus invoke the disturbances in the electroless plating process.
It is an object of the present invention to overcome the drawbacks of the above- described techniques and to achieve an entirely novel type of method for forming contact bumps through an electroless deposition method.
The goal of the invention is achieved by depositing a thin seed metal film onto the wafer prior to the bumping process.
More specifically, the method according to the invention is characterized by what is stated in the characterizing part of claim 1.
The invention offers significant benefits.
Although the process according to the invention involves more processing steps and material costs than a normal maskless, electroless bumping process, it has the benefit of saving process analyzing and control costs and facilitating denser bumping through improved control of bump height variation as compared with the results of galvanic plating processes. Furthermore, the method according to the invention can be applied to any layouts and any internal circuits with wide variations in the pad alloy materials.
In the following, the invention will be examined in more detail by means of exemplifying embodiments with reference to the attached drawings, in which:
Figure 1 is a longitudinally sectioned side view of bump structures formed using prior-art electroless processes;
Figure 2 is a longitudinally sectioned side view of a third bump structure formed using a prior-art process;
Figure 3 is a longitudinally sectioned side view of a process step of the method according to the invention; and
Figures 4a - 4e are longitudinally sectioned side views of different process steps of the method according to the invention.
Referring to Fig. 1, the bumps are formed onto a substrate 1 conventionally made from silicon. On the substrate 1 are located aluminum contact pad areas 2 on which nickel bumps 5 are formed. Prior to forming the nickel bumps, a passiva¬ tion layer 3 is deposited to prevent short circuits between the bumps. The passiva¬ tion layer 3 is typically of silicon dioxide. During the zincate treatment step, a zinc layer 4 is formed onto the aluminum contact pad areas 2. The actual contact bumps 5 are formed onto the zinc layer 4 using an electroless process, and to improve the electrical contact, the bumps are further coated with a gold layer 6. The nickel layer 5 of the left-side bump in the diagram has a thickness of 20 μm with the gold layer 6 having a thickness of 0.1 μm. Correspondingly, the nickel layer 5 of the right-side bump has a thickness of 16 μm with the gold layer 6 having a thickness of 4 μm. Referring to Fig. 2, the embodiment illustrated therein has in accordance with prior-art techniques a thin photoresist 10 placed on the wafer with a pattern protecting the electroless process from the disturbing effect of test pads and dicing lanes.
Referring to Fig. 3, a process step of the method according to the invention is shown having the passivation layer 3 coated over the entire area of the wafer by a continuous, thin seed metal layer 7 in order to form a constant potential surface. A suitable material for the metallic layer 7 is aluminum, for instance. The nickel bumps 9 are now formed onto areas where the photoresist 8 is patterned for bumping holes. By virtue of this approach, the bumps 9 are formed with steep sides. During the next step, the photoresist is removed and the metallic layer 7 is etched away. Also the bump 9 is subjected to etching during this process step, this, however, involving no practical meaning as the ratio of height of the bump 9 to the thickness of the seed metal layer 7 typically is in the order of approx.
1: 100 - 1:1000. The thickness of the seed metal layer 7 is typically approx. 10 - 100 nm, advantageously approx. 50 nm.
Referring to Fig. 4a, the first step of the method according to the invention comprises sputtering a thin metallic layer 7 onto contact pad areas 2 and the passivation layer 3 on the substrate 1.
Referring to Fig. 4b, the photoresist 8 is formed about the contact pad areas 2 using conventional photolithography methods. The holes made to the photoresist 8 are made slightly larger than those of the contact pad areas 2.
Referring to Fig. 4c, the bumps 9 are formed to a height of approx. 25 μm using an electroless process.
Referring to Fig. 4d, the photoresist is removed and the metallic layer 7 is etched away as shown in Fig. 4e. In order to minimize the geometrical (= capacitance), internal circuitry and alloying difference effects, a uniform but very thin "seed" layer 7 is sputtered on the wafer to hold all the contact pad areas at the same potential and to standardize the surface layer of the wafer 1 to a known alloy for more practical plating process parameter settings. Typically, the metallic layer 7 is made of aluminum, while other materials may offer more interesting benefits, like zinc as an active catalyst to initiate the electroless nickel process. After the seed metallization step, a full photolithography process has to be carried out using a thick photoresist layer 8 with vertical sidewalls. The purpose of the high vertical sidewalls is to prevent the lateral growth of nickel. When the nickel layer 9 has reached a sufficient thickness, typically 25 μm, the photoresist is removed. As the last step, the seed metal layer 7 is etched away.
According to the invention, a zincate process is preferred to a palladium process as the pretreatment preceding the electroless process.
References
1. K. Wong et al., Application of Electroless Nickel Plating in the Semiconductor
Microcircuit Industry, Plating and Surface Finishing, pp. 70-76, July 1988. 2. K. Yamakawa et al., Maskless Bumping by Electroless Plating for High Pin Count, Thin, and Low Cost Microcircuits, presented at the 1989 International Symposium on Hybrid
Microelectronics, Baltimore, Maryland, October 24-26, 1989. 3. J. Simon et al., Electroless Deposition of Bumps for TAB technology, Proc. 40th ECTC,
Las Vegas 1990. 4. J. Liu, Development of a Cost-effective and Flexible Bumping Method for Flip-chip
Interconnections, Hybrid Circuits, No. 29, September 1992. 5. A. Aintila et al., Towards Low Cost High Density Bumping, Proc. 1993 Japan
International Electronic Manufacturing Technology Symposium, June 9-11, 1993,
Kanazawa, Japan, pp. 33-36. 6. A.M.T. van der Putten et al., Geometrical Effects in the Electroless Metallization of Fine
Metal Patterns, J. Electrochem. Soc, Vol. 140, No. 8, pp. 2221-2228, August 1993. 7. A.M.T. van der Putten et al., Anisotropic Deposition of Electroless Nickel, J.
Electrochem. Soc, Vol. 140, No. 8, pp. 2229-2235, August 1993. 8. R. Sard, et al., Electroless Gold Lead Plating, J. Electrochem. Soc, Vol. 121, No. 1 , pp. 62-66, January 1974.
9. Y. Okinaka, et al.. Some Practical Aspects of Electroless Gold Plating, J. Electrochem. Soc, Vol. 121, No. 1, pp. 56-62, January 1974. 10. J. Simon et al., Proc 1993 International Symposium on Microelectronics, Dallas, Texas,
November 1993, pp. 439-444. 11. A. Ostmann et al., Alternative Metallization by Low Cost Electroless Plating for MCM
Applications, Workshop on MCM and VLSI Packaging Techniques and Manufacturing Techniques, 8-10 June 1994, near Windsor, England. 12. A.J. Griffin, Jr. et al., A Galvanic Series for Thin-Film Metallizations and Barrier Layers
Commonly Used in the Microelectronics Industry, J. Electrochem. Soc, Vol. 141, No. 3, pp. 807-809, March 1974.

Claims

Claims:
1. A method for forming contact bumps (9) on metallic contact pad areas (2) on the surface of a substrate (1) by means of an electroless process, in which method
- a passivation layer (3) is formed onto the substrate (1) and partially onto the contact pad areas (2) in order to minimize galvanic currents,
characterized in that
- after forming the passivation layer (3), the entire substrate (1) is coated with a thin conducting layer (7),
- the conducting layer (7) is covered by a photoresist (8) with the exclusion of said contact pad areas (2),
- contact bumps (9) are formed onto the contact pad areas (2) using an electroless method,
- the photoresist (8) is removed, and
- the conducting layer (7) is etched away.
2. A method as defined in claim 1, in which method the contact pad areas (2) are subjected to zincate treatment (4), characterized in that the conducting layer (7) is made of aluminum.
3. A method as defined in claim l or2, characterized in that the conducting layer (7) is made of zinc.
4. A method as defined in claim 1, in which method the contact pad areas (2) are subjected to zincate treatment (4), characterized in that the conducting layer (7) is formed with a thickness of 10 - 100 nm, advantageously approx. 50 nm.
PCT/FI1995/000392 1994-07-08 1995-07-06 Electroless method of forming contact bumps WO1996002122A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FI943276A FI943276A0 (en) 1994-07-08 1994-07-08 Electroless-foil Foer bildning av kontaktstudsar
FI943276 1994-07-08
FI946015A FI946015L (en) 1994-07-08 1994-12-21 Electroless contact nodule formation method
FI946015 1994-12-21

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Cited By (5)

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Publication number Priority date Publication date Assignee Title
WO1997015070A3 (en) * 1995-10-16 1997-06-12 Picopak Oy Fabrication method and contact bump structure for high-density surface-mount connections of solid-state device chips
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
DE102004019445A1 (en) * 2004-04-19 2005-11-03 Siemens Ag With planar connection technology on a particular electrically conductive substrate constructed circuit
DE102004047730A1 (en) * 2004-09-30 2006-04-06 Advanced Micro Devices, Inc., Sunnyvale A method for thinning semiconductor substrates for the production of thin semiconductor wafers

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US4182781A (en) * 1977-09-21 1980-01-08 Texas Instruments Incorporated Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating
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US4182781A (en) * 1977-09-21 1980-01-08 Texas Instruments Incorporated Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit

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PROC. INTERNATIONAL ELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM, 9-11 June 1993, Kanazawa, Japan, A. AINTILA et al., "Towards Low Cost High Density Bumping", pp. 33-36. *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997015070A3 (en) * 1995-10-16 1997-06-12 Picopak Oy Fabrication method and contact bump structure for high-density surface-mount connections of solid-state device chips
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
DE19616373A1 (en) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Forming galvanically deposited contact bumps for integrated circuits
DE102004019445A1 (en) * 2004-04-19 2005-11-03 Siemens Ag With planar connection technology on a particular electrically conductive substrate constructed circuit
DE102004047730A1 (en) * 2004-09-30 2006-04-06 Advanced Micro Devices, Inc., Sunnyvale A method for thinning semiconductor substrates for the production of thin semiconductor wafers
US7375032B2 (en) 2004-09-30 2008-05-20 Advanced Micro Devices, Inc. Semiconductor substrate thinning method for manufacturing thinned die
DE102004047730B4 (en) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. A method for thinning semiconductor substrates for the production of thin semiconductor wafers

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FI946015A0 (en) 1994-12-21
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