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WO1996002122A1 - Procede par immersion pour former des bosses de contact - Google Patents

Procede par immersion pour former des bosses de contact Download PDF

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Publication number
WO1996002122A1
WO1996002122A1 PCT/FI1995/000392 FI9500392W WO9602122A1 WO 1996002122 A1 WO1996002122 A1 WO 1996002122A1 FI 9500392 W FI9500392 W FI 9500392W WO 9602122 A1 WO9602122 A1 WO 9602122A1
Authority
WO
WIPO (PCT)
Prior art keywords
contact pad
pad areas
electroless
conducting layer
layer
Prior art date
Application number
PCT/FI1995/000392
Other languages
English (en)
Inventor
Ahti Aintila
Original Assignee
Picopak Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FI943276A external-priority patent/FI943276A0/fi
Application filed by Picopak Oy filed Critical Picopak Oy
Publication of WO1996002122A1 publication Critical patent/WO1996002122A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L24/03—Manufacturing methods
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2924/01005—Boron [B]
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    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/0103—Zinc [Zn]
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01039—Yttrium [Y]
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    • H01L2924/01046—Palladium [Pd]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/1904—Component type
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    • H01L2924/30105—Capacitance

Definitions

  • the invention is related to a method according to the preamble of claim 1 for forming contact bumps through an electroless deposition method.
  • Both the electroless zincate process and the electroless nickel process are very critical with regard to the correct process parameters of the baths.
  • the bath condi ⁇ tions can easily be adjusted for optimum results on a uniform aluminum surface having known properties. In practice, however, it is the wafer manufacturer and layout designer that set the constraints as regards variations of surface quality and alloying of aluminum, geometry and internal leakage paths between the pads.
  • this protective coating greatly reduces the difficulties caused by electrochemical corrosion currents and related potential differences between the pads and the substrate material in electroless nickel bumping. In most cases good results have been achieved.
  • this process may be called “maskless", because no exposure of the resist through a mask is needed.
  • the maskless process Since the time of the first experiments, the maskless process has recently become more complicated to use, because in modern wafer processes a great number of test pads are placed close to the dicing lanes. If not masked out by a photoresist layer, bumps around the dice would form a potential short circuit in the bonding operation. For this practical matter, the benefits of a maskless process have been abandoned, and instead, the use of a photolithographically patterned, thin, protective coating on the active side of the wafer has been adopted.
  • the mask alignment is not critical, because large free areas around the contact pads are desirable for lateral growth. This practice has considerably widened the process window, because now less silicon substrate area is exposed to the electrolyte.
  • the goal of the invention is achieved by depositing a thin seed metal film onto the wafer prior to the bumping process.
  • the invention offers significant benefits.
  • the process according to the invention involves more processing steps and material costs than a normal maskless, electroless bumping process, it has the benefit of saving process analyzing and control costs and facilitating denser bumping through improved control of bump height variation as compared with the results of galvanic plating processes. Furthermore, the method according to the invention can be applied to any layouts and any internal circuits with wide variations in the pad alloy materials.
  • Figure 1 is a longitudinally sectioned side view of bump structures formed using prior-art electroless processes
  • Figure 2 is a longitudinally sectioned side view of a third bump structure formed using a prior-art process
  • Figure 3 is a longitudinally sectioned side view of a process step of the method according to the invention.
  • Figures 4a - 4e are longitudinally sectioned side views of different process steps of the method according to the invention.
  • the bumps are formed onto a substrate 1 conventionally made from silicon.
  • a passiva ⁇ tion layer 3 is deposited to prevent short circuits between the bumps.
  • the passiva ⁇ tion layer 3 is typically of silicon dioxide.
  • a zinc layer 4 is formed onto the aluminum contact pad areas 2.
  • the actual contact bumps 5 are formed onto the zinc layer 4 using an electroless process, and to improve the electrical contact, the bumps are further coated with a gold layer 6.
  • the nickel layer 5 of the left-side bump in the diagram has a thickness of 20 ⁇ m with the gold layer 6 having a thickness of 0.1 ⁇ m.
  • the nickel layer 5 of the right-side bump has a thickness of 16 ⁇ m with the gold layer 6 having a thickness of 4 ⁇ m.
  • the embodiment illustrated therein has in accordance with prior-art techniques a thin photoresist 10 placed on the wafer with a pattern protecting the electroless process from the disturbing effect of test pads and dicing lanes.
  • a process step of the method according to the invention is shown having the passivation layer 3 coated over the entire area of the wafer by a continuous, thin seed metal layer 7 in order to form a constant potential surface.
  • a suitable material for the metallic layer 7 is aluminum, for instance.
  • the nickel bumps 9 are now formed onto areas where the photoresist 8 is patterned for bumping holes. By virtue of this approach, the bumps 9 are formed with steep sides.
  • the photoresist is removed and the metallic layer 7 is etched away. Also the bump 9 is subjected to etching during this process step, this, however, involving no practical meaning as the ratio of height of the bump 9 to the thickness of the seed metal layer 7 typically is in the order of approx.
  • the thickness of the seed metal layer 7 is typically approx. 10 - 100 nm, advantageously approx. 50 nm.
  • the first step of the method according to the invention comprises sputtering a thin metallic layer 7 onto contact pad areas 2 and the passivation layer 3 on the substrate 1.
  • the photoresist 8 is formed about the contact pad areas 2 using conventional photolithography methods.
  • the holes made to the photoresist 8 are made slightly larger than those of the contact pad areas 2.
  • the bumps 9 are formed to a height of approx. 25 ⁇ m using an electroless process.
  • the photoresist is removed and the metallic layer 7 is etched away as shown in Fig. 4e.
  • a uniform but very thin "seed" layer 7 is sputtered on the wafer to hold all the contact pad areas at the same potential and to standardize the surface layer of the wafer 1 to a known alloy for more practical plating process parameter settings.
  • the metallic layer 7 is made of aluminum, while other materials may offer more interesting benefits, like zinc as an active catalyst to initiate the electroless nickel process.
  • a full photolithography process has to be carried out using a thick photoresist layer 8 with vertical sidewalls. The purpose of the high vertical sidewalls is to prevent the lateral growth of nickel.
  • the photoresist is removed.
  • the seed metal layer 7 is etched away.
  • a zincate process is preferred to a palladium process as the pretreatment preceding the electroless process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé pour former des bosses de contact (9) sur des régions de plot de contact métallique (2) à la surface d'un substrat (1) à l'aide d'un processus par immersion. Dans ce procédé, une couche de passivation (3) est formée sur le substrat (1) et partiellement sur les régions de plot de contact (2) afin de réduire au minimum les courants galvaniques. Après formation de cette couche de passivation (3), le substrat (1) tout entier est revêtu d'une fine couche conductrice (7), laquelle est recouverte d'un photorésist (8) à l'exclusion desdites régions de plot de contact (2), des bosses de contact (9) sont formées sur les régions de plot de contact (2) à l'aide d'un procédé par immersion, le photorésist (8) est éliminé, et la couche conductrice (7) est éliminée par gravure.
PCT/FI1995/000392 1994-07-08 1995-07-06 Procede par immersion pour former des bosses de contact WO1996002122A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FI943276A FI943276A0 (fi) 1994-07-08 1994-07-08 Elektroless-foerfarande foer bildning av kontaktstudsar
FI943276 1994-07-08
FI946015A FI946015L (fi) 1994-07-08 1994-12-21 Electroless-kontaktinystynmuodostusmenetelmä
FI946015 1994-12-21

Publications (1)

Publication Number Publication Date
WO1996002122A1 true WO1996002122A1 (fr) 1996-01-25

Family

ID=26159774

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1995/000392 WO1996002122A1 (fr) 1994-07-08 1995-07-06 Procede par immersion pour former des bosses de contact

Country Status (2)

Country Link
FI (1) FI946015L (fr)
WO (1) WO1996002122A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997015070A3 (fr) * 1995-10-16 1997-06-12 Picopak Oy Technique de fabrication et structure de bosse de contact pour connexions a haute densite et a montage en surface de microplaquettes a semi-conducteurs
DE19616373A1 (de) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Herstellung galvanisch abgeformter Kontakthöcker
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
DE102004019445A1 (de) * 2004-04-19 2005-11-03 Siemens Ag Mit planarer Verbindungstechnik auf einem insbesondere elektrischleitendem Substrat aufgebaute Schaltung
DE102004047730A1 (de) * 2004-09-30 2006-04-06 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4182781A (en) * 1977-09-21 1980-01-08 Texas Instruments Incorporated Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4182781A (en) * 1977-09-21 1980-01-08 Texas Instruments Incorporated Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating
US5226232A (en) * 1990-05-18 1993-07-13 Hewlett-Packard Company Method for forming a conductive pattern on an integrated circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PROC. 40TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 1990, Las Vegas, USA, J. SIMON et al., "Electroless Deposition of Bumps for TAB Technology", pp. 412-417. *
PROC. INTERNATIONAL ELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM, 9-11 June 1993, Kanazawa, Japan, A. AINTILA et al., "Towards Low Cost High Density Bumping", pp. 33-36. *

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997015070A3 (fr) * 1995-10-16 1997-06-12 Picopak Oy Technique de fabrication et structure de bosse de contact pour connexions a haute densite et a montage en surface de microplaquettes a semi-conducteurs
US5989993A (en) * 1996-02-09 1999-11-23 Elke Zakel Method for galvanic forming of bonding pads
DE19616373A1 (de) * 1996-04-24 1997-08-14 Fraunhofer Ges Forschung Herstellung galvanisch abgeformter Kontakthöcker
DE102004019445A1 (de) * 2004-04-19 2005-11-03 Siemens Ag Mit planarer Verbindungstechnik auf einem insbesondere elektrischleitendem Substrat aufgebaute Schaltung
DE102004047730A1 (de) * 2004-09-30 2006-04-06 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen
US7375032B2 (en) 2004-09-30 2008-05-20 Advanced Micro Devices, Inc. Semiconductor substrate thinning method for manufacturing thinned die
DE102004047730B4 (de) * 2004-09-30 2017-06-22 Advanced Micro Devices, Inc. Ein Verfahren zum Dünnen von Halbleitersubstraten zur Herstellung von dünnen Halbleiterplättchen

Also Published As

Publication number Publication date
FI946015A7 (fi) 1996-01-09
FI946015A0 (fi) 1994-12-21
FI946015L (fi) 1996-01-09

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