WO1996003807A1

WO1996003807A1 - Digital circuit topology offering an improved power delay product

Info

Publication number: WO1996003807A1
Application number: PCT/US1995/009349
Authority: WO
Inventors: Graham Y. Mostyn; William H. Herndon; John P. Moussouris; Timothy B. Robinson; Geert P. Rosseel
Original assignee: Microunity Systems Engineering, Inc.
Priority date: 1994-07-25
Filing date: 1995-07-25
Publication date: 1996-02-08
Also published as: AU3144395A

Abstract

The present invention is an improvement of a digital topology including a logic block portion and a buffer portion. The improved buffer portion of the present invention is implemented with first and second parallel, same conductivity type transmission gates. The transmission gates couple either a first (V1) or second (V2) voltage onto the output of the buffer (55) in response to a logic signal originating from the logic block portion. The first (V1) and second (V2) voltages are selected to be relatively close in magnitude such that the peak-to-peak voltage of the digital output signal seen on the output of the buffer is relatively small. As a result, power consumption for charging the output of the buffer is minimized. In addition, the parallel transmission gates only consume power while charging the output of the buffer so that quiescent power consumption of the buffer is eliminated. Quiescent power dissipation is also eliminated in certain types of logic block designs that include logic gates having constant current sources. This is achieved by enabling the current sources with a pulse signal. The pulse width and magnitude of the pulse signal is selected to allow a latched sense amplifier to sense valid data from the output of the logic block portion during a specified interval. After valid data is sensed, the logic blocks's current sources are disabled, and the logic block portion no longer consumes any power. The sense amplifier is enabled for intervals long enough to capture the data from the logic block and drive the transmission gates with the data. In this configuration, none of the elements in the topology dissipate quiescent power since none of them are constantly operating.

Description

DIGITAL CIRCUIT TOPOLOGY OFFERING AN IMPROVED POWER DELAY PRODUCT

FIELD OF THE INVENTION

The present invention relates to the field of digital circuit design and particularly to the power characteristics of digital circuit topologies.

BACKGROUND OF THE INVENTION

In a large digital circuit design, often times there are smaller circuit structures or topologies that are repeated throughout the larger circuit. One particularly common circuit topology includes two portions, a core logic portion (50) and a line driver or buffer portion (53), as shown in

Figure 1. Often times core logic portion 50 comprises many logic gates such as AND or OR gates. In addition, core logic 50 may comprise memory cell devices. In either case, the core logic portion performs some logical function in response to digital input signal/signals 49, and outputs intermediate digital signal 51. Because the core logic portion typically comprises low current logic gates, the core logic portion has low current drive capability and cannot drive high capacitance loads.

Intermediate signal 51 is coupled to buffer 53. Generally, buffer 53 is located relatively close to core logic 50 such that interconnect lines are relatively short. As a result, buffer 53 represents a relatively small amount of capacitive loading to core logic 50 due to interconnect line capacitance. Buffer 53 functions to boost the current level of intermediate signal 51 so as to enable charging a highly capacitive load (56). Capacitive load 56 typically represents a long interconnect line coupled to another core logic portion or possibly an integrated circuit input/output pad.

The core logic/buffer topology shown in Figure 1 may be designed with many types of logic gates. One commonly utilized type of logic gate comprises complementary devices (such as complementary metal oxide silicon (CMOS) devices). Referring to Figure 2A, this type of gate consists of complementary switches 16 and 17 that connect either a positive or negative supply voltage (VDD and VSS) to capacitive load 21 in response to input signal 20.

Figure 2C shows VOUT (Figure 2A) for a square wave input signal V20 that alternates between VDD and VSS. As can be seen in Figure 2C, VOUT transitions between VDD and VSS, making the peak-to-peak voltage (Vp-p) swing of the digital signal at the output of the logic gate equal to the difference between the positive and negative supply voltages, (VDD - VSS). In the field of digital circuit design this Vp-p voltage is considered to be relatively large when compared with other available logic gate designs.

Figure 2B illustrates a complementary-type logic gate implemented with CMOS devices. The Vp-p for this logic gate is typically 3.0 - 5.0 Vp- p. Basically, the logic gate shown in Figure 2B functions such that when input signal 20 is a high voltage, device 17 is on and device 16 is off. In this state VOUT is coupled to VSS. When input signal 20 is a low voltage, device 17 is off and device 16 is on. When this occurs, VOUT is coupled to VDD.

The complementary-type logic gate shown in Figure 2A dissipates power only during state transitions, i.e. when charging load 21. This feature makes the complementary-type logic gate very power efficient when it is not switching states very frequently. However, since this type of logic gate outputs a signal having a relatively large Vp-p, the amount of power dissipated to drive a capacitive load is relatively high when compared to other logic gates, particularly when the capacitive load is large. As described above, buffer 13 drives a relatively large capacitive load. Consequently, buffers, (such as buffer 13), implemented with complementary-type logic gates become very power inefficient when they are switched relatively frequently. Another type of logic gate that is utilized to implement the circuit topology illustrated in Figure 1 is shown in Figure 3A. A gate designed in this manner typically has a current source (22) coupled between a first working potential (23) and two matched parallel discrete devices (24 and 25). Reference voltage, VI, provides the drive for current source 22 so that it supplies a constant current. Each one of a pair of identical loads (26 and 27) are coupled between one of the matched devices and a second working potential (28). Input signals, Vin and Vin/, are coupled to each of the inputs of matched devices 24 and 25. The output of the gate is taken at either one or both of lines 30 and 31 (depending on whether a single-ended signal or a differential signal is desired). Since Vin and Vin/ are the inverse of each other, one device has a voltage corresponding to a high logic state on its input and the other has a voltage corresponding to a low logic state on its input. As a result, one device is on and the other is off. When this occurs, most of the current supplied by current source 22 is routed through the on-device and its respective load device, while relatively no current flows through the off- device and its respective load. Consequently, a larger voltage is developed across one load device than the other. For example, if all of the current is routed through device 25 and load 27, output line 30 is at a voltage that represents a logical high state and output line 31 is at a voltage that represents a logical low state. Referring to Figure 3C, the difference between the logic high and low voltages is the peak-to-peak voltage swing of the logic gate. The magnitude of the Vp-p for the logic gate shown in Figure 3A is determined by the amount of current flowing through the resistive load and the resistance of each load. Consequently, it is possible to select the Vp-p swing of this gate such that it is relatively small. In particular, the Vp-p voltage of the logic gate shown in Figure 3A is typically selected to be less than the Vp-p of the complementary-type logic gate shown in Figure 2B. One widely utilized example of the logic gate shown in Figure 3A is the emitter-coupled logic (ECL) gate, shown in Figure 3B. The Vp-p of a typical ECL logic gate is approximately 0.50 volts. In contrast to the complementary-type logic gate, the logic gate shown in Figure 3A characteristically has a quiescent power consumption due to constant current source 22. Thus, even when it is not switching states, it is dissipating power. However, due to its relatively small Vp-p swing, the logic gate shown in Figure 3A dissipates relatively less power to charge/discharge a given capacitive load than the complementary-type logic gate - especially when the given capacitive load is relatively large. Hence, when buffer 13 (Figure 1) is implemented in ECL-type of logic gates (as shown in Figures 3A and 3B), it is more power efficient than the complementary-type logic gate when the logic gate is frequently switched - but is less power efficient when it is switching relatively infrequently due to its quiescent power dissipation feature.

In comparing the power characteristics of the two logic types, it is evident that the complementary-type of logic gate performs optimally when it is switching infrequently, whereas ECL-type of logic performs best when it is switching frequently.

In designing an integrated circuit topology as shown in Figure 1 , the above described logic gate types are selected so that the overall power, speed and area characteristics of a circuit are optimized. The space/area consideration further relates to the ultimate cost of the integrated circuit. In the past, this topology has been designed with generally either all complementary-type logic gates or all logic gates having quiescent power consumption. However, if the topology shown in Figure 1 requires logic gates to switch both frequently and infrequently over different periods of time, depending on input conditions, neither complementary logic nor logic with quiescent consumption represent an optimum power design solution. In particular, power issues are particularly crucial when designing buffer 13 since it drives a relatively large capacitive load and tends to dissipate a large percentage of the overall power of the topology. The present invention is an improvement to the digital circuit topology shown in Figure 1. The improved topology includes a buffer having low Vp-p output voltage characteristics like the ECL-type of logic gate (as shown in Figure 3) and having the static power characteristic of the CMOS-type logic gate technology (as shown in Figure 2). The low peak-to-peak voltage swing results in reduced power dissipation when charging and discharging loads. While, reduced static power consumption results in power savings during periods when logic states are not switched. In addition, the present invention provides other improvements to the digital topology shown in Figure 1 so that overall power dissipation for this topology is reduced.

SUMMARY OF THE INVENTION

A digital circuit topology having improved power characteristics is described. The present invention relates to digital circuit topologies that include a logical core portion and a bus driver/buffer portion. The improvement of the present invention is a unique output buffer that generates a relatively small output swing and does not dissipate quiescent power. Another aspect of the present invention reduces quiescent power consumption by pulsing the core logic portion.

The core logic portion in the topology of the present invention may be implemented in any type of logic gate. Accordingly, in one embodiment of the present invention the core logic portion substantially comprises logic gate types that characteristically dissipate quiescent power and have small Vp-p swings. In another embodiment of the present invention the core logic portion substantially comprises complementary-type logic gates. The core logic portion outputs an intermediate signal. This intermediate signal and its inverse are coupled to the buffer of the present invention.

In response to the intermediate signal and its inverse, the output buffer of the present invention generates an output digital signal. The buffer generates the output digital signal by multiplexing first and second reference voltages onto the output of the buffer. The first and second reference voltages are very close in magnitude so that the output of the buffer is driven by a digital signal having a very small Vp-p swing. In one embodiment, the output buffer is implemented with first and second transmission gates comprising p-type field effect transistors (PFETs). In another embodiment the transmission gates comprise n-type FETs (NFETs). Since the buffer of the present invention does not utilize constant current sources, no quiescent power is dissipated.

In another embodiment of the improved topology of the present invention, the buffer is designed to output a differential signal. In this embodiment two sets of transmission gates are coupled to the output of the core logic; each set of transmission gates providing an output signal that is inversely related to the other output signal.

In a further embodiment of the present invention, a gain stage is coupled between the core logic portion and the buffer of the present invention. The gain stage converts small Vp-p intermediate signals into signals having large voltage swings. This is done so that the on- resistance of the transmission gates is minimized when PFETs or NFETs are utilized in the buffer. Still another embodiment of the present invention relates to digital circuit topologies having core logic comprising logic gates that dissipate quiescent power. In this embodiment, the current sources within the core logic portion are pulsed at a predetermined rate. Pulsing the current sources enables the core logic for short intervals. These intervals are long enough to pass the data from the logic portion to a latched sense amplifier. Once the sense amplifier has sensed the data from the core logic, the pulse is removed from the current sources. The frequency of the core logic pulse and sense amplifier clock are selected so that the overall power characteristic of this topology is optimized. A variation of this embodiment involves setting the amount of drive supplied by the current sources in the core logic portion with respect to the clock frequency of the sense amplifier/latch.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a block diagram of a digital circuit topology including a logic block and a buffer.

Figure 2A is a block diagram of a complementary-type logic gate.

Figure 2B is a complementary-type logic gate comprising CMOS devices.

Figure 2C are the input and output timing diagrams for the logic gates shown in Figure 2A and 2B.

Figure 3A is a block diagram of a type of logic gate that dissipates quiescent power.

Figure 3B is an emitter-coupled logic (ECL) gate.

Figure 3C is the timing diagram of the output voltage for the logic gate shown in Figure 3B.

Figure 4 is a block diagram of an embodiment of the improved digital circuit topology of the present invention including the improved buffer of the present invention.

Figure 5 illustrates the embodiment of the present invention shown in Figure 4 with the buffer of the present invention implemented in p-type field effect transistors. Figure 6 shows an embodiment of the improved digital circuit topology of the present invention having the logic block portion being implemented in ECL-type devices.

Figure 7 illustrates an embodiment of the improved digital circuit topology of the present invention having the logic block portion being implemented in CMOS-type devices.

Figure 8 is a differential version of the improved circuit topology of the present invention in which the logic block portion is implemented in ECL-type devices.

Figure 9 illustrates a differential version of the improved circuit topology of the present invention in which the logic block portion is implemented in CMOS-type devices.

Figure 10 is an embodiment of the circuit topology of the present invention in which the core logic portion is pulsed to reduce the quiescent power consumption of the logic block.

Figure 11 illustrates the timing diagrams for the logic block strobe signal and the sense amplifier clock signal.

Figure 12 illustrates a variation of the embodiment shown in Figure 10, including two alternately enabled sense amplifiers and buffers.

Figure 13 is the timing diagram for Figure 12.

Figure 14 is the topology illustrated in Figure 12, showing the sense amplifier portion in schematic form. Figure 15 is the timing diagram for Figure 14.

Figure 16 is another alternative embodiment of the present invention which includes a frequency-to-voltage converter that adjusts current drive within the logic block to optimize the power consumption of the logic block with respect to the sense amplifier clock frequency.

DETAILED DESCRIPTION

In the following description, an improved digital circuit topology is described in which numerous specific details are set forth, such as specific logic gate types, device conductivity types etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known structures and circuits have not been shown in detail in order to avoid unnecessarily obscuring the present invention. The present invention improves the power efficiency of the topology shown in Figure 1 by 1) providing a buffer design that has no quiescent power dissipation and that generates an output signal having a relatively small voltage swing, and 2) providing an improved topology design that reduces the quiescent power dissipation of logic block 50 when it is designed with ECL-type logic.

Elimination of Quiescent Power Consumption in Buffer 53

Figure 4 illustrates a block diagram of a core logic/buffer digital topology including the improved buffer of the present invention. The topology comprises logic block 50 and output buffer 53. In response to input signals 49, logic block 50 provides either a digital high or low output voltage (corresponding to either a high or low logic state) onto interconnect line 51. In one embodiment of the present invention, logic block 50 is implemented in complementary-type logic gates such as that illustrated in Figure 2A. In this case, the output signal on interconnect line 51 has a relatively large peak-to-peak voltage swing (equal to the difference between the positive and negative supply voltages). In another embodiment, the core logic portion comprises ECL-type logic gates. In this case, the output signal on interconnect line 51 has a small Vp-p swing.

Capacitor 52 (Figure 4) represents the capacitive loading contributed by interconnect line 51 and the input of buffer 53. Since the length of interconnect line 51 is usually designed to be relatively short, and since the input capacitance of buffer 53 tends to be small, capacitor 52 represents a relatively small capacitive load (approximately 10 - 100 fF). Buffer 53 of the digital circuit topology of the present invention comprises multiplexer 54. Multiplexer 54 functions as a basic multiplexer. As is well known in the art, multiplexers basically have a set of n input data signals that are applied to the multiplexers input data inputs. A set of control signals are applied to the multiplexers control inputs. The control signals indicate which one of the n input data signals is to appear at the output of the multiplexer.

Multiplexer 54 of the present invention has voltage V1 applied to a first information input and V2 coupled to a second information input. The digital signal on line 51 is applied to a first control input and the inverse of the signal on line 51 is applied to a second control input. In response to the digital signal on line 51 and its inverse, multiplexer 54 couples either V1 or V2 to its output (interconnect line 55) causing line 55 to transition between V1 and V2. As a result, a digital signal (corresponding to the digital signal on interconnect line 51) is coupled onto interconnect line 55. The peak-to-peak voltage swing of the signal on line 55 is equal to the difference between V1 and V2 (i.e. Vp-p = V1 - V2). Voltages V1 and V2 are selected to have magnitudes that are relatively close in value so that the Vp-p swing on line 55 is relatively small. Voltage swings in the range of 200 mV are possible. Multiplexer 54 is designed so that it only dissipates power when charging and discharging capacitive load 56. Load capacitance 56 represents a relatively large capacitive load, such as a long interconnect line or an internal input/output (I/O) pad, typically greater than 300 fF.

In one embodiment of the present invention, reference voltages V1 and V2 may both be independently generated. There are many well known prior art power efficient techniques to generate a reference voltage. Some techniques include charge pump voltage converters and switching converters utilizing inductive elements. In the preferred embodiment, V1 is equal to the supply voltage, VDD, coupled from another portion of the circuit and V2 is generated independently; V2 having a magnitude close in value to VDD.

Thus, the buffer of the present invention generates a digital signal having a small Vp-p like an ECL-type of logic gate and like the complementary-type logic gate it dissipates no quiescent power. As a result, it is extremely power efficient whether it is changing states frequently or infrequently.

Figure 5 shows the core logic/buffer topology of the present invention with buffer 53 implemented utilizing two p-type field effect transistors (FETs), coupled as parallel transmission gates.

A transmission gate is defined as a device having an input terminal, and output terminal and a control terminal. A transmission gate functions such that it couples the voltage on its input terminal through a low resistive path to its output terminal in response to a given voltage applied to its control terminal.

The control terminal of device 57 is coupled to interconnect 51. The input terminal of device 57 is coupled to VDD and its output terminal is coupled to interconnect line 55. Interconnect line 51 is also coupled to to the control terminal of device 58 through inverter 59. The input terminal of device 58 is coupled to V2 and its output terminal is coupled to interconnect line 55. The PFET devices function such that when the digital signal on line 51 is high, device 57 is off and device 58 is on. When this occurs, device 58 passes V2 to interconnect line 55. When the digital signal on line 51 is low, device 58 is off and device 57 is on. As a result, VDD is coupled to interconnect line 55. Thus, interconnect line 55 transitions between VDD and V2. The transmission gates may also be implemented in n-type FETs. In this case, the node shown as VDD becomes the most negative supply voltage (commonly referred to as VSS) and V2 becomes a voltage slightly more positive than VSS.

In the embodiments of the circuit topology of the present invention shown in Figures 4 and 5, logic block 50 may be implemented utilizing many types of logic gate designs. If logic block 50 is implemented with logic gates that generate a digital signal having a small Vp-p swing, it is desirable to convert the small Vp-p signal to a large Vp-p signal. Increasing the Vp-p swing of the signal ensures that the PFETs operate with low on-resistance (for moderately sized devices). By ensuring that the PFETs are operated in their low on-resistance region, the frequency response of the buffer of the present invention is increased. For example, if a minimum geometry device is driven with a 3 volts Vp-p swing signal, its on-resistance would be in the range of 1000 ohms. Further, if this device drives a 1pF capacitive load, the RC time constant for the output of the device is I nanosec, i.e. RC = (1 x 10^'12 F) x (1 x 10³ ohms) = 1 x 10^"9sec = 1 nanosec. Hence, frequencies in the hundreds of Megahertz are achievable with this invention.

In the implementation of the topology of the present invention shown in Figure 6, logic block 50 is implemented with logic gates that produce a digital signal having a small Vp-p swing. As a result, line 51 is driven with a small Vp-p signal. This embodiment of the present invention also includes gain stage 60 coupled between core logic portion 50 and buffer 53. Gain stage 60 functions to convert the small swing digital signal on line 51 to a large swing signal and couple it to the control gates of PFET devices 57 and 58. Gain stage 60 provides a large Vp-p swing output signal (on line 61) and an inverse output signal (on line 62). The logical state of the signal on interconnect line 61 corresponds to the logical state of the digital signal on line 51. PFETs 57 and 58 function in the same manner as described in the embodiment shown in Figure 5, i.e. coupling either VDD or V2 onto line 55.

It should be noted that if interconnect line 55 is coupled to another ECL-type logic block located elsewhere within the digital circuit, the small Vp-p digital signal on interconnect 55 is compatible with the input of that ECL-type logic block. However, some level shifting of the signal on line 55 may be necessary. It should further be noted that gain stage 60 may be implemented as a sense amplifier that compares the input signal on line 51 to a given reference voltage. If the input signal on line 51 is higher than the reference voltage, gain stage 60 outputs a voltage corresponding to a high logic state onto line 61. If signal 51 is lower than the reference voltage, then stage 60 outputs a voltage corresponding to a low logic state onto line 61. Figure 7 illustrates still another embodiment of the present invention in which logic block 50 is implemented in complementary-type logic and buffer 53 interfaces with a complementary-type logic block (logic block 64). Complementary-type logic blocks 50 and 64 are only compatible with digital signals having large Vp-p swings. In addition, logic blocks 50 and 64 generate digital signals having large Vp-p swings. Consequently, unlike the ECL-type logic implementation shown in Figure 6, the signal from logic block 50 is directly coupled to buffer 53. In other words, the implementation shown in Figure 7 does not require gain stage 60 (Figure 6) to boost the voltage levels of the digital signals on line 51. As described in the previous embodiments, buffer 53 generates a digital signal on interconnect line 55 having Vp-p swing equal to VDD - V2. Interconnect 55 transmits this small Vp-p swing signal to logic block 64 (located remotely from 53) through gain stage 63. Gain stage 63 converts the small Vp-p swing signal on line 55 to a large Vp-p swing signal compatible with complementary-type logic block 64. It should be noted that the input capacitance of logic block 64 is relatively small. Consequently, little power is dissipated by gain stage 63.

The embodiments shown in Figures 4, 5, 6, and 7 are single- ended versions of the topology of the present invention. In other words, buffer 53 provides only one digital output signal. Figure 8 illustrates a differential embodiment of the present invention in which buffer 53 outputs a digital signal (OUT) and the inverse of that digital signal (OUT ). In this embodiment logic block 50 is designed utilizing ECL-type logic gates. Consequently, the signal on line 51 is converted to a large swing signal by gain stage 60 to ensure that the PFET devices are driven by a large Vp-p signal. The differential output of gain stage 60 is coupled to two pairs of PFETs. PFETs 57 and 58 have their control inputs coupled to interconnect lines 61 and 62 respectively. Interconnect lines 61 and 62 are also coupled to the control inputs of PFETs 64 and 65. The signal on interconnect line 61 is the inverse of the signal on line 62. As a result, when the signal on line 61 is high, the signal on line 62 is low and devices 57 and 65 are off and devices 58 and 64 are on. In this state, V2 is coupled to OUT and VDD is coupled to OUT/. Similarly, if interconnect line 61 is low and line 62 is high, devices 57 and 65 are on and devices 58 and 64 are off. In this state, VDD is coupled to OUT and V2 is coupled to OUT/. Thus, buffer 53 generates two signals that transition between VDD and V2 - each being the inverse of the other.

Figure 9 illustrates another differential embodiment of the present invention. In this embodiment, logic block 50 is implemented in complementary-type logic gates. As can be seen, block 50 generates a differential signal onto lines 51 and 51'. This differential signal is coupled directly into buffer 53. Buffer 53 comprises PFETs 57, 58 and 64 and 65. Buffer 53 (Figure 9) generates a differential signal on lines OUT and OUT/ in response to the differential signal on lines 51 and 51' in the same manner as described in Figure 8. The differential signal on OUT and OUT/ is transmitted to another logic block 64 within the digital circuit. Gain stage 63 converts the small Vp-p swing signal on lines OUT and OUT/ to a large Vp-p swing signal compatible with complementary-type logic block 64. It should be noted that the input capacitance of logic block 64 is relatively small. Consequently, little power is dissipated by gain stage 63.

In the single-ended version of the present invention, gain stage 63 (Figure 7) is typically a comparison stage - such as a sense amplifier - that compares the signal on line 55 to a reference voltage. However due to noise, this reference voltage may fluctuate and cause gain stage 63 to output the wrong logic level. In contrast, the differential implementations of the present invention (shown in Figure 9) compares the signal on line 55 (OUT) to its inverse (OUT/). As a result, if power supply noise occurs, OUT and OUT/ fluctuate concurrently so that the noise cancels itself out. Consequently, the differential implementation shown in Figures 8 and 9 are less susceptible to noise related errors and are typically more robust.

Elimination of Quiescent Power in Logic block 50 and

Gain stage 60 Another aspect of the present invention relates to the circuit topology shown in Figure 6, specifically, to a circuit topology in which logic block 50 is implemented in a type of logic gate that dissipates quiescent power due to logic gates utilizing constant current sources. As noted above, an example of this type of logic gate is shown in Figure 3A. In Figure 3A, current source 22 is biased by reference voltage (VI) such that it provides a constant current. As a result, a logic block implemented utilizing this type of logic gate is constantly dissipating power. Additionally, gain stage 60 as described in the embodiment shown in Figure 6, typically is implemented as a sense amplifier. Sense amplifiers also comprise constant current sources. As a result, gain stage 60 further adds to the quiescent power dissipation of the topology shown in Figure 6.

The embodiment of the present invention shown in Figure 10 eliminates the quiescent power dissipation of logic block 50 (when it is implemented with the logic gate type shown in Figure 3A) and eliminates the quiescent power dissipation of its associated gain stage.

Figure 10 includes strobed logic block 50, latched sense amplifier 68, and the buffer of the present invention implemented with two PFETs (as described above). Strobe signal 69 is coupled to all of the logic gates' current sources within logic block 50. Referring to the timing diagram shown in Figure 11 , when strobe signal 69 is at some voltage, V(on), the logic gates' current sources are on. In this case, the logic gates are activated and dissipating power. When signal 69 is at a voltage equal to V(off), the current sources are off and the logic gates are not dissipating power.

Clock 70 is the enable signal for sense amplifier 68. Referring to Figure 11 when clock signal 70 is high, sense amplifier 68 (SA68) is enabled and captures the logic state present on line 51. During this time, SA68 is dissipating power. When signal 70 is low, SA68 is no longer dissipating power.

Logic block 50 is strobed by signal 69 when the input conditions on lines 49 are expected to change. Strobing in this manner ensures that logic block 50 is activated such that all input condition changes are detected. For example, if logic block 50 is designed as a synchronous system and state changes occur on clock transitions, then strobing would occur for a short period on every clock edge. When strobe 69 is at V(on), input signals 49 (Figure 10) cause the logic block 50 to output a logic signal onto line 51. Strobe 69 is applied long enough to ensure that line 51 reaches the new logic state. The required pulse duration of strobe 69 is dependent on the RC constant of line 51 and the amount of current drive supplied by the logic gates' current sources. Sense amplifier 68 is not clocked until line 51 is fully charged. Thus, it is not dissipating quiescent power until it is enabled by signal 70.

When line 51 is fully charged to a voltage potential equal to either a high or low logic level, sense amplifier 68 is clocked by signal 70. The latched sense amplifier is responsive to the positive edge transition (indicated by 200 in Figure 11) of clock signal 70. At this time, the logic state on line 51 is latched into sense amplifier 68 and lines 61 and 62. Once the state of the sense amplifier is stable, the strobe 69 transitions to V(off). With strobe 69 at V(off), the current sources in logic block 50 are turned off. The latched logic state on lines 61 and 62 drive transmission gates 57 and 58 in the same manner as described with previous embodiments. Once the logic state is latched onto lines 61 and 62, clock 70 is removed so that the sense amplifier is no longer dissipating power. The logic states on lines 61 and 62 do not change after clock 70 is removed. Note that none of the elements in Figure 10 consume power continuously.

Figure 12 illustrates a variation of the embodiment shown in Figure 10. In this embodiment, two sense amplifiers are utilized to store the state changes from logic block 50. This allows logic block 50 to transfer data twice every sense amplifier clock cycle, (i.e. once on the rising edge of the clock cycle and once on the falling edge of the clock cycle), instead of being sensed once every clock cycle as in the previous embodiment shown in Figure 10. Referring to Figure 12, multiplexer 200 is coupled to the output of logic block 50. It functions to direct the data on line 51 to either sense amplifier 201 or 202. Multiplexer 200 is responsive to the rising and falling edges of system clock signal PHI, so that data is passed to either sense amplifier 201 or 202 every half clock cycle. For instance, on the rising edge of PHI, multiplexer 200 couples the logic state on line 51 to the input of sense amplifier 201 , node 1. On the falling edge of PHI, multiplexer 200 couples the logic state of line 51 to the input of sense amplifier 202, node 2.

Sense amplifier 201 is enabled by clock signal PHIA when the data on line 51 is directed to node 1. Sense amplifier 202 is enabled by clock signal PHIB when the data on line 51 is directed to data path 2. The output of each of the sense amplifiers controls each of the multiplexer buffers 203 and 204. Specifically, sense amplifier 201 controls MUX 203 in one half cycle. Alternately, sense amplifier 202 controls MUX 204 in the the other half cycle. Figure 13 is the timing diagram for the topology shown in Figure

12. When strobe signal 69 transitions low to high (indicated by 205, Figure 13), logic block 50 is enabled and begins to charge capacitor 52 with a voltage corresponding to either a high or. low logic state. Once line 51 reaches a stable state at time T1 , PHI transitions high (indicated by 206, Figure 13), and couples the data on line 51 to node 1. Once this occurs (and the data is stable on node 1), strobe signal 69 transitions low so that logic block 50 no longer consumes any power. Also at this time, PHIA transitions high (indicated by 207, Figure 13) and enables sense amplifier 201 and MUX 203. Sense amp 201 latches the logic state sensed on node 1 to OUTA. The signal on OUTA controls MUX 203 so that it drives output line 55 with either V1 or V2 (depending on the data sensed during the first pulse of strobe signal 69).

When the second pulse of strobe signal 69 occurs, logic block 50 charges capacitor 52 with a voltage level corresponding to a new logic state. Once line 51 is stable at T2, PHI transitions high-to-low (indicated by 208, Figure 13). When this occurs, the data on line 51 is coupled to node 2. Also at this time, sense amp 202 and MUX 204 are enabled when signal PHIB transitions low-to-high (indicated by 209, Figure 13). After which, MUX 204 couples either V1 or V2 to line 55 (depending on the data sensed during pulse 2). Referring to Figure 13, it should be noted that strobe signal 69 provides a pulse twice per clock cycle T, resulting in data transfer twice per clock period.

Figure 14 illustrates one schematic implementation of the sense amplifier/latches shown in Figure 12. Referring to Figure 14, sense amplifier/latch 201 comprises devices 207 - 211 and sense amplifier/latch 202 comprises devices 212 - 216. NMOS Devices 211 and 216 function as current sources for sense amplifier/latches 201 and 202, respectively.

Each sense amplifier/latch functions to compare its input node (line 51) to VREF when its corresponding current source is enabled. If the voltage on its input node is higher than VREF, then the sense amplifier latches a voltage level corresponding to a high logic level (VDD) on its non-inverted output (node 1 for SA201 and node 2 for SA202) and a low logic level (VSS) on its inverted output (node 3 for SA201 and node 4 for SA202). When the voltage on its input node is lower than VREF, then the sense amplifier latches a voltage level corresponding to a low logic level on its non-inverted output and a high on its inverted output. Clock signals PHI2 and PHI4 are the enable signals for each of NMOS current source devices 211 and 216. When PHI2 is high, device 211 is on. In this state, SA201 is sensing the data on line 51 and driving PFETs 57 and 58. When PHI4 is high, device 216 is on and SA202 is sensing data on line 51 and driving PFETs 64 and 65.

PMOS devices 205 and 217 function as SA201's pass gates. PMOS devices 206 and 218 function as SA202's pass gates. Clock signal PHI1 controls devices 205 and 217 and clock signal PHI3 controls devices 206 and 218. Clock signals PHI1 and PHI3 are inversely related. As a result, when devices 205 and 217 are on, 206 and 218 are off. Conversely, when devices 205 and 217 are off, devices 206 and 218 are on. In this way, data on line 51 is passed to only one sense amplifier/latch at a time.

PFETs 57, 58, 64, and 65 function in the same manner as described in the embodiments shown in Figures 8 and 9.

Referring to Figure 15, at TO, PHI1 and PHI2 are high so that pass gate devices 205 and 217 are off and SA201's current source device 211 is on. In this state, SA201 is providing a previously latched logic level to PFETs 57 and 58. In addition, since SA201's pass gates are off, any change on line 51 does not affect the voltage levels on nodes 1 and 3. Further, at TO, PHI4 is low such that SA202's current source is off. Thus, at time TO, SA201 is driving line 55 with a previously latched data and SA202 is disabled.

It should be noted that at TO, logic block 50 is disabled (PHI5 is low) and PHI3 is low such that SA202's pass gates (206 and 218) are on. In this state, since SA202's current source is off, it is not sensing a differential voltage between nodes 2 and 4. However, since the SA202's pass gates are on, the voltage on node 51 is applied to the gate of device 64 and VREF is applied to the gate of device 65. To ensure that devices 64 and 65 are off while devices 57 and 58 are driving output line 55 at TO, VREF is set to a voltage more positive than the threshold voltage of devices 65. Additionally, it is necessary to ensure that the voltage on line 51 is higher than the threshold voltage on device 64. The voltage on line 51 (at TO) is dependent on the disabled output voltage of logic block 50 which, in turn, is dependent on the internal logic of logic block 50. In the embodiment shown in Figure 14, it is assumed that logic block 50 is implemented such that when it is disabled, its output (line 51) rises to a voltage close to the most positive power supply voltage (VDD). This ensures that the voltage on line 51 is high enough to keep device 64 off. However, in the case in which logic block 50's disabled output voltage does not rise high enough to keep device 64 off, additional circuitry is required to pull line 51 to a higher voltage.

At time T1 , PHI5 transitions from low-to-high and logic block 50 is enabled. When this occurs, logic block 50 begins to charge capacitor 52 to a voltage corresponding to either a high or low voltage level

(depending on input signals 49). Since SA202's pass gate 206 is on, node 2 is also being charged to the same logic level as line 51. SA201's pass gate is off, so the data on line 51 is not seen by this sense amplifier. At time T2, PHI2 goes low and PHI4 goes high. This turns

SA201's current source device 211 off and SA202's current source 216 on. As a result, a differential voltage is latched across nodes 2 and 4 that corresponds to the logic level sensed on line 51. The voltage on nodes 2 and 4 drive PFET devices 64 and 65 which, in turn, drive output line 55 to a voltage corresponding to the logic level sensed on line 51. At time T3, PHI1 transitions high-to-low and PHI3 transitions low- to-high. As a result, the pass gates for SA201, devices 205 and 217, turn on and the pass gates for SA202, 206 and 218, turn off. SA201's current source is still off and SA202's current source is still on at time T3. Consequently, output line 55 is driven by SA202. It should be noted that although SA201's pass gates 205 and 217 are on, PFETs 57 and 58 are held off and have no affect on output line 55 since VREF and the voltage on line 51 are at levels close to VDD. At time T4, PHI5 transitions low, turning off all of the current sources in logic block 50 such that it no longer consumes power. It should be noted that after PHI5 transitions low, the data stored in SA202 still provides the differential voltage on nodes 2 and 4 to drive devices 64 and 65.

At T5 the same sequence of events as described for times TO - T4 are repeated with alternate sense amplifiers driving the output. Specifically, the following sequence occurs: 1) before logic block 50 is enabled at time T5, SA201's pass gates are on but line 51 has no effect on the output, (during this time SA202 is enabled and is driving output line 55 and SA201 is disabled); 2) at T5, logic block 50 is enabled and charges line 51 and the input of SA201 ; 3) at T6, SA201 is enabled and drives output line 55 (with logic level sensed at T5); also at time T6, SA202 is disabled; 4) at T7, the pass gates are set so that line 51 is coupled to input of SA202; 5) at T8, logic block 50 is disabled.

It should be noted that none of the elements in Figure 14 dissipate quiescent power.

PHI5 provides bias voltage VI (refer to Figure 3A and 3B) to logic gate current sources when logic block 50 is enabled. In this case, the amount of current generated by each current source, and consequently the time averaged power dissipated by logic block 50, is directly proportional to the magnitude (V_PH|5) and pulse width (t_PH|5) of signal PHI5, (Figure 15). For example, a pulse having a large V_PHI5 and a long t_PHI5 causes logic block 50 to dissipate more time averaged power than a pulse having a small V_PHI5 and a relatively short t_PH|5. Time averaged power dissipation in the embodiment shown in Figure 14 is optimized by selecting pulse magnitude (V_PHI5) and pulse width (t_PHI5) such that it causes logic block 50 to dissipate the least amount of time-averaged power for a given PHI1 - PHI4 clock frequency. This is achieved by selecting minimum values for V_PHI5 and t_PHI5 to ensure that 1) PHI5 is at a high voltage level long enough for the state change on line 51 to be captured by either of the sense amplifiers in a specific time interval (set by tp_His). ^{and 2}) enough current drive is supplied by logic block 50 so that the logic state on line 51 is stable in that time interval (set by V_PHI5).

PHI5 may also be a digital signal that controls the magnitude and duration of a signal supplied by a variable current bias source. In this case, instead of adjusting the pulse width and magnitude of PHI5 for optimization, PHI5 is set so that it controls the variable current bias source to provide a signal that ensures power optimization. As an example, in the timing diagram shown in Figure 15, V_PHI5 and t_PHI5 are set so that the state of line 51 is charged to its appropriate logic level within interval 221 , i.e. when SA202's pass gate and current source are on. In this way, the logic state on line 51 is reliably captured by SA202. Any values for V_PHI5 and t_PHI5 over the optimized value translates into unnecessary power consumption.

In the embodiment of the present invention shown in Figure 14, the magnitude and pulse width of signal PHI5 are tailored with respect to the sense amplifiers' clock signal to eliminate the quiescent power dissipation of logic block 50. An alternative to the embodiment shown in Figure 14 is shown in Figure 16. In this embodiment, logic block 50 comprises logic gates that are designed such that VI is a constant voltage and current source 22 is always on (refer to Figure 3A). As a result, logic block 50 dissipates quiescent power. However, the quiescent power dissipation of logic block 50 is optimized by adjusting VI with respect to the frequency of the sense amplifier clock signal.

Referring to Figure 16 the output of logic block 50 (line 51) is coupled to sense amplifier 68 through pass gate 221. When pass gates 221 and 222 and sense amplifier 68 are enabled by clock PHI1 , the sense amplifier compares the voltage on line 51 to VREF and outputs a differential signal, OUT and OUT/, corresponding to the logic signal sensed on line 51. This differential signal drives buffer 53 such that it couples either VDD or V2 to output line 55. Optimization of power consumption is achieved by coupling clock signal PHI1 to a frequency-to- voltage converter (shown in Figure 16).

The frequency-to-voltage converter generates two voltages scaled to the frequency of clock signal PHH . The first voltage on line 219, V₂₁₉, is coupled to each of the current source devices within logic block 50. In other words, V₂₁₉ functions as the VI (see Figure 3A) for all logic gate current sources. The voltage on line 219 determines the amount of current generated by each of the logic gates and consequently the amount of power consumed by logic block 50

The second voltage V₂₂₀ is coupled to variable load devices within logic block 50. These variable load devices correspond to resistive loads 26 and 27 in Figure 3A. The variable load devices along with the current supplied by current source 22, determine the output swing of the logic gate and consequently, logic block 50. In most logic circuits, a constant output logic swing is required as the power is varied. Thus, to ensure that the output logic swing remains constant, it is necessary to adjust the resistance of the variable load at the same time that the current drive for each logic gate is adjusted. This is accomplished by scaling V₂₁₉ and V₂₂₀ simultaneously.

Optimum power dissipation for the topology shown in Figure 16 is achieved by adjusting the current drive of a logic block 50 to a minimum value such that logic block 50 drives line 51 with a signal that reaches a stable state in the desired PHI1 time interval. It should be obvious that as the frequency of clock signal PHI1 increases, the output of logic block 50 needs to transition faster to get to the desired logic state within the established time interval. Increasing the current drive of current sources 22 causes the output of logic block 50 to transition faster. Conversely, decreasing the current drive of current sources 22, causes the output of logic block 50 to transition slower. If PHI1 is a high signal frequency, the output of logic block 50 needs to transition relatively fast. In this case, V219 needs to be a relatively large voltage potential such that the logic blocks' current sources provide a large current drive. On the other hand, a low frequency PHI1 allows logic block 50 a long time to establish a valid voltage level on line 51. In this case, less current drive is required and thus a smaller voltage potential is generated by V219.

Although the present invention has been described in conjunction with certain embodiments, it is appreciated that the invention may be implemented in a variety of other ways. By way of example, many types of logic gate types and device technologies may be utilized to implement the logic block portion. Consequently, it is to be understood that the particular embodiments shown and described by way of illustration are in no way intended to be considered limiting. Reference to the details of these embodiments is not intended to limit the scope of the claims which themselves recite only those features regarded as essential to the invention.

Claims

CLAIMSWe Claim:

1. A digital circuit buffer for driving an interconnect bus with a first digital signal, said first digital signal fluctuating between a first and a second voltage in response to an input digital signal, said buffer comprising: a first transmission gate having a control terminal, an input terminal and an output terminal, said first transmission gate's control terminal being coupled to said input digital signal, said first transmission gate's input terminal being coupled to said first voltage and said first transmission gate's output terminal being coupled to said interconnect bus; a second transmission gate having a control terminal, an input terminal and an output terminal, said second transmission gate's control terminal being coupled to the inverse of said input digital signal, said second transmission gate's input terminal being coupled to said second voltage and said second transmission gate's output terminal being coupled to said interconnect bus; said first and said second transmission gates functioning to multiplex said first and said second voltages to said interconnect bus so as to generate said first digital signal having a peak-to-peak voltage equal to the difference between said first and said second voltages, said first and second transmission gates generating said first digital signal without dissipating quiescent power.

2. The digital circuit buffer as described in claim 1 wherein said first and second transmission gates comprise p-type field effect transistors.

3. The digital circuit buffer as described in claim 1 wherein said first and second transmission gates comprise n-type field effect transistors.

4. The digital circuit buffer as described in claim 2 and 3 wherein said digital circuit buffer further includes a means for amplifying said input digital signal so that said first and second transmission gates are operated in a low on-resistance state, said amplifying means being coupled to said control terminal of said first transmission gate and said control terminal of said second transmission gate.

5. The digital circuit buffer as described in claim 4 wherein said amplifying means is a sense amplifier.

6. The digital circuit buffer as described in claim 5 wherein said absolute value of said difference between said first and said second voltages is less than 600mV.

7. A digital circuit buffer for driving a first interconnect bus with a first digital signal and for driving a second interconnect bus with the inverse of said first digital signal, each of said first digital signal and said inverse of said first digital signal fluctuating between a first and a second voltage in response to an input digital signal, said buffer comprising: a first transmission gate having a control terminal, an input terminal and an output terminal, said first transmission gate's control terminal being coupled to said input digital signal, said first transmission gate's input terminal being coupled to said first voltage and said first transmission gate's output terminal being coupled to said first interconnect bus; a second transmission gate having a control terminal, an input terminal and an output terminal, said second transmission gate's control terminal being coupled to said inverse of said input digital signal, said second transmission gate's input terminal being coupled to said second voltage and said second transmission gate's output terminal being coupled to said first interconnect bus; said first and said second transmission gates functioning to multiplex said first and said second voltages to said first interconnect bus so as to generate said first digital signal having a peak-to-peak voltage equal to the absolute value of the difference between said first and said second voltages, said first and second transmission gates generating said first digital signal without dissipating quiescent power. a third transmission gate having a control terminal, an input terminal and an output terminal, said third transmission gate's control terminal being coupled to said input digital signal, said third transmission gate's input terminal being coupled to said first voltage and said third transmission gate's output terminal being coupled to said second interconnect bus; a fourth transmission gate having a control terminal, an input terminal and an output terminal, said fourth transmission gate's control terminal being coupled to said inverse of said input digital signal, said fourth transmission gate's input terminal being coupled to said second voltage and said fourth transmission gate's output terminal being coupled to said second interconnect bus; said third and said fourth transmission gates functioning to multiplex said first and said second voltages to said second interconnect bus so as to generate said inverse of said first digital signal having a peak-to-peak voltage equal to the absolute value of the difference between said first and said second voltages, said third and fourth transmission gates generating said inverse of said first digital signal without dissipating quiescent power.

8. The digital circuit buffer as described in claim 7 wherein said first, second, third, and fourth transmission gates comprise p-type field effect transistors.

9. The digital circuit buffer as described in claim 7 wherein said first, second, third, and fourth transmission gates comprise n-type field effect transistors.

10. The digital circuit buffer as described in claim 8 and 9 wherein said digital circuit buffer further includes means for amplifying said input digital signal so that said first, said second, said third and said fourth transmission gates are operated in a low on-resistance state, said amplifying means being coupled to said control terminal of each of said first, said second, said third and said fourth transmission gates.

11. The digital circuit buffer as described in claim 10 wherein said absolute value of said difference between said first and said second voltages is less than 600mV.

12. In a digital circuit topology including a logic circuit portion for generating a first digital signal, said logic circuit portion implemented with logic gates including current sources that are constantly enabled such that said logic circuit portion dissipates quiescent power, said digital circuit topology also including a buffer portion responsive to said first digital signal, said buffer portion for driving a bus with a second digital signal corresponding to said first digital signal, an improved topology comprising: a pulse signal, said pulse signal transitioning between a first logic state and a second logic state; a logic circuit portion having said current sources controlled by said pulse signal, said pulse signal functioning to enable and disable said current sources, wherein when said current sources are enabled, said logic circuit portion outputs a valid data signal and when said current sources are disabled, said logic circuit portion is disabled; a control signal, said control signal fluctuating between a voltage corresponding to a first logic state and a voltage corresponding to a second logic state; a means for sensing and storing said valid data signal, said means being responsive to said control signal, wherein when said control signal is in said first logic state said means is sensing and storing said valid data signal and when said control signal is in said second logic state said sensing and storing means is disabled; a multiplexer means for generating said second digital signal, said multiplexer means having first and second control terminals, first and second input terminals and an output terminal, said first control terminal being coupled to said valid data signal stored in said sensing and storing means, said second control terminal being coupled to the inverse of said valid data signal stored in said sensing and storing means, said first input terminal being coupled to a first voltage, said second input terminal being coupled to a second voltage, and said output terminal coupled to said bus, said multiplexer means coupling said first voltage to said bus when said valid data signal is at a voltage corresponding to said first logic state and coupling said second voltage to said bus when said valid data signal is at a voltage corresponding to said second logic state.

13. The improved topology described in claim 12 wherein said pulse signal and said control signal are synchronized with respect to one another such that said logic circuit portion is enabled no longer than the amount of time necessary to charge the input capacitance of said sensing and storing means with said valid data signal and wherein said sensing and storing means is not enabled until said input capacitance of said sensing and storing means is charged with said valid data signal.

14. The improved topology described in claim 13 wherein said multiplexer means comprises a first and second transmission gates each having input terminal, control terminal, and output terminal, said first transmission gate's control terminal being coupled to said valid data signal, said first transmission gate's input terminal being coupled to said first voltage and said first transmission gate's output terminal being coupled to said bus, said second transmission gate's control terminal coupled to said inverse of said valid data signal, said second transmission gate's input terminal coupled to said second voltage and said second transmission gate's output terminal coupled to said bus.

15. The improved topology as described in claim 14 wherein said first and second transmission gates comprise p-type field effect transistors.

16. The improved topology as described in claim 14 wherein said first and second transmission gates comprise n-type field effect transistors.

17. The improved topology as described in claim 15 and 16 wherein said means for storing and sensing said valid data signal comprises a latched sense amplifier.

18. A digital circuit topology comprising: a pulse signal, said pulse signal transitioning between a first logic state and a second logic state; a logic circuit portion for generating a valid data signal, said logic circuit portion being controlled by said pulse signal such that when said pulse signal is in said first logic state, said logic circuit portion outputs said valid data signal and when said pulse signal is in said second logic state, said logic circuit portion is disabled; a clock signal, wherein a cycle of said clock signal includes a first and a second half cycle, said clock signal being at a voltage corresponding to said first logic state during said first half cycle and said clock signal being at a voltage corresponding to said second logic state during said second half cycle; first and second means for sensing and storing said valid data signal, said first sensing and storing means being enabled by said clock signal such that it is sensing and storing said valid data signal in said first half cycle, and said second sensing and storing means being enabled by said clock signal such that it is sensing and storing said valid data signal in said second half cycle; a means for directing said valid data signal from said logic circuit portion to said first and second sensing and storing means in response to said clock signal, wherein said valid data signal is passed from said logic circuit portion to said first sensing and storing means in said first half cycle and said valid data signal is passed from said logic circuit portion to said said second sensing and storing means in said second half cycle; first and second multiplexer means for generating a digital output signal in response to said valid data signal stored by said first and second sensing and storing means, said first multiplexer means being enabled by said clock signal during said first half cycle and said second multiplexer means being enabled during said second half cycle; wherein, when said said first multiplexer means is enabled during said first half cycle, said first multiplexer means couples said first voltage to the output of said circuit topology when said valid data signal corresponds to said first logic state and couples said second voltage to said output of said circuit topology when said valid data signal corresponds to said second logic state; and wherein, when said said second multiplexer means is enabled during said second half cycle, said second multiplexer means couples said first voltage to the output of said circuit topology when said valid data signal corresponds to said first logic state and couples said second voltage to said output of said circuit topology when said valid data signal corresponds to said second logic state; said pulse signal and said clock signal being synchronized with respect to one another such that said logic circuit portion is enabled no longer than the amount of time necessary to transfer said valid data to said each of said first and second sensing and storing means and said each of said first and second sensing and storing means is enabled no longer than the amount of time necessary to sense and store said valid data signal.

19. The digital circuit topology described in claim 18 wherein said first multiplexer means comprises first and second transmission gates each having a control terminal, an input terminal and an output terminal, said first transmission gate's control terminal being coupled to said valid data signal, said first transmission gate's input terminal being coupled to said first voltage and said first transmission gate's output terminal being coupled to said output of said circuit topology, said second transmission gate's control terminal being coupled to said inverse of said valid data signal, said second transmission gate's input terminal being coupled to said second voltage and said second transmission gate's output terminal being coupled to said output of said circuit topology, and wherein said second multiplexer means comprises third and fourth transmission gates each having a control terminal, an input terminal and an output terminal, said third transmission gate's control terminal being coupled to said valid data signal, said third transmission gate's input terminal being coupled to said first voltage and said third transmission gate's output terminal being coupled to said output of said circuit topology, said fourth transmission gate's control terminal being coupled to said inverse of said valid data signal, said fourth transmission gate's input terminal being coupled to said second voltage and said fourth transmission gate's output terminal being coupled to said output of said circuit topology.

20. The digital circuit topology as described in claim 19 wherein said first, second, third, and fourth transmission gates comprise p-type field effect transistors.

21. The digital circuit topology as described in claim 19 wherein said first, second, third, and fourth transmission gates comprise n-type field effect transistors.

22. The digital circuit topology described in claim 20 and 21 wherein said first sensing and storing means comprises a first latched sense amplifier and said second sensing and storing means comprises a second latched sense amplifier.

23. The digital circuit topology described in claim 22 wherein the absolute value of the difference between said first and second voltages is less than 600mV.

24. A digital circuit topology comprising: a pulse signal, said pulse signal transitioning between a first logic state and a second logic state; a logic circuit portion for generating a valid data signal, said logic circuit portion being controlled by said pulse signal such that when said pulse signal is in said first logic state, said logic circuit portion outputs said valid data signal and when said pulse signal is in said second logic state, said logic circuit portion is disabled; a plurality of clock signals, each of said plurality of clock signals being characterized by a different phase and each of said plurality of clock signals fluctuating between a voltage corresponding to said first logic state a voltage corresponding to said second logic state; a plurality of means for sensing and storing said valid data signal, each of said plurality of sensing and storing means being enabled by one of said plurality of clock signals, wherein only one of said plurality of sensing and storing means is enabled at a time; a means for directing said valid data from said logic circuit portion to said one of said plurality of sensing and storing means when said one of said plurality of sensing and storing means is enabled; a plurality of multiplexer means for generating a digital output signal in response to said valid data signal stored by a corresponding one of said plurality of sensing and storing means when said corresponding one of said plurality of sensing and storing means is enabled; wherein each of said plurality of multiplexing means coupling said first voltage to the output of said circuit topology when said valid data signal corresponds to a first logic state and coupling a second voltage to said output when said valid data signal corresponds to a second logic state; said pulse signal and said plurality of clock signals being synchronized with respect to one another such that said logic circuit portion is enabled no longer than the amount of time necessary to transfer said valid data to said each of said said plurality of sensing and storing means and said each of said said plurality of sensing and storing means being enabled no longer than the amount of time necessary to sense and store said valid data signal.

25. The digital circuit topology- described in claim 24 wherein said each of said plurality of multiplexer means comprises a first transmission gate having its control terminal coupled to said valid data signal, its input terminal coupled to said first voltage and its output terminal coupled to said output of said circuit topology and a second transmission gate having its control terminal coupled to said inverse of said valid data signal, its input terminal coupled to said second voltage and its output terminal coupled to said output of said circuit topology.

26. The topology as described in claim 25 wherein said first and second transmission gates comprise p-type field effect transistors.

27. The topology as described in claim 25 wherein said first and second transmission gates comprise n-type field effect transistors.

28. The topology described in claim 26 and 27 wherein said each of said sensing and storing means comprises a latched sense amplifier.

29. The topology described in claim 28 wherein the absolute value of the difference between said first and second voltages is less than 600 mV.

30. A circuit topology for driving an interconnect bus with an output digital signal comprising: a logic circuit portion for generating a first digital signal, said logic circuit portion including at least one variable current source that is constantly enabled and at least one variable load device, said at least one variable load device determining the output swing of said first digital signal; a first adjustable voltage coupled to said at least one variable current source for setting the amount of current drive supplied by said at least one variable current source; a second adjustable voltage coupled to said at least one variable load device for setting the conductiviey of said at least one variable load device; a variable frequency clock signal which fluctuates between a voltage corresponding to a first logic state and a voltage corresponding to a second logic state; a means for sensing and storing the logic state of said first digital signal, said means being responsive to said variable frequency clock signal such that when said said variable frequency clock signal is in said first logic state said means is sensing and storing said first digital signal and when said variable frequency clock signal is in said second logic state said means is disabled; a multiplexer means for generating said output digital signal, said multiplexer means having first and second control inputs and first and second data inputs, said first control input being coupled to said first digital signal, said second control input being coupled to the inverse of said first digital signal, said first data input being coupled to a first voltage and said second data input being coupled to a second voltage, said multiplexer means coupling said first voltage to said interconnect bus when said said first digital signal is at a voltage corresponding to said first logic state and coupling said second voltage to said interconnect bus when said said first digital signal is at a voltage corresponding to said second logic state; a frequency-to-voltage converter feedback means for adjusting said first adjustable voltage with respect to variation of frequency in said variable frequency clock signal, said first adjustable voltage being adjusted such that the power consumed by said at least one variable current source is no greater than the amount of power required to drive said sensing and storing means and said multiplexer means with said first digital signal; said frequency-to-voltage converter feedback means also adjusting said second adjsutable voltage with respect to said first adjsutable voltage, said second adjustable voltage being adjusted such that said output swing of said first digital signal remains constant, said frequency- to-voltage converter feedback means being coupled between said sensing means and said logic circuit means.