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WO1996003807A1 - Topologie de circuit numerique a retard d'energie ameliore - Google Patents

Topologie de circuit numerique a retard d'energie ameliore Download PDF

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Publication number
WO1996003807A1
WO1996003807A1 PCT/US1995/009349 US9509349W WO9603807A1 WO 1996003807 A1 WO1996003807 A1 WO 1996003807A1 US 9509349 W US9509349 W US 9509349W WO 9603807 A1 WO9603807 A1 WO 9603807A1
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WO
WIPO (PCT)
Prior art keywords
signal
coupled
voltage
logic
valid data
Prior art date
Application number
PCT/US1995/009349
Other languages
English (en)
Inventor
Graham Y. Mostyn
William H. Herndon
John P. Moussouris
Timothy B. Robinson
Geert P. Rosseel
Original Assignee
Microunity Systems Engineering, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microunity Systems Engineering, Inc. filed Critical Microunity Systems Engineering, Inc.
Priority to AU31443/95A priority Critical patent/AU3144395A/en
Publication of WO1996003807A1 publication Critical patent/WO1996003807A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Definitions

  • the present invention relates to the field of digital circuit design and particularly to the power characteristics of digital circuit topologies.
  • One particularly common circuit topology includes two portions, a core logic portion (50) and a line driver or buffer portion (53), as shown in
  • core logic portion 50 comprises many logic gates such as AND or OR gates.
  • core logic 50 may comprise memory cell devices. In either case, the core logic portion performs some logical function in response to digital input signal/signals 49, and outputs intermediate digital signal 51. Because the core logic portion typically comprises low current logic gates, the core logic portion has low current drive capability and cannot drive high capacitance loads.
  • Intermediate signal 51 is coupled to buffer 53.
  • buffer 53 is located relatively close to core logic 50 such that interconnect lines are relatively short.
  • buffer 53 represents a relatively small amount of capacitive loading to core logic 50 due to interconnect line capacitance.
  • Buffer 53 functions to boost the current level of intermediate signal 51 so as to enable charging a highly capacitive load (56).
  • Capacitive load 56 typically represents a long interconnect line coupled to another core logic portion or possibly an integrated circuit input/output pad.
  • the core logic/buffer topology shown in Figure 1 may be designed with many types of logic gates.
  • One commonly utilized type of logic gate comprises complementary devices (such as complementary metal oxide silicon (CMOS) devices).
  • CMOS complementary metal oxide silicon
  • this type of gate consists of complementary switches 16 and 17 that connect either a positive or negative supply voltage (VDD and VSS) to capacitive load 21 in response to input signal 20.
  • VDD and VSS positive or negative supply voltage
  • FIG. 2C shows VOUT (Figure 2A) for a square wave input signal V20 that alternates between VDD and VSS.
  • VOUT transitions between VDD and VSS, making the peak-to-peak voltage (Vp-p) swing of the digital signal at the output of the logic gate equal to the difference between the positive and negative supply voltages, (VDD - VSS).
  • Vp-p peak-to-peak voltage
  • this Vp-p voltage is considered to be relatively large when compared with other available logic gate designs.
  • Figure 2B illustrates a complementary-type logic gate implemented with CMOS devices.
  • the Vp-p for this logic gate is typically 3.0 - 5.0 Vp- p.
  • the logic gate shown in Figure 2B functions such that when input signal 20 is a high voltage, device 17 is on and device 16 is off. In this state VOUT is coupled to VSS. When input signal 20 is a low voltage, device 17 is off and device 16 is on. When this occurs, VOUT is coupled to VDD.
  • the complementary-type logic gate shown in Figure 2A dissipates power only during state transitions, i.e. when charging load 21. This feature makes the complementary-type logic gate very power efficient when it is not switching states very frequently. However, since this type of logic gate outputs a signal having a relatively large Vp-p, the amount of power dissipated to drive a capacitive load is relatively high when compared to other logic gates, particularly when the capacitive load is large. As described above, buffer 13 drives a relatively large capacitive load. Consequently, buffers, (such as buffer 13), implemented with complementary-type logic gates become very power inefficient when they are switched relatively frequently. Another type of logic gate that is utilized to implement the circuit topology illustrated in Figure 1 is shown in Figure 3A.
  • a gate designed in this manner typically has a current source (22) coupled between a first working potential (23) and two matched parallel discrete devices (24 and 25).
  • Reference voltage, VI provides the drive for current source 22 so that it supplies a constant current.
  • Each one of a pair of identical loads (26 and 27) are coupled between one of the matched devices and a second working potential (28).
  • Input signals, Vin and Vin/ are coupled to each of the inputs of matched devices 24 and 25.
  • the output of the gate is taken at either one or both of lines 30 and 31 (depending on whether a single-ended signal or a differential signal is desired).
  • one device Since Vin and Vin/ are the inverse of each other, one device has a voltage corresponding to a high logic state on its input and the other has a voltage corresponding to a low logic state on its input. As a result, one device is on and the other is off. When this occurs, most of the current supplied by current source 22 is routed through the on-device and its respective load device, while relatively no current flows through the off- device and its respective load. Consequently, a larger voltage is developed across one load device than the other. For example, if all of the current is routed through device 25 and load 27, output line 30 is at a voltage that represents a logical high state and output line 31 is at a voltage that represents a logical low state.
  • the difference between the logic high and low voltages is the peak-to-peak voltage swing of the logic gate.
  • the magnitude of the Vp-p for the logic gate shown in Figure 3A is determined by the amount of current flowing through the resistive load and the resistance of each load. Consequently, it is possible to select the Vp-p swing of this gate such that it is relatively small.
  • the Vp-p voltage of the logic gate shown in Figure 3A is typically selected to be less than the Vp-p of the complementary-type logic gate shown in Figure 2B.
  • One widely utilized example of the logic gate shown in Figure 3A is the emitter-coupled logic (ECL) gate, shown in Figure 3B.
  • ECL emitter-coupled logic
  • the logic gate shown in Figure 3A characteristically has a quiescent power consumption due to constant current source 22. Thus, even when it is not switching states, it is dissipating power. However, due to its relatively small Vp-p swing, the logic gate shown in Figure 3A dissipates relatively less power to charge/discharge a given capacitive load than the complementary-type logic gate - especially when the given capacitive load is relatively large.
  • buffer 13 ( Figure 1) is implemented in ECL-type of logic gates (as shown in Figures 3A and 3B), it is more power efficient than the complementary-type logic gate when the logic gate is frequently switched - but is less power efficient when it is switching relatively infrequently due to its quiescent power dissipation feature.
  • the present invention is an improvement to the digital circuit topology shown in Figure 1.
  • the improved topology includes a buffer having low Vp-p output voltage characteristics like the ECL-type of logic gate (as shown in Figure 3) and having the static power characteristic of the CMOS-type logic gate technology (as shown in Figure 2).
  • the low peak-to-peak voltage swing results in reduced power dissipation when charging and discharging loads. While, reduced static power consumption results in power savings during periods when logic states are not switched.
  • the present invention provides other improvements to the digital topology shown in Figure 1 so that overall power dissipation for this topology is reduced.
  • the present invention relates to digital circuit topologies that include a logical core portion and a bus driver/buffer portion.
  • the improvement of the present invention is a unique output buffer that generates a relatively small output swing and does not dissipate quiescent power.
  • Another aspect of the present invention reduces quiescent power consumption by pulsing the core logic portion.
  • the core logic portion in the topology of the present invention may be implemented in any type of logic gate. Accordingly, in one embodiment of the present invention the core logic portion substantially comprises logic gate types that characteristically dissipate quiescent power and have small Vp-p swings. In another embodiment of the present invention the core logic portion substantially comprises complementary-type logic gates. The core logic portion outputs an intermediate signal. This intermediate signal and its inverse are coupled to the buffer of the present invention.
  • the output buffer of the present invention In response to the intermediate signal and its inverse, the output buffer of the present invention generates an output digital signal.
  • the buffer generates the output digital signal by multiplexing first and second reference voltages onto the output of the buffer.
  • the first and second reference voltages are very close in magnitude so that the output of the buffer is driven by a digital signal having a very small Vp-p swing.
  • the output buffer is implemented with first and second transmission gates comprising p-type field effect transistors (PFETs).
  • the transmission gates comprise n-type FETs (NFETs). Since the buffer of the present invention does not utilize constant current sources, no quiescent power is dissipated.
  • the buffer is designed to output a differential signal.
  • two sets of transmission gates are coupled to the output of the core logic; each set of transmission gates providing an output signal that is inversely related to the other output signal.
  • a gain stage is coupled between the core logic portion and the buffer of the present invention.
  • the gain stage converts small Vp-p intermediate signals into signals having large voltage swings. This is done so that the on- resistance of the transmission gates is minimized when PFETs or NFETs are utilized in the buffer.
  • Still another embodiment of the present invention relates to digital circuit topologies having core logic comprising logic gates that dissipate quiescent power.
  • the current sources within the core logic portion are pulsed at a predetermined rate. Pulsing the current sources enables the core logic for short intervals. These intervals are long enough to pass the data from the logic portion to a latched sense amplifier.
  • the pulse is removed from the current sources.
  • the frequency of the core logic pulse and sense amplifier clock are selected so that the overall power characteristic of this topology is optimized.
  • a variation of this embodiment involves setting the amount of drive supplied by the current sources in the core logic portion with respect to the clock frequency of the sense amplifier/latch.
  • Figure 1 illustrates a block diagram of a digital circuit topology including a logic block and a buffer.
  • Figure 2A is a block diagram of a complementary-type logic gate.
  • Figure 2B is a complementary-type logic gate comprising CMOS devices.
  • Figure 2C are the input and output timing diagrams for the logic gates shown in Figure 2A and 2B.
  • Figure 3A is a block diagram of a type of logic gate that dissipates quiescent power.
  • Figure 3B is an emitter-coupled logic (ECL) gate.
  • Figure 3C is the timing diagram of the output voltage for the logic gate shown in Figure 3B.
  • Figure 4 is a block diagram of an embodiment of the improved digital circuit topology of the present invention including the improved buffer of the present invention.
  • Figure 5 illustrates the embodiment of the present invention shown in Figure 4 with the buffer of the present invention implemented in p-type field effect transistors.
  • Figure 6 shows an embodiment of the improved digital circuit topology of the present invention having the logic block portion being implemented in ECL-type devices.
  • Figure 7 illustrates an embodiment of the improved digital circuit topology of the present invention having the logic block portion being implemented in CMOS-type devices.
  • Figure 8 is a differential version of the improved circuit topology of the present invention in which the logic block portion is implemented in ECL-type devices.
  • Figure 9 illustrates a differential version of the improved circuit topology of the present invention in which the logic block portion is implemented in CMOS-type devices.
  • Figure 10 is an embodiment of the circuit topology of the present invention in which the core logic portion is pulsed to reduce the quiescent power consumption of the logic block.
  • Figure 11 illustrates the timing diagrams for the logic block strobe signal and the sense amplifier clock signal.
  • Figure 12 illustrates a variation of the embodiment shown in Figure 10, including two alternately enabled sense amplifiers and buffers.
  • Figure 13 is the timing diagram for Figure 12.
  • Figure 14 is the topology illustrated in Figure 12, showing the sense amplifier portion in schematic form.
  • Figure 15 is the timing diagram for Figure 14.
  • Figure 16 is another alternative embodiment of the present invention which includes a frequency-to-voltage converter that adjusts current drive within the logic block to optimize the power consumption of the logic block with respect to the sense amplifier clock frequency.
  • the present invention improves the power efficiency of the topology shown in Figure 1 by 1) providing a buffer design that has no quiescent power dissipation and that generates an output signal having a relatively small voltage swing, and 2) providing an improved topology design that reduces the quiescent power dissipation of logic block 50 when it is designed with ECL-type logic.
  • Figure 4 illustrates a block diagram of a core logic/buffer digital topology including the improved buffer of the present invention.
  • the topology comprises logic block 50 and output buffer 53.
  • logic block 50 provides either a digital high or low output voltage (corresponding to either a high or low logic state) onto interconnect line 51.
  • logic block 50 is implemented in complementary-type logic gates such as that illustrated in Figure 2A.
  • the output signal on interconnect line 51 has a relatively large peak-to-peak voltage swing (equal to the difference between the positive and negative supply voltages).
  • the core logic portion comprises ECL-type logic gates. In this case, the output signal on interconnect line 51 has a small Vp-p swing.
  • Capacitor 52 ( Figure 4) represents the capacitive loading contributed by interconnect line 51 and the input of buffer 53. Since the length of interconnect line 51 is usually designed to be relatively short, and since the input capacitance of buffer 53 tends to be small, capacitor 52 represents a relatively small capacitive load (approximately 10 - 100 fF).
  • Buffer 53 of the digital circuit topology of the present invention comprises multiplexer 54.
  • Multiplexer 54 functions as a basic multiplexer. As is well known in the art, multiplexers basically have a set of n input data signals that are applied to the multiplexers input data inputs. A set of control signals are applied to the multiplexers control inputs. The control signals indicate which one of the n input data signals is to appear at the output of the multiplexer.
  • Multiplexer 54 of the present invention has voltage V1 applied to a first information input and V2 coupled to a second information input.
  • the digital signal on line 51 is applied to a first control input and the inverse of the signal on line 51 is applied to a second control input.
  • multiplexer 54 couples either V1 or V2 to its output (interconnect line 55) causing line 55 to transition between V1 and V2.
  • a digital signal (corresponding to the digital signal on interconnect line 51) is coupled onto interconnect line 55.
  • Voltages V1 and V2 are selected to have magnitudes that are relatively close in value so that the Vp-p swing on line 55 is relatively small. Voltage swings in the range of 200 mV are possible.
  • Multiplexer 54 is designed so that it only dissipates power when charging and discharging capacitive load 56.
  • Load capacitance 56 represents a relatively large capacitive load, such as a long interconnect line or an internal input/output (I/O) pad, typically greater than 300 fF.
  • reference voltages V1 and V2 may both be independently generated.
  • V1 is equal to the supply voltage, VDD, coupled from another portion of the circuit and V2 is generated independently; V2 having a magnitude close in value to VDD.
  • the buffer of the present invention generates a digital signal having a small Vp-p like an ECL-type of logic gate and like the complementary-type logic gate it dissipates no quiescent power. As a result, it is extremely power efficient whether it is changing states frequently or infrequently.
  • Figure 5 shows the core logic/buffer topology of the present invention with buffer 53 implemented utilizing two p-type field effect transistors (FETs), coupled as parallel transmission gates.
  • FETs field effect transistors
  • a transmission gate is defined as a device having an input terminal, and output terminal and a control terminal.
  • a transmission gate functions such that it couples the voltage on its input terminal through a low resistive path to its output terminal in response to a given voltage applied to its control terminal.
  • the control terminal of device 57 is coupled to interconnect 51.
  • the input terminal of device 57 is coupled to VDD and its output terminal is coupled to interconnect line 55.
  • Interconnect line 51 is also coupled to to the control terminal of device 58 through inverter 59.
  • the input terminal of device 58 is coupled to V2 and its output terminal is coupled to interconnect line 55.
  • the PFET devices function such that when the digital signal on line 51 is high, device 57 is off and device 58 is on. When this occurs, device 58 passes V2 to interconnect line 55.
  • the digital signal on line 51 is low, device 58 is off and device 57 is on.
  • VDD is coupled to interconnect line 55.
  • interconnect line 55 transitions between VDD and V2.
  • the transmission gates may also be implemented in n-type FETs. In this case, the node shown as VDD becomes the most negative supply voltage (commonly referred to as VSS) and V2 becomes a voltage slightly more positive than VSS.
  • logic block 50 may be implemented utilizing many types of logic gate designs. If logic block 50 is implemented with logic gates that generate a digital signal having a small Vp-p swing, it is desirable to convert the small Vp-p signal to a large Vp-p signal. Increasing the Vp-p swing of the signal ensures that the PFETs operate with low on-resistance (for moderately sized devices). By ensuring that the PFETs are operated in their low on-resistance region, the frequency response of the buffer of the present invention is increased.
  • logic block 50 is implemented with logic gates that produce a digital signal having a small Vp-p swing.
  • line 51 is driven with a small Vp-p signal.
  • This embodiment of the present invention also includes gain stage 60 coupled between core logic portion 50 and buffer 53.
  • Gain stage 60 functions to convert the small swing digital signal on line 51 to a large swing signal and couple it to the control gates of PFET devices 57 and 58.
  • Gain stage 60 provides a large Vp-p swing output signal (on line 61) and an inverse output signal (on line 62).
  • the logical state of the signal on interconnect line 61 corresponds to the logical state of the digital signal on line 51.
  • PFETs 57 and 58 function in the same manner as described in the embodiment shown in Figure 5, i.e. coupling either VDD or V2 onto line 55.
  • gain stage 60 may be implemented as a sense amplifier that compares the input signal on line 51 to a given reference voltage. If the input signal on line 51 is higher than the reference voltage, gain stage 60 outputs a voltage corresponding to a high logic state onto line 61. If signal 51 is lower than the reference voltage, then stage 60 outputs a voltage corresponding to a low logic state onto line 61.
  • Figure 7 illustrates still another embodiment of the present invention in which logic block 50 is implemented in complementary-type logic and buffer 53 interfaces with a complementary-type logic block (logic block 64).
  • Complementary-type logic blocks 50 and 64 are only compatible with digital signals having large Vp-p swings.
  • logic blocks 50 and 64 generate digital signals having large Vp-p swings. Consequently, unlike the ECL-type logic implementation shown in Figure 6, the signal from logic block 50 is directly coupled to buffer 53.
  • the implementation shown in Figure 7 does not require gain stage 60 ( Figure 6) to boost the voltage levels of the digital signals on line 51.
  • buffer 53 generates a digital signal on interconnect line 55 having Vp-p swing equal to VDD - V2.
  • Interconnect 55 transmits this small Vp-p swing signal to logic block 64 (located remotely from 53) through gain stage 63.
  • Gain stage 63 converts the small Vp-p swing signal on line 55 to a large Vp-p swing signal compatible with complementary-type logic block 64. It should be noted that the input capacitance of logic block 64 is relatively small. Consequently, little power is dissipated by gain stage 63.
  • FIG. 4 illustrates a differential embodiment of the present invention in which buffer 53 outputs a digital signal (OUT) and the inverse of that digital signal (OUT ).
  • logic block 50 is designed utilizing ECL-type logic gates. Consequently, the signal on line 51 is converted to a large swing signal by gain stage 60 to ensure that the PFET devices are driven by a large Vp-p signal.
  • the differential output of gain stage 60 is coupled to two pairs of PFETs.
  • PFETs 57 and 58 have their control inputs coupled to interconnect lines 61 and 62 respectively.
  • Interconnect lines 61 and 62 are also coupled to the control inputs of PFETs 64 and 65.
  • the signal on interconnect line 61 is the inverse of the signal on line 62.
  • V2 is coupled to OUT and VDD is coupled to OUT/.
  • interconnect line 61 is low and line 62 is high, devices 57 and 65 are on and devices 58 and 64 are off.
  • VDD is coupled to OUT and V2 is coupled to OUT/.
  • buffer 53 generates two signals that transition between VDD and V2 - each being the inverse of the other.
  • Figure 9 illustrates another differential embodiment of the present invention.
  • logic block 50 is implemented in complementary-type logic gates.
  • block 50 generates a differential signal onto lines 51 and 51'.
  • This differential signal is coupled directly into buffer 53.
  • Buffer 53 comprises PFETs 57, 58 and 64 and 65.
  • Buffer 53 ( Figure 9) generates a differential signal on lines OUT and OUT/ in response to the differential signal on lines 51 and 51' in the same manner as described in Figure 8.
  • the differential signal on OUT and OUT/ is transmitted to another logic block 64 within the digital circuit.
  • Gain stage 63 converts the small Vp-p swing signal on lines OUT and OUT/ to a large Vp-p swing signal compatible with complementary-type logic block 64. It should be noted that the input capacitance of logic block 64 is relatively small. Consequently, little power is dissipated by gain stage 63.
  • gain stage 63 ( Figure 7) is typically a comparison stage - such as a sense amplifier - that compares the signal on line 55 to a reference voltage.
  • this reference voltage may fluctuate and cause gain stage 63 to output the wrong logic level.
  • the differential implementations of the present invention (shown in Figure 9) compares the signal on line 55 (OUT) to its inverse (OUT/). As a result, if power supply noise occurs, OUT and OUT/ fluctuate concurrently so that the noise cancels itself out. Consequently, the differential implementation shown in Figures 8 and 9 are less susceptible to noise related errors and are typically more robust.
  • Gain stage 60 Another aspect of the present invention relates to the circuit topology shown in Figure 6, specifically, to a circuit topology in which logic block 50 is implemented in a type of logic gate that dissipates quiescent power due to logic gates utilizing constant current sources.
  • current source 22 is biased by reference voltage (VI) such that it provides a constant current.
  • V reference voltage
  • gain stage 60 as described in the embodiment shown in Figure 6, typically is implemented as a sense amplifier. Sense amplifiers also comprise constant current sources. As a result, gain stage 60 further adds to the quiescent power dissipation of the topology shown in Figure 6.
  • the embodiment of the present invention shown in Figure 10 eliminates the quiescent power dissipation of logic block 50 (when it is implemented with the logic gate type shown in Figure 3A) and eliminates the quiescent power dissipation of its associated gain stage.
  • Figure 10 includes strobed logic block 50, latched sense amplifier 68, and the buffer of the present invention implemented with two PFETs (as described above).
  • Strobe signal 69 is coupled to all of the logic gates' current sources within logic block 50. Referring to the timing diagram shown in Figure 11 , when strobe signal 69 is at some voltage, V(on), the logic gates' current sources are on. In this case, the logic gates are activated and dissipating power. When signal 69 is at a voltage equal to V(off), the current sources are off and the logic gates are not dissipating power.
  • Clock 70 is the enable signal for sense amplifier 68. Referring to Figure 11 when clock signal 70 is high, sense amplifier 68 (SA68) is enabled and captures the logic state present on line 51. During this time, SA68 is dissipating power. When signal 70 is low, SA68 is no longer dissipating power.
  • Logic block 50 is strobed by signal 69 when the input conditions on lines 49 are expected to change. Strobing in this manner ensures that logic block 50 is activated such that all input condition changes are detected. For example, if logic block 50 is designed as a synchronous system and state changes occur on clock transitions, then strobing would occur for a short period on every clock edge.
  • input signals 49 Figure 10
  • Strobe 69 is applied long enough to ensure that line 51 reaches the new logic state. The required pulse duration of strobe 69 is dependent on the RC constant of line 51 and the amount of current drive supplied by the logic gates' current sources.
  • Sense amplifier 68 is not clocked until line 51 is fully charged. Thus, it is not dissipating quiescent power until it is enabled by signal 70.
  • sense amplifier 68 When line 51 is fully charged to a voltage potential equal to either a high or low logic level, sense amplifier 68 is clocked by signal 70. The latched sense amplifier is responsive to the positive edge transition (indicated by 200 in Figure 11) of clock signal 70. At this time, the logic state on line 51 is latched into sense amplifier 68 and lines 61 and 62. Once the state of the sense amplifier is stable, the strobe 69 transitions to V(off). With strobe 69 at V(off), the current sources in logic block 50 are turned off. The latched logic state on lines 61 and 62 drive transmission gates 57 and 58 in the same manner as described with previous embodiments.
  • Figure 12 illustrates a variation of the embodiment shown in Figure 10.
  • two sense amplifiers are utilized to store the state changes from logic block 50.
  • This allows logic block 50 to transfer data twice every sense amplifier clock cycle, (i.e. once on the rising edge of the clock cycle and once on the falling edge of the clock cycle), instead of being sensed once every clock cycle as in the previous embodiment shown in Figure 10.
  • multiplexer 200 is coupled to the output of logic block 50. It functions to direct the data on line 51 to either sense amplifier 201 or 202.
  • Multiplexer 200 is responsive to the rising and falling edges of system clock signal PHI, so that data is passed to either sense amplifier 201 or 202 every half clock cycle.
  • multiplexer 200 couples the logic state on line 51 to the input of sense amplifier 201 , node 1.
  • multiplexer 200 couples the logic state of line 51 to the input of sense amplifier 202, node 2.
  • Sense amplifier 201 is enabled by clock signal PHIA when the data on line 51 is directed to node 1.
  • Sense amplifier 202 is enabled by clock signal PHIB when the data on line 51 is directed to data path 2.
  • the output of each of the sense amplifiers controls each of the multiplexer buffers 203 and 204. Specifically, sense amplifier 201 controls MUX 203 in one half cycle. Alternately, sense amplifier 202 controls MUX 204 in the the other half cycle.
  • Figure 13 is the timing diagram for the topology shown in Figure
  • strobe signal 69 transitions low to high (indicated by 205, Figure 13)
  • logic block 50 is enabled and begins to charge capacitor 52 with a voltage corresponding to either a high or. low logic state.
  • line 51 reaches a stable state at time T1
  • PHI transitions high (indicated by 206, Figure 13), and couples the data on line 51 to node 1.
  • strobe signal 69 transitions low so that logic block 50 no longer consumes any power.
  • PHIA transitions high (indicated by 207, Figure 13) and enables sense amplifier 201 and MUX 203.
  • Sense amp 201 latches the logic state sensed on node 1 to OUTA.
  • the signal on OUTA controls MUX 203 so that it drives output line 55 with either V1 or V2 (depending on the data sensed during the first pulse of strobe signal 69).
  • logic block 50 charges capacitor 52 with a voltage level corresponding to a new logic state.
  • line 51 is stable at T2, PHI transitions high-to-low (indicated by 208, Figure 13). When this occurs, the data on line 51 is coupled to node 2.
  • sense amp 202 and MUX 204 are enabled when signal PHIB transitions low-to-high (indicated by 209, Figure 13). After which, MUX 204 couples either V1 or V2 to line 55 (depending on the data sensed during pulse 2).
  • strobe signal 69 provides a pulse twice per clock cycle T, resulting in data transfer twice per clock period.
  • Figure 14 illustrates one schematic implementation of the sense amplifier/latches shown in Figure 12.
  • sense amplifier/latch 201 comprises devices 207 - 211 and sense amplifier/latch 202 comprises devices 212 - 216.
  • NMOS Devices 211 and 216 function as current sources for sense amplifier/latches 201 and 202, respectively.
  • Each sense amplifier/latch functions to compare its input node (line 51) to VREF when its corresponding current source is enabled. If the voltage on its input node is higher than VREF, then the sense amplifier latches a voltage level corresponding to a high logic level (VDD) on its non-inverted output (node 1 for SA201 and node 2 for SA202) and a low logic level (VSS) on its inverted output (node 3 for SA201 and node 4 for SA202). When the voltage on its input node is lower than VREF, then the sense amplifier latches a voltage level corresponding to a low logic level on its non-inverted output and a high on its inverted output.
  • VDD high logic level
  • VSS low logic level
  • Clock signals PHI2 and PHI4 are the enable signals for each of NMOS current source devices 211 and 216.
  • PHI2 When PHI2 is high, device 211 is on. In this state, SA201 is sensing the data on line 51 and driving PFETs 57 and 58.
  • PHI4 When PHI4 is high, device 216 is on and SA202 is sensing data on line 51 and driving PFETs 64 and 65.
  • PMOS devices 205 and 217 function as SA201's pass gates.
  • PMOS devices 206 and 218 function as SA202's pass gates.
  • Clock signal PHI1 controls devices 205 and 217
  • clock signal PHI3 controls devices 206 and 218.
  • Clock signals PHI1 and PHI3 are inversely related. As a result, when devices 205 and 217 are on, 206 and 218 are off. Conversely, when devices 205 and 217 are off, devices 206 and 218 are on. In this way, data on line 51 is passed to only one sense amplifier/latch at a time.
  • PFETs 57, 58, 64, and 65 function in the same manner as described in the embodiments shown in Figures 8 and 9.
  • PHI1 and PHI2 are high so that pass gate devices 205 and 217 are off and SA201's current source device 211 is on.
  • SA201 is providing a previously latched logic level to PFETs 57 and 58.
  • PHI4 is low such that SA202's current source is off.
  • SA201 is driving line 55 with a previously latched data and SA202 is disabled.
  • logic block 50 is disabled (PHI5 is low) and PHI3 is low such that SA202's pass gates (206 and 218) are on.
  • PHI5 is low
  • PHI3 is low
  • SA202's pass gates 206 and 2128 are on.
  • the voltage on node 51 is applied to the gate of device 64 and VREF is applied to the gate of device 65.
  • VREF is set to a voltage more positive than the threshold voltage of devices 65. Additionally, it is necessary to ensure that the voltage on line 51 is higher than the threshold voltage on device 64.
  • the voltage on line 51 is dependent on the disabled output voltage of logic block 50 which, in turn, is dependent on the internal logic of logic block 50.
  • logic block 50 is implemented such that when it is disabled, its output (line 51) rises to a voltage close to the most positive power supply voltage (VDD). This ensures that the voltage on line 51 is high enough to keep device 64 off.
  • VDD most positive power supply voltage
  • PHI5 transitions from low-to-high and logic block 50 is enabled.
  • logic block 50 begins to charge capacitor 52 to a voltage corresponding to either a high or low voltage level
  • a differential voltage is latched across nodes 2 and 4 that corresponds to the logic level sensed on line 51.
  • the voltage on nodes 2 and 4 drive PFET devices 64 and 65 which, in turn, drive output line 55 to a voltage corresponding to the logic level sensed on line 51.
  • PHI1 transitions high-to-low and PHI3 transitions low- to-high.
  • SA201's current source is still off and SA202's current source is still on at time T3. Consequently, output line 55 is driven by SA202.
  • PHI5 provides bias voltage VI (refer to Figure 3A and 3B) to logic gate current sources when logic block 50 is enabled.
  • the amount of current generated by each current source, and consequently the time averaged power dissipated by logic block 50 is directly proportional to the magnitude (V PH
  • 5 the magnitude of current generated by each current source
  • 5 pulse width
  • a pulse having a large V PHI5 and a long t PHI5 causes logic block 50 to dissipate more time averaged power than a pulse having a small V PHI5 and a relatively short t PH
  • Time averaged power dissipation in the embodiment shown in Figure 14 is optimized by selecting pulse magnitude (V PHI5 ) and pulse width (t PHI5 ) such that it causes logic block 50 to dissipate the least amount of time-averaged power for a given PHI1 - PHI4 clock frequency. This is achieved by selecting minimum values for V PHI5 and t PHI5 to ensure that 1) PHI5 is at a high voltage level long enough for the state change on line 51 to be captured by either of the sense amplifiers in a specific time interval (set by tp H is). and 2 ) enough current drive is supplied by logic block 50 so that the logic state on line 51 is stable in that time interval (set by V PHI5 ).
  • PHI5 may also be a digital signal that controls the magnitude and duration of a signal supplied by a variable current bias source.
  • PHI5 instead of adjusting the pulse width and magnitude of PHI5 for optimization, PHI5 is set so that it controls the variable current bias source to provide a signal that ensures power optimization.
  • V PHI5 and t PHI5 are set so that the state of line 51 is charged to its appropriate logic level within interval 221 , i.e. when SA202's pass gate and current source are on. In this way, the logic state on line 51 is reliably captured by SA202. Any values for V PHI5 and t PHI5 over the optimized value translates into unnecessary power consumption.
  • logic block 50 comprises logic gates that are designed such that VI is a constant voltage and current source 22 is always on (refer to Figure 3A). As a result, logic block 50 dissipates quiescent power. However, the quiescent power dissipation of logic block 50 is optimized by adjusting VI with respect to the frequency of the sense amplifier clock signal.
  • the output of logic block 50 (line 51) is coupled to sense amplifier 68 through pass gate 221.
  • the sense amplifier compares the voltage on line 51 to VREF and outputs a differential signal, OUT and OUT/, corresponding to the logic signal sensed on line 51.
  • This differential signal drives buffer 53 such that it couples either VDD or V2 to output line 55. Optimization of power consumption is achieved by coupling clock signal PHI1 to a frequency-to- voltage converter (shown in Figure 16).
  • the frequency-to-voltage converter generates two voltages scaled to the frequency of clock signal PHH .
  • the first voltage on line 219, V 219 is coupled to each of the current source devices within logic block 50.
  • V 219 functions as the VI (see Figure 3A) for all logic gate current sources.
  • the voltage on line 219 determines the amount of current generated by each of the logic gates and consequently the amount of power consumed by logic block 50
  • the second voltage V 220 is coupled to variable load devices within logic block 50. These variable load devices correspond to resistive loads 26 and 27 in Figure 3A.
  • the variable load devices along with the current supplied by current source 22, determine the output swing of the logic gate and consequently, logic block 50. In most logic circuits, a constant output logic swing is required as the power is varied. Thus, to ensure that the output logic swing remains constant, it is necessary to adjust the resistance of the variable load at the same time that the current drive for each logic gate is adjusted. This is accomplished by scaling V 219 and V 220 simultaneously.
  • Optimum power dissipation for the topology shown in Figure 16 is achieved by adjusting the current drive of a logic block 50 to a minimum value such that logic block 50 drives line 51 with a signal that reaches a stable state in the desired PHI1 time interval. It should be obvious that as the frequency of clock signal PHI1 increases, the output of logic block 50 needs to transition faster to get to the desired logic state within the established time interval. Increasing the current drive of current sources 22 causes the output of logic block 50 to transition faster. Conversely, decreasing the current drive of current sources 22, causes the output of logic block 50 to transition slower. If PHI1 is a high signal frequency, the output of logic block 50 needs to transition relatively fast.
  • V219 needs to be a relatively large voltage potential such that the logic blocks' current sources provide a large current drive.
  • a low frequency PHI1 allows logic block 50 a long time to establish a valid voltage level on line 51. In this case, less current drive is required and thus a smaller voltage potential is generated by V219.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention porte sur une topologie numérique améliorée comportant un bloc logique et une mémoire tampon. La mémoire tampon améliorée est munie d'une première et d'une deuxième grille de transmission, parallèles et de conductivité identique, qui fournissent soit une première (V1) soit une deuxième (V2) tension à la sortie de la mémoire tampon (55) en réponse à un signal logique émanant du bloc logique. Les valeurs des deux tensions sont choisies relativement proches de manière à ce que la tension crête à crête du signal numérique de sortie perçue à la sortie de la mémoire soit relativement faible. Il en résulte une réduction de l'énergie consommée pour charger la sortie de la mémoire tampon, et de plus, les grilles de transmission en parallèle ne consomment d'énergie que lors du chargement de la mémoire tampon, dont la consommation au repos est ainsi supprimée. Cela supprime également la dissipation d'énergie au repos dans certains types de blocs logiques et notamment dans les grilles logiques à source constante de courant. Cela s'obtient en commandant la source de courant à l'aide d'un signal pulsé. La largeur et l'amplitude des impulsions sont choisies pour permettre à un amplificateur de lecture verrouillée de détecter les données valables sortant du bloc logique pendant un intervalle donné. Après détection d'une donnée valable, les sources de courant du bloc logique sont désactivées et le bloc logique ne consomme plus de courant. L'amplificateur de lecture est activé pendant des intervalles suffisamment longs pour pouvoir saisir les données du bloc logique et piloter les grilles de transmission avec les données. Dans cette configuration, aucun des éléments de la topologie ne dissipe d'énergie au repos, puisque aucun ne fonctionne en permanence.
PCT/US1995/009349 1994-07-25 1995-07-25 Topologie de circuit numerique a retard d'energie ameliore WO1996003807A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU31443/95A AU3144395A (en) 1994-07-25 1995-07-25 Digital circuit topology offering an improved power delay product

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28038294A 1994-07-25 1994-07-25
US08/280,382 1994-07-25

Publications (1)

Publication Number Publication Date
WO1996003807A1 true WO1996003807A1 (fr) 1996-02-08

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WO (1) WO1996003807A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030003347A (ko) * 2001-06-30 2003-01-10 황석훈 중금속 폐수 처리 시스템 및 그 처리 방법
KR100468430B1 (ko) * 2001-06-13 2005-01-27 조영봉 슬러지의 자원화를 위한 청정슬러지 또는 청정액체의 제조방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3991379A (en) * 1975-06-03 1976-11-09 United Technologies Corporation Logic level decoding circuit
US4163209A (en) * 1977-09-28 1979-07-31 Harris Corporation Technique for controlling memoryful non-linearities
WO1990016133A1 (fr) * 1989-06-20 1990-12-27 Motorola, Inc. Limiteur de donnees a couplage direct et autosyntonisation d'un recepteur de recherche de personne du type a economie de batterie
GB2276475A (en) * 1993-03-23 1994-09-28 Motorola Inc Generating threshold levels in a radio communication device for receiving four-level signals

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3991379A (en) * 1975-06-03 1976-11-09 United Technologies Corporation Logic level decoding circuit
US4163209A (en) * 1977-09-28 1979-07-31 Harris Corporation Technique for controlling memoryful non-linearities
WO1990016133A1 (fr) * 1989-06-20 1990-12-27 Motorola, Inc. Limiteur de donnees a couplage direct et autosyntonisation d'un recepteur de recherche de personne du type a economie de batterie
GB2276475A (en) * 1993-03-23 1994-09-28 Motorola Inc Generating threshold levels in a radio communication device for receiving four-level signals

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468430B1 (ko) * 2001-06-13 2005-01-27 조영봉 슬러지의 자원화를 위한 청정슬러지 또는 청정액체의 제조방법
KR20030003347A (ko) * 2001-06-30 2003-01-10 황석훈 중금속 폐수 처리 시스템 및 그 처리 방법

Also Published As

Publication number Publication date
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