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WO1996008749A2 - Procede de production d'un composant tridimensionnel ou d'un groupe de composants - Google Patents

Procede de production d'un composant tridimensionnel ou d'un groupe de composants Download PDF

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Publication number
WO1996008749A2
WO1996008749A2 PCT/DE1995/001151 DE9501151W WO9608749A2 WO 1996008749 A2 WO1996008749 A2 WO 1996008749A2 DE 9501151 W DE9501151 W DE 9501151W WO 9608749 A2 WO9608749 A2 WO 9608749A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
structurable
layers
coil
piston
Prior art date
Application number
PCT/DE1995/001151
Other languages
German (de)
English (en)
Other versions
WO1996008749A3 (fr
Inventor
Martina Rothe
Andreas Maciossek
Bernd LÖCHEL
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Publication of WO1996008749A2 publication Critical patent/WO1996008749A2/fr
Publication of WO1996008749A3 publication Critical patent/WO1996008749A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F15—FLUID-PRESSURE ACTUATORS; HYDRAULICS OR PNEUMATICS IN GENERAL
    • F15C—FLUID-CIRCUIT ELEMENTS PREDOMINANTLY USED FOR COMPUTING OR CONTROL PURPOSES
    • F15C5/00—Manufacture of fluid circuit elements; Manufacture of assemblages of such elements integrated circuits
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F41/00—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties
    • H01F41/02—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets
    • H01F41/04—Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformers; Apparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils, or magnets for manufacturing coils
    • H01F41/041—Printed circuit coils
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/0086—Printed inductances on semiconductor substrate

Definitions

  • the invention relates to a method for producing a three-dimensional component or a component group, in particular on surfaces of already processed semiconductor chips.
  • micromechanical or microelectronic components such as three-dimensional micro-coils or transformers directly on surfaces of fully processed electronic components enables, in addition to further miniaturization of the overall structure, the production of previously unrealizable systems while at the same time reducing production costs.
  • the basic structures of known RF-ID systems consist of two hardware components, an information data carrier and one Base station and two physical interfaces between the components.
  • the data exchange takes place via a magnetic or electromagnetic high-frequency field. Frequencies around 125 kHz and a few MHz are common.
  • Systems that work in the information carrier without internal energy supply are particularly interested. These can be made much smaller and also have a longer service life.
  • the design of the communication interface is of particular interest for the future development of these RF-ID systems, i.e. the design of the transmitting and receiving antennas.
  • the information carrier obtains the energy via transformer coupling, i.e. it has a coil as the receiving antenna.
  • the voltage transmission grows with the transmission frequency and the maximum achievable resonant circuit quality. Since high power consumption lowers the quality, future systems must have low energy consumption and the highest possible carrier frequencies. Modern CMOS technology creates the conditions for this.
  • the development is moving towards an increasingly greater miniaturization and ultimately towards a complete integration of the information carrier on a silicon chip, whereby all previously used assembly technologies are superfluous.
  • capacitors and coils With integrated manufacturing, about 1000 RF-ID systems could be produced on a 6 inch Si wafer at the same time and the unit price could be greatly reduced.
  • planar coils on the Chip surface ⁇ can be realized with the help of conventional CMOS metallization. Since the metallization is normally used for the electrical wiring of the circuit elements on the chip, no active components can be accommodated in the coil areas.
  • Another disadvantage is the limited low resistance of the conductor tracks. With the usual specific material resistance, ohmic resistances of a few k ⁇ result on a 4 mm chip with 50 turns. This high resistance causes a poor quality of the input resonance circuit and leads to low-pass attenuation at high carrier frequencies when parasitic capacitances occur in the chip structure.
  • Kawahito et al., Sensors and Materials 5 (1994) 241-251 presents a method for producing a three-dimensional coil with a core on a silicon chip, which has the disadvantage of a planar structure, ie in particular the limited number of coil windings per surface element, eliminated.
  • the coil axis runs parallel to the surface of the chip.
  • the core is embedded by electrodeposition in a polyimide layer, which serves as insulation from the coil windings.
  • the coil windings are produced by means of splintering and subsequent structuring on the chip surface (lower coil area) or on the polyimide layer (upper and lateral coil areas).
  • the methods mentioned use only thick photoresist and intermediate electroplating layers for the formation of the three-dimensional structures.
  • the construction of more complicated structures is therefore only possible with increased effort.
  • the lacquers which can be used are not sufficiently physically, chemically and thermally stable.
  • the varnish becomes vacuum in the vacuum, for example, when an electroplating start layer splinters, or gas bubbles are generated by escaping solvent, so that no flat surfaces over larger areas (mm range) are available for subsequent layer build-ups.
  • the splintered galvanic start layer seals the underlying lacquer layers. With further outgassing, deformations and destruction of the electroplating starter layers above can occur. Different thermal expansion coefficients also support the formation of cracks in the overall structure. The reliable manufacture of complicated multi-layer structures is therefore not possible.
  • the method according to the invention also uses the molding with metallic auxiliary layers (sacrificial layers) to be removed later for the three-dimensional structures.
  • these metallic auxiliary layers lying in the lacquer layers are simultaneously used as electroplating start layers for further levels to be built up.
  • the method is suitable for all microelectronic or micromechanical components which have individual regions which can be produced by galvanic layer deposition, that is to say are electrically conductive.
  • the three-dimensional components or component groups are built up in layers on a surface, for example the surface of a chip.
  • the first area is first applied to the surface or to those already applied Layers or component areas are galvanically deposited. This requires an electroplating start layer that can be sputtered on beforehand. It is of course not necessary to apply the starting layer if an electrically conductive layer is already present as a base.
  • a structurable layer eg photoresist
  • the structure must expose a part of the electroplating start layer which is adjacent or below, depending on the component geometry, so that the desired shape of the first region can be produced in the structure by the subsequent electrodeposition.
  • the shape of the first region is determined by the shape of the structure and the thickness of the deposited layer. Adjacent to the first area already applied, a metallic sacrificial layer is now electrodeposited, which defines the space between the already applied (first) and the area or areas to be applied (second). For example, the distance between the two plates of a capacitor is determined by the thickness of the metallic sacrificial layer that is deposited on one of the plates.
  • the already applied electrically conductive (first) area serves as the electroplating start layer for the deposition of the metallic sacrificial layer.
  • the shape of the metallic sacrificial layer is also predetermined by the fact that the deposition takes place in a correspondingly structured layer (for example photoresist, see above).
  • the second region of the component is electrodeposited onto the metallic sacrificial layer, the shaping again being carried out by means of a structurable layer analogous to the deposition of the first region.
  • a structurable layer analogous to the deposition of the first region.
  • the metallic sacrificial layer so that no additional electroplating layer has to be applied.
  • a further metallic sacrificial layer can now be applied to the second layer in the same way and the method can be continued accordingly.
  • the repeated use of the method steps shown enables the production of complex component structures.
  • the structurable layers and the metallic sacrificial layers are selectively removed at the latest after completion of all areas of the component or the component group. After completion of the method, a component is thus available which has electrically conductive areas which are spaced apart from one another by precisely defined free spaces.
  • the method described here provides, for example, coils and transformers for integration on chip surfaces that were previously not possible in this form. With an increased range of variations in inductance, it enables completely new ways of carrying out information carriers.
  • An advantage of the method according to the invention is, in particular, that the metallic auxiliary layers, which have the double function of a sacrificial layer and an electroplating start layer, have a very high stability, so that smooth stable surfaces are provided, on which further levels can be built up without problems.
  • Electroplated layer surfaces can be greatly changed in their properties, such as roughness and reflectivity, by varying the deposition parameters (current strength, pulse duration, temperature). This can be used to achieve more uniform exposures of the photoresist with different varnish thicknesses (claim 12). Strongly structured surfaces, such as those which arise in the build-up electroplating process, have the consequence that varnish thickness fluctuations have to be dealt with in a plane to be exposed. The reduction in the reflection under thin layers of lacquer on rougher surfaces leads to a lower exposure effect, whereas highly reflective ones smooth surfaces favor the exposure of thick layers of paint. This enables large differences in lacquer thickness to be equalized.
  • the roughness of the electroplating surfaces can also be increased by chemical intermediate treatments, such as immersion baths in acids. In addition to the changed reflectivity of the surfaces, increased roughness also improves paint adhesion.
  • process steps can also be saved compared to the previously known methods, since no additional electroplating start layers are required for each further level.
  • the method makes it possible to generate minimal distances between different areas of the component or the component group with high accuracy.
  • the method can advantageously be carried out directly on finished chip surfaces that were previously provided with a chemically resistant insulation layer (chip-on technology), and thus enables the integration of electrical components such as e.g. Coils, transformers or capacitors without using bonding techniques.
  • electrical components such as e.g. Coils, transformers or capacitors without using bonding techniques.
  • contact holes are opened in the insulation layer of the chip and the component is electrically contacted via these contact holes with the components of the chip, for example via galvanically separated supply lines (claim 3).
  • 2 shows a side view of a three-dimensional coil with a core produced by the method according to the invention, integrated on a finished chip surface
  • 3 ar shows an example of the production according to the invention of a rectangular cylinder with a piston
  • 4 a-b show an example of the use of roughness differences on electroplating surfaces to adjust the exposure effect in the case of widely differing coating thicknesses.
  • a three-dimensional coil with a core is integrated on a chip surface.
  • Preliminary work that is necessary for such structures on chips is due to the stacked construction and the materials used. These preparations must be taken into account when designing the microsystem and can be carried out during CMOS production.
  • So z. B. a barrier layer between the CMOS structure and the overlying system structure, which prevent the diffusion of harmful metal ions (z. B. gold) in the underlying chip.
  • a sufficiently thick (a few 100 nm to 1 ⁇ m), chemically sealed electrical insulation layer (e.g. silicon nitride layer) between the chip structure and the metallic layers of the overlying components is necessary.
  • the three-dimensional coils or transformers according to the invention as can be used in the interfaces for contactless identification and communication systems, are produced according to the following method:
  • the passivating and insulating protective layer on the chips 1 is opened at the electrical contact points to the chip (not shown in FIG. 1).
  • An electroplating start layer 2 which is applied by sputtering and, depending on the structure of the chip, can consist of one layer of silicon nitride / gold, titanium / nickel or only of platinum, is deposited over the entire surface of the chip surface (FIG. 1a).
  • a layer of highly viscous, UV-structurable photoresist 3 is applied to the galva Matekt Anlagenicht 2 applied and dried (Fig. 1b).
  • the drying process must be carried out in such a way that the lacquer dries well, but no cracks occur when it cools down.
  • the first photoresist layer 3 is structured by exposure to a UV exposure device and subsequent development in an immersion process. or spraying method (Fig. 1c).
  • the supply lines (not shown in FIG. 1) to the open contact points and the lower coil level 5 are formed by electrodeposition in the lacquer structures 4.
  • the thickness of the lower lacquer layer 3 is determined by the desired thickness of the lower coil level determined (Fig. 1d).
  • the galvanized wafers are rinsed well and dried at room temperature.
  • a further approximately 10 ⁇ m thick photoresist layer 6 is then applied to the lower layer (FIG. 1e). It should be noted that the entire process is designed in such a way that unintentional UV exposure (daylight, microscope) is excluded. This is followed by exposure of a central region 7 along the axis of the coil to be produced over the entire coil length (FIG. 1f).
  • the lower coil windings 5 and between them the underlying electroplating start layer 2 are thus exposed in the exposed area.
  • a less noble sacrificial metal 8 is deposited into these lacquer structures 7 than that used for the coil structure (FIG. 1g). Copper is a suitable sacrificial material for gold coils.
  • the lacquer 3, 6 is completely removed and a new 40-60 ⁇ m thick photoresist layer 9 is applied (FIG. 1h).
  • a further lithography step 10 which is likewise along the coil axis, but longer and narrower than the sacrificial layer, exposes the anchors for the coil core and defines the structure of the coil core itself (FIG. 1i).
  • a NiFe alloy (permalloy) 11 of the desired thickness (for example 10-100 ⁇ m) is deposited in the now exposed areas (FIG. 1j). This layer is connected to the electroplating start layer 2 and thus to the chip 1 itself outside of the coil windings and is separated from the coil turns 5 below by the sacrificial layer 8 previously applied within the coil. After electroplating, cleaning and drying take place.
  • the same lacquer layer 9 is structured 12 in such a way that the side walls of the core 11 are exposed and the core is completely covered with a sacrificial layer 8, 13 by a new galvanic molding (FIGS. 1j and 1k).
  • a further lacquer layer 14 of appropriate thickness is applied in order to structure 15 of the still missing top and side areas of the coils (bridges) (FIG. 11).
  • the subsequent galvanic impression with 10 - 20 ⁇ m coil metal (gold, copper) forms the upper and the lateral coil areas 16 (FIG. 1 m).
  • the entire sacrificial layer 8, 13 is then removed using a suitable selective etchant which does not attack the chip structure, for example ammonia with a small addition of hydrogen peroxide in the case of copper as the sacrificial layer material and a gold coil with a Ni / Fe core (FIG. 10).
  • a suitable selective etchant which does not attack the chip structure, for example ammonia with a small addition of hydrogen peroxide in the case of copper as the sacrificial layer material and a gold coil with a Ni / Fe core (FIG. 10).
  • the metal portions of the electroplating start layer 2 in the entire wafer area must finally be removed (FIG. 1p). Since this must also take place between the windings, only a wet chemical etching step is again possible. For a silicon nitride / gold starting layer, this can be done by etching with suitable etching solutions (e.g. KJ / J) without having to accept appreciable thickness losses in the gold windings 5, 16 or in the NiFe core 11.
  • suitable etching solutions e.g. KJ / J
  • FIG. 2 A side view of a three-dimensional coil with core 17 integrated in this way on a chip surface with CMOS components 1 is shown in FIG. 2.
  • a rectangular cylinder with a piston is produced on a wafer surface using the following method steps:
  • a nickel layer 19 is applied to the surface of the wafer 18 as a galvanic start layer (FIG. 3a).
  • a suitable method e.g. B. in the centrifugal process, an approximately 50-60 ⁇ m high layer of UV-structurable photoresist 20 (e.g. highly viscous novolac) is applied to the electroplating start layer 19 and dried.
  • the first photoresist layer is structured according to the shape of the bulb (bulb width and bulb length) by exposure to a UV exposure unit and subsequent development in the immersion or spray process (Fig. 3b).
  • a metallic auxiliary layer 22 (here: copper) is first electroplated into the structure 21 thus formed up to a defined height (FIG. 3c; in plan view: FIG. 3d).
  • the height of the auxiliary layer 22 defines the distance between the piston and the wafer surface.
  • piston material 23 here: Fe / Ni alloy
  • the piston material 23 is galvanized to a thickness of approximately 40 ⁇ m over the auxiliary layer 22 in the same lacquer structure 21 (FIG. 3e).
  • the lacquer 20 is then completely removed.
  • a new, approximately 60 ⁇ m thick photoresist layer 24 is then applied.
  • This is followed by a further lithography step, which exposes an area 25 which is longer and wider than the piston 23 (cf. FIG. 3f; in plan view: FIG. 3g).
  • a further metallic auxiliary layer 26 is deposited on the piston 23 and in the exposed areas between the piston 23 and the photoresist 24 in a thickness which defines the distance between the piston 23 and the cylinder wall.
  • the piston is after this Complete step (approx. 5-10 ⁇ m thick) with sacrificial metal 22, 26 (metallic
  • the lacquer 24 is completely removed, after which a new approx.
  • the entire metallic sacrificial layer 22, 26 is then removed using a suitable selective etchant.
  • the result is shown in FIGS. 3p in cross section, 3q in side view and 3r in top view.
  • the lower cylinder wall forms the wafer 18 with the electroplating start layer 19.
  • the sacrificial metal 22, 26 defines the distance between the piston 23 and the cylinder walls 29, distances of a few micrometers can be achieved.
  • the piston for example, holes could be etched into the lower wall of the cylinder from the back of the wafer and the piston could then be moved with pressure. If the piston arrangement is designed such that two of the cylinders described are realized, the piston can be moved pneumatically and the mechanical force can be used in microsystems.
  • FIGS. 4a and 4b An example of the use of roughness differences on electroplating surfaces to adjust the exposure effect in the case of paints with widely differing paint thicknesses is shown schematically in FIGS. 4a and 4b.
  • 4a shows electroplating structures 30 with different structure heights, to which a photoresist layer 31 has been applied.
  • a smooth surface 32 of the low electroplating structure and a rough surface 33 (in FIG. highlighted) the high electroplating structure used in the exposure of the photoresist layer 31.
  • the reduction in the reflection on the rough surface 33 leads to a lower exposure effect of the thin lacquer layer above it, whereas the highly reflective smooth surfaces 32 promote the through-exposure of the thick lacquer layer above it.
  • the exposure dose is matched to the different coating thicknesses.
  • the different roughnesses can already be generated in the galvanic deposition by varying the deposition parameters (current strength, pulse duration, temperature) or after the deposition by chemical intermediate treatments, such as immersion baths in acids.
  • the exemplary embodiments presented naturally only show a small section of the large number of components that can be produced using the method according to the invention.
  • the method can be used for the production of many other microelectronic (e.g. capacitors) and / or micromechanical (e.g. cooling channels, waveguides, gear wheels on axles, etc.) components with spaced areas.
  • microelectronic e.g. capacitors
  • micromechanical e.g. cooling channels, waveguides, gear wheels on axles, etc.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fluid Mechanics (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Micromachines (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)

Abstract

L'invention concerne un procédé de production d'un composant tridimensionnel ou d'un groupe de composants, notamment à la surface de puces de semi-conducteurs déjà fabriquées. La production de superstructures tridimensionnelles connues réalisées à la surface de puces est fondée sur la structuration de laques photosensibles et sur la modification galvanique subséquente de la forme desdites structures de laques. Les procédés connus font uniquement appel à des laques photosensibles et à des couches d'amorçage de galvanisation intermédiaires épaisses pour la réalisation des superstructures tridimensionnelles. La production de structures compliquées implique une plus grande complexité technique en raison de la faible stabilité des laques photosensibles. Pour la réalistion de superstructures tridimensionnelles, outre la déformation galvanique de laques photosensibles structurées par ex. par U.V. et pourvues de couches métalliques (16), ce procédé intègre également la modification de la forme à l'aide de couches métalliques auxiliaires (couches sacrificielles) (13) qui seront enlevées ultérieurement. Dans les superstructures multicouches, ces couches métalliques auxiliaires situées dans les couches de laques servent simultanément de couches d'amorçage d'action galvanique pour d'autres plans à structurer. Ce procédé de réalisation de superstructures tridimensionnelles s'utilise par exemple pour produire des bobines et des transformateurs à intégrer à la surface de puces, ce que l'état de la technique ne permettait pas jusqu'à maintenant.
PCT/DE1995/001151 1994-09-14 1995-08-23 Procede de production d'un composant tridimensionnel ou d'un groupe de composants WO1996008749A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE4432725A DE4432725C1 (de) 1994-09-14 1994-09-14 Verfahren zur Herstellung eines dreidimensionalen Bauteils oder einer Bauteilgruppe
DEP4432725.0 1994-09-14

Publications (2)

Publication Number Publication Date
WO1996008749A2 true WO1996008749A2 (fr) 1996-03-21
WO1996008749A3 WO1996008749A3 (fr) 1996-07-25

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487355B1 (en) * 1999-11-15 2002-11-26 Axsun Technologies, Inc. Mounting and alignment structures for optical components providing optical axis direction deformation
US7041433B1 (en) * 1999-11-19 2006-05-09 Institut Fur Mikrotechnik Mainz Gmbh Flat coil and lithographic method for producing microcomponents
JP6302613B1 (ja) * 2017-03-01 2018-03-28 ナノコイル株式会社 ナノコイル型ｇｓｒセンサ素子の製造方法
US11117195B2 (en) 2018-07-19 2021-09-14 The University Of Liverpool System and process for in-process electron beam profile and location analyses
US11532760B2 (en) 2017-05-22 2022-12-20 Howmedica Osteonics Corp. Device for in-situ fabrication process monitoring and feedback control of an electron beam additive manufacturing process

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DE19523915A1 (de) * 1995-06-30 1997-01-02 Bosch Gmbh Robert Mikroventil und Verfahren zur Herstellung eines Mikroventils
EP1178499B1 (fr) * 1999-04-14 2004-11-24 Takashi Nishi Bobine de microsolenoide et procede de fabrication
US6763575B2 (en) * 2001-06-11 2004-07-20 Oak-Mitsui Inc. Printed circuit boards having integrated inductor cores
US6852454B2 (en) 2002-06-18 2005-02-08 Freescale Semiconductor, Inc. Multi-tiered lithographic template and method of formation and use
DE10302771B4 (de) * 2003-01-24 2006-07-27 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. System und Verfahren zur Herstellung von Mikrobauteilen
US6977223B2 (en) * 2003-03-07 2005-12-20 Massachusetts Institute Of Technology Three dimensional microfabrication
DE102006058068B4 (de) 2006-12-07 2018-04-05 Infineon Technologies Ag Halbleiterbauelement mit Halbleiterchip und passivem Spulen-Bauelement sowie Verfahren zu dessen Herstellung

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Publication number Priority date Publication date Assignee Title
US5190637A (en) * 1992-04-24 1993-03-02 Wisconsin Alumni Research Foundation Formation of microstructures by multiple level deep X-ray lithography with sacrificial metal layers
US5258097A (en) * 1992-11-12 1993-11-02 Ford Motor Company Dry-release method for sacrificial layer microstructure fabrication

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6487355B1 (en) * 1999-11-15 2002-11-26 Axsun Technologies, Inc. Mounting and alignment structures for optical components providing optical axis direction deformation
US7041433B1 (en) * 1999-11-19 2006-05-09 Institut Fur Mikrotechnik Mainz Gmbh Flat coil and lithographic method for producing microcomponents
JP6302613B1 (ja) * 2017-03-01 2018-03-28 ナノコイル株式会社 ナノコイル型ｇｓｒセンサ素子の製造方法
JP2018148189A (ja) * 2017-03-01 2018-09-20 ナノコイル株式会社 ナノコイル型ｇｓｒセンサ素子の製造方法
US11532760B2 (en) 2017-05-22 2022-12-20 Howmedica Osteonics Corp. Device for in-situ fabrication process monitoring and feedback control of an electron beam additive manufacturing process
US11117195B2 (en) 2018-07-19 2021-09-14 The University Of Liverpool System and process for in-process electron beam profile and location analyses

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DE4432725C1 (de) 1996-01-11
WO1996008749A3 (fr) 1996-07-25

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