WO1996008749A2 - Method of producing a three-dimensional component or group of components - Google Patents

Abstract

The invention concerns a method of producing a three-dimensional component or group of components, particularly on surfaces of already processed semiconductor chips. The production of three-dimensional features on chip surfaces is based on the stucturing of thick photosensitive resists and subsequent formation of the surface features by galvanic etching. Prior art methods merely use a thick photoresist and interposed galvanic starting layers to form three-dimensional features. The production of complex features is only possible with considerable difficulty owing to the low stability of the photoresist. The method proposed for the production of three-dimensional features uses, in addition to the galvanic etching of e.g. UV-structured photoresist layers with build-on metal films (16), etching using metal auxiliary films which are later removed again (sacrificial layers) (13). These metal auxiliary films lying in the resist layers are also used, in multi-layer features, as galvanic starting layers for additional build-on levels. The three-dimensional features which can be made by the method described enable, for example, e.g. coils and transformers to be manufactured, in a form in which they could not be manufactured previously, for integration on chip surfaces.

Description

 DESCRIPTION

METHOD FOR PRODUCING A THREE-DIMENSIONAL COMPONENT OR GROUP OF COMPONENTS

The invention relates to a method for producing a three-dimensional component or a component group, in particular on surfaces of already processed semiconductor chips.

To be able to manufacture micromechanical or microelectronic components such as three-dimensional micro-coils or transformers directly on surfaces of fully processed electronic components enables, in addition to further miniaturization of the overall structure, the production of previously unrealizable systems while at the same time reducing production costs.

The use of the latest technologies in the production of electronic data carriers and information systems leads to an accelerated expansion of this promising market. In order to be able to implement the technical progress in computer technology, rapid development in automatic communication interfaces is required. The radio frequency ID systems (RF-ID) used for this work on a radio frequency basis and are increasingly being transformed into complex information systems with bidirectional data exchange. The basic structures of known RF-ID systems consist of two hardware components, an information data carrier and one Base station and two physical interfaces between the components. The data exchange takes place via a magnetic or electromagnetic high-frequency field. Frequencies around 125 kHz and a few MHz are common. Systems that work in the information carrier without internal energy supply are particularly interested. These can be made much smaller and also have a longer service life. These systems also receive the necessary energy to function via the high-frequency field. The data transmission takes place via different modulation methods. Passive systems are characterized by an extended temperature range compared to active systems. The transmission energies required for their function are in the range of a few μW (up to 100 μW) for loosely coupled systems for longer ranges and more than 1 mW for systems with a fixed coupling.

The design of the communication interface is of particular interest for the future development of these RF-ID systems, i.e. the design of the transmitting and receiving antennas. In the case of a channel-separated structure, several coordinated circles per interface are necessary. The information carrier obtains the energy via transformer coupling, i.e. it has a coil as the receiving antenna. The voltage transmission grows with the transmission frequency and the maximum achievable resonant circuit quality. Since high power consumption lowers the quality, future systems must have low energy consumption and the highest possible carrier frequencies. Modern CMOS technology creates the conditions for this. The development is moving towards an increasingly greater miniaturization and ultimately towards a complete integration of the information carrier on a silicon chip, whereby all previously used assembly technologies are superfluous. However, in addition to the electronic components already present in the chip, there is also the need to integrate capacitors and coils. With integrated manufacturing, about 1000 RF-ID systems could be produced on a 6 inch Si wafer at the same time and the unit price could be greatly reduced.

In known systems, the complete monolithic integration of the information carrier is achieved in that planar coils on the Chip surfaceπ can be realized with the help of conventional CMOS metallization. Since the metallization is normally used for the electrical wiring of the circuit elements on the chip, no active components can be accommodated in the coil areas. Another disadvantage is the limited low resistance of the conductor tracks. With the usual specific material resistance, ohmic resistances of a few kΩ result on a 4 mm chip with 50 turns. This high resistance causes a poor quality of the input resonance circuit and leads to low-pass attenuation at high carrier frequencies when parasitic capacitances occur in the chip structure.

A process developed from the assembly and connection technology, which provides a remedy here, realizes the coil construction with other metals, especially gold and copper. However, the coils are always made in a planar design and without inductance-improving coil cores (R. Jurisch, Elektronik 9 (1993) 86-92).

The basis for well-known three-dimensional structures on chip surfaces is the structuring of thick photoresists and the subsequent galvanic molding of these lacquer structures. Simple structures that were produced with this basic method are e.g. in B. Löchel et al., Microelectr. Engineering ring 21 (1993) 463-466. In G. Engelmann et al., Proc. MEMS 92, Travemύnde, (1992) 93-98, this method is used for the production of planar coils.

From CH Ahn et al., J. Micromech. Microeng. 3 (1993) 37-44, it is known to produce a planar three-dimensional coil with a core, the coil windings being arranged in two superimposed planes and enclosed by the core material. The coil core advantageously increases the inductance of the coil. The different levels of the coil structure are produced by repeated application and structuring of thick photoresists and subsequent galvanic molding of these resist structures, with an electroplating start layer having to be split up before the galvanic deposition of each level. S. Kawahito et al., Sensors and Materials 5 (1994) 241-251, presents a method for producing a three-dimensional coil with a core on a silicon chip, which has the disadvantage of a planar structure, ie in particular the limited number of coil windings per surface element, eliminated. The coil axis runs parallel to the surface of the chip. In the process, the core is embedded by electrodeposition in a polyimide layer, which serves as insulation from the coil windings. The coil windings are produced by means of splintering and subsequent structuring on the chip surface (lower coil area) or on the polyimide layer (upper and lateral coil areas).

The splitting of the coil windings, however, only results in small structural heights of the windings of 1-2 μm, so that the qualities and usable current strengths that can be achieved with them are correspondingly low and thus limit the range of use.

In B. Löchel et al., Microelectr. Engineering 23 (1994) 455-459 describes a process for producing a three-dimensional coil on chip surfaces, the basis of which also forms the structuring of thick photoresists (10-60 μm structure height) and the subsequent galvanic molding of these lacquer structures. The different levels of the coil structure are produced here by repeated application and structuring of the photoresists and galvanic molding, with an electroplating start layer having to be sputtered on before the deposition of each level if this cannot be replaced by a lower electroplating layer.

Examples of an application of this method for producing other micromechanical components are described in B. Löchel et al., Proc. ACTUATOR 94, Bremen, (1994) 109-113, or in G. Engelmann et al., SPIE 2045 (1994) 306-313.

However, the methods mentioned use only thick photoresist and intermediate electroplating layers for the formation of the three-dimensional structures. The construction of more complicated structures is therefore only possible with increased effort. This is due in particular to the fact that the lacquers which can be used are not sufficiently physically, chemically and thermally stable. For example, the varnish becomes vacuum in the vacuum, for example, when an electroplating start layer splinters, or gas bubbles are generated by escaping solvent, so that no flat surfaces over larger areas (mm range) are available for subsequent layer build-ups. The splintered galvanic start layer seals the underlying lacquer layers. With further outgassing, deformations and destruction of the electroplating starter layers above can occur. Different thermal expansion coefficients also support the formation of cracks in the overall structure. The reliable manufacture of complicated multi-layer structures is therefore not possible.

The problem is exacerbated in particular by the need to apply new electroplating starter layers for each component level to the underlying lacquer layers, which also leads to an increase in the number of process steps.

It is therefore an object of the present invention to provide a method for producing a three-dimensional component or a component group, with which complicated structures can be built up in a simple and reliable manner and integrated on chip surfaces.

The object is achieved with the features of the method according to claim 1. Particular embodiments of the method are the subject of the subclaims.

In addition to the galvanic molding of, for example, UV-structured photoresist layers with metal layers that build up, the method according to the invention also uses the molding with metallic auxiliary layers (sacrificial layers) to be removed later for the three-dimensional structures. In the case of multilayer structures, these metallic auxiliary layers lying in the lacquer layers are simultaneously used as electroplating start layers for further levels to be built up. The method is suitable for all microelectronic or micromechanical components which have individual regions which can be produced by galvanic layer deposition, that is to say are electrically conductive. In the method according to the invention, the three-dimensional components or component groups are built up in layers on a surface, for example the surface of a chip. To produce electrically conductive areas between which there should be a defined free space (i.e. without solid matter) in the finished component, for example between two plates of a condenser or between two opposite walls of a cooling channel, the first area is first applied to the surface or to those already applied Layers or component areas are galvanically deposited. This requires an electroplating start layer that can be sputtered on beforehand. It is of course not necessary to apply the starting layer if an electrically conductive layer is already present as a base. A structurable layer (eg photoresist) is then applied to this electroplating start layer and structured in accordance with the shape of the first region. The structure must expose a part of the electroplating start layer which is adjacent or below, depending on the component geometry, so that the desired shape of the first region can be produced in the structure by the subsequent electrodeposition. The shape of the first region is determined by the shape of the structure and the thickness of the deposited layer. Adjacent to the first area already applied, a metallic sacrificial layer is now electrodeposited, which defines the space between the already applied (first) and the area or areas to be applied (second). For example, the distance between the two plates of a capacitor is determined by the thickness of the metallic sacrificial layer that is deposited on one of the plates. The already applied electrically conductive (first) area serves as the electroplating start layer for the deposition of the metallic sacrificial layer. The shape of the metallic sacrificial layer is also predetermined by the fact that the deposition takes place in a correspondingly structured layer (for example photoresist, see above). Finally, the second region of the component is electrodeposited onto the metallic sacrificial layer, the shaping again being carried out by means of a structurable layer analogous to the deposition of the first region. Serves as galvanic starting layer here, however, the metallic sacrificial layer, so that no additional electroplating layer has to be applied. For the production of further areas, this time spaced from the second electrically conductive area, a further metallic sacrificial layer can now be applied to the second layer in the same way and the method can be continued accordingly. The repeated use of the method steps shown enables the production of complex component structures.

The structurable layers and the metallic sacrificial layers are selectively removed at the latest after completion of all areas of the component or the component group. After completion of the method, a component is thus available which has electrically conductive areas which are spaced apart from one another by precisely defined free spaces.

With the three-dimensional structures, the method described here provides, for example, coils and transformers for integration on chip surfaces that were previously not possible in this form. With an increased range of variations in inductance, it enables completely new ways of carrying out information carriers.

An advantage of the method according to the invention is, in particular, that the metallic auxiliary layers, which have the double function of a sacrificial layer and an electroplating start layer, have a very high stability, so that smooth stable surfaces are provided, on which further levels can be built up without problems.

Electroplated layer surfaces (such as the surfaces of the metallic sacrificial layers) can be greatly changed in their properties, such as roughness and reflectivity, by varying the deposition parameters (current strength, pulse duration, temperature). This can be used to achieve more uniform exposures of the photoresist with different varnish thicknesses (claim 12). Strongly structured surfaces, such as those which arise in the build-up electroplating process, have the consequence that varnish thickness fluctuations have to be dealt with in a plane to be exposed. The reduction in the reflection under thin layers of lacquer on rougher surfaces leads to a lower exposure effect, whereas highly reflective ones smooth surfaces favor the exposure of thick layers of paint. This enables large differences in lacquer thickness to be equalized. The roughness of the electroplating surfaces can also be increased by chemical intermediate treatments, such as immersion baths in acids. In addition to the changed reflectivity of the surfaces, increased roughness also improves paint adhesion.

With the method, process steps can also be saved compared to the previously known methods, since no additional electroplating start layers are required for each further level.

Furthermore, the method makes it possible to generate minimal distances between different areas of the component or the component group with high accuracy.

The method can advantageously be carried out directly on finished chip surfaces that were previously provided with a chemically resistant insulation layer (chip-on technology), and thus enables the integration of electrical components such as e.g. Coils, transformers or capacitors without using bonding techniques.

For this purpose, contact holes are opened in the insulation layer of the chip and the component is electrically contacted via these contact holes with the components of the chip, for example via galvanically separated supply lines (claim 3).

The method according to the invention is explained in more detail below on the basis of the exemplary embodiments and the drawings.

Show:

1 a-p an example of the production of a three-dimensional coil with a core using the method according to the invention,

2 shows a side view of a three-dimensional coil with a core produced by the method according to the invention, integrated on a finished chip surface, 3 ar shows an example of the production according to the invention of a rectangular cylinder with a piston, and

4 a-b show an example of the use of roughness differences on electroplating surfaces to adjust the exposure effect in the case of widely differing coating thicknesses.

In a first exemplary embodiment, a three-dimensional coil with a core is integrated on a chip surface. Preliminary work that is necessary for such structures on chips is due to the stacked construction and the materials used. These preparations must be taken into account when designing the microsystem and can be carried out during CMOS production. So z. B. a barrier layer between the CMOS structure and the overlying system structure, which prevent the diffusion of harmful metal ions (z. B. gold) in the underlying chip. In addition, a sufficiently thick (a few 100 nm to 1 μm), chemically sealed electrical insulation layer (e.g. silicon nitride layer) between the chip structure and the metallic layers of the overlying components is necessary.

The three-dimensional coils or transformers according to the invention, as can be used in the interfaces for contactless identification and communication systems, are produced according to the following method:

The passivating and insulating protective layer on the chips 1 is opened at the electrical contact points to the chip (not shown in FIG. 1).

An electroplating start layer 2, which is applied by sputtering and, depending on the structure of the chip, can consist of one layer of silicon nitride / gold, titanium / nickel or only of platinum, is deposited over the entire surface of the chip surface (FIG. 1a).

With a suitable method, e.g. B. in the centrifugal process, a layer of highly viscous, UV-structurable photoresist 3 is applied to the galva Niciktschichticht 2 applied and dried (Fig. 1b). Depending on the photoresist used, the drying process must be carried out in such a way that the lacquer dries well, but no cracks occur when it cools down. After a possibly necessary paint aftertreatment (for novolak systems, light-protected storage at room temperature and normal clean room climate for several hours to days), the first photoresist layer 3 is structured by exposure to a UV exposure device and subsequent development in an immersion process. or spraying method (Fig. 1c).

After drying at room temperature, the supply lines (not shown in FIG. 1) to the open contact points and the lower coil level 5 are formed by electrodeposition in the lacquer structures 4. The thickness of the lower lacquer layer 3 is determined by the desired thickness of the lower coil level determined (Fig. 1d). The galvanized wafers are rinsed well and dried at room temperature. A further approximately 10 μm thick photoresist layer 6 is then applied to the lower layer (FIG. 1e). It should be noted that the entire process is designed in such a way that unintentional UV exposure (daylight, microscope) is excluded. This is followed by exposure of a central region 7 along the axis of the coil to be produced over the entire coil length (FIG. 1f). The lower coil windings 5 and between them the underlying electroplating start layer 2 are thus exposed in the exposed area. A less noble sacrificial metal 8 is deposited into these lacquer structures 7 than that used for the coil structure (FIG. 1g). Copper is a suitable sacrificial material for gold coils. B. Zinc. An additional electroplating layer is not necessary at this point. After the first sacrificial metal deposition, the lacquer 3, 6 is completely removed and a new 40-60 μm thick photoresist layer 9 is applied (FIG. 1h). This is followed by a further lithography step 10, which is likewise along the coil axis, but longer and narrower than the sacrificial layer, exposes the anchors for the coil core and defines the structure of the coil core itself (FIG. 1i). In the subsequent electroplating step, a NiFe alloy (permalloy) 11 of the desired thickness (for example 10-100 μm) is deposited in the now exposed areas (FIG. 1j). This layer is connected to the electroplating start layer 2 and thus to the chip 1 itself outside of the coil windings and is separated from the coil turns 5 below by the sacrificial layer 8 previously applied within the coil. After electroplating, cleaning and drying take place. In the next step, the same lacquer layer 9 is structured 12 in such a way that the side walls of the core 11 are exposed and the core is completely covered with a sacrificial layer 8, 13 by a new galvanic molding (FIGS. 1j and 1k).

After complete stripping, a further lacquer layer 14 of appropriate thickness is applied in order to structure 15 of the still missing top and side areas of the coils (bridges) (FIG. 11). The subsequent galvanic impression with 10 - 20 μm coil metal (gold, copper) forms the upper and the lateral coil areas 16 (FIG. 1 m).

In the next step, the entire paint structure 9 is removed with solvents (acetone) (FIG. 1n).

The entire sacrificial layer 8, 13 is then removed using a suitable selective etchant which does not attack the chip structure, for example ammonia with a small addition of hydrogen peroxide in the case of copper as the sacrificial layer material and a gold coil with a Ni / Fe core (FIG. 10).

In order to be able to operate the coil functionally, the metal portions of the electroplating start layer 2 in the entire wafer area must finally be removed (FIG. 1p). Since this must also take place between the windings, only a wet chemical etching step is again possible. For a silicon nitride / gold starting layer, this can be done by etching with suitable etching solutions (e.g. KJ / J) without having to accept appreciable thickness losses in the gold windings 5, 16 or in the NiFe core 11.

After a final cleaning, the coil 17 on the surface is functionally contacted to the chip 1 and ready for use. A side view of a three-dimensional coil with core 17 integrated in this way on a chip surface with CMOS components 1 is shown in FIG. 2.

In a second exemplary embodiment, a rectangular cylinder with a piston is produced on a wafer surface using the following method steps:

A nickel layer 19 is applied to the surface of the wafer 18 as a galvanic start layer (FIG. 3a). With a suitable method, e.g. B. in the centrifugal process, an approximately 50-60 μm high layer of UV-structurable photoresist 20 (e.g. highly viscous novolac) is applied to the electroplating start layer 19 and dried. After a possibly necessary paint aftertreatment (for novolak systems, light-protected storage at room temperature and normal clean room climate for several hours to days), the first photoresist layer is structured according to the shape of the bulb (bulb width and bulb length) by exposure to a UV exposure unit and subsequent development in the immersion or spray process (Fig. 3b). A metallic auxiliary layer 22 (here: copper) is first electroplated into the structure 21 thus formed up to a defined height (FIG. 3c; in plan view: FIG. 3d). The height of the auxiliary layer 22 defines the distance between the piston and the wafer surface.

Then the piston material 23 (here: Fe / Ni alloy) is galvanized to a thickness of approximately 40 μm over the auxiliary layer 22 in the same lacquer structure 21 (FIG. 3e).

The lacquer 20 is then completely removed. A new, approximately 60 μm thick photoresist layer 24 is then applied. This is followed by a further lithography step, which exposes an area 25 which is longer and wider than the piston 23 (cf. FIG. 3f; in plan view: FIG. 3g). In the subsequent electroplating step, a further metallic auxiliary layer 26 is deposited on the piston 23 and in the exposed areas between the piston 23 and the photoresist 24 in a thickness which defines the distance between the piston 23 and the cylinder wall. The piston is after this Complete step (approx. 5-10 μm thick) with sacrificial metal 22, 26 (metallic

Auxiliary layer) sheathed (Fig. 3h; in plan view: Fig. 3i).

The lacquer 24 is completely removed, after which a new approx.

60 μm thick photoresist layer 27 is applied. This is followed by a further lithography step, which exposes an area 28 which is wider than the previous structure 25, but shorter than the piston 23, so that it is covered on one side by the lacquer 27 (cf. FIG. 3j; in

Top view Fig. 3k).

In the subsequent electroplating step, a NiFe alloy (permalloy) in the desired thickness of the cylinder walls is placed in the now exposed areas 28

29 deposited (Fig. 31; in plan view Fig. 3m).

In the next step, the entire paint structure 27 with solvents

(Acetone) removed (Fig. 3n; in plan view Fig. 3o)).

The entire metallic sacrificial layer 22, 26 is then removed using a suitable selective etchant. The result is shown in FIGS. 3p in cross section, 3q in side view and 3r in top view. The lower cylinder wall forms the wafer 18 with the electroplating start layer 19.

Since the sacrificial metal 22, 26 defines the distance between the piston 23 and the cylinder walls 29, distances of a few micrometers can be achieved. For the movement of the piston, for example, holes could be etched into the lower wall of the cylinder from the back of the wafer and the piston could then be moved with pressure. If the piston arrangement is designed such that two of the cylinders described are realized, the piston can be moved pneumatically and the mechanical force can be used in microsystems.

An example of the use of roughness differences on electroplating surfaces to adjust the exposure effect in the case of paints with widely differing paint thicknesses is shown schematically in FIGS. 4a and 4b. 4a shows electroplating structures 30 with different structure heights, to which a photoresist layer 31 has been applied. To produce a lacquer structure, as is shown in FIG. 4b, a smooth surface 32 of the low electroplating structure and a rough surface 33 (in FIG. highlighted) the high electroplating structure used in the exposure of the photoresist layer 31. The reduction in the reflection on the rough surface 33 leads to a lower exposure effect of the thin lacquer layer above it, whereas the highly reflective smooth surfaces 32 promote the through-exposure of the thick lacquer layer above it. As a result, the exposure dose is matched to the different coating thicknesses. The different roughnesses can already be generated in the galvanic deposition by varying the deposition parameters (current strength, pulse duration, temperature) or after the deposition by chemical intermediate treatments, such as immersion baths in acids.

The exemplary embodiments presented naturally only show a small section of the large number of components that can be produced using the method according to the invention. The method can be used for the production of many other microelectronic (e.g. capacitors) and / or micromechanical (e.g. cooling channels, waveguides, gear wheels on axles, etc.) components with spaced areas.

It also enables multi-level wiring to be implemented in one level, with crossings of conductor tracks being prevented by air bridges isolating the wiring levels from one another at these locations. If necessary, the entire microsystem resulting from the components can be encapsulated by embedding in plastic after completion and thus mechanically and electrically stabilized and environmental influences largely removed.

Claims

PATENT CLAIMS 1. A method for producing a three-dimensional component or a component group, in which electrically conductive areas (5, 11, 16) of the component (17) or the component group are applied to a surface (1) by galvanic layer deposition, with structurable layers (3 , 6, 9, 14) are deposited and structured, the structures (4, 10, 15) of which at least partially determine the shapes of regions of the component or the component group, the galvanic deposition takes place in these structures, and the structurable layers at the latest after completion of all Areas of the component or group of components are selectively removed, characterized in that prior to the galvanic deposition of electrically conductive areas (11, 16) of the component or group of components to be applied, those of an already applied electrically conductive area (5, 11) by a free Are spaced apart, a metallic sacrifice hicht (8, 13) is electrodeposited adjacent to the area already applied, which defines the space between the areas already applied and the areas to be applied and serves as a galvanic starting layer for the deposition of the areas to be applied, the metallic sacrificial layer at the latest after completion of all Areas of the component or group of components are selectively removed. 2. The method according to claim 1, characterized in that a base metal is used for the metallic sacrificial layer (8, 13) than for the electrically conductive regions (5, 16) of the component. 3. The method according to any one of claims 1 or 2, characterized in that that the surface (1) is the passivated surface of a chip which already contains finished processed components, contact holes being opened for the components of the chip and the component being electrically contacted via these contact holes with the components of the chip by conductor tracks applied to the chip . Method according to one of the claims 3, characterized in that for the production of a three-dimensional coil (17), the electrically conductive areas include a lower coil area (5), lateral coil areas (16), an upper coil area (16) and a core (11), the following process steps are carried out: - Applying an electroplating start layer (2) to the surface (1); - Applying a first structurable layer (3) to the electroplating layer; - Structuring the first structurable layer in accordance with the shape of the lower coil region such that an interface of the structure is formed by the electroplating start layer (2); - Galvanic deposition of the lower coil region (5) into the structure of the first structurable layer (3); - Applying a second structurable layer (6) to the lower coil area; Structuring of the second structurable layer in a central region along the coil axis such that the structure defines the interspace between the lower coil region and the core, and an interface of the structure at least partially through the adjacent lower coil region (5) is bidding; - Galvanic deposition of the metallic sacrificial layer (8) into the structure of the second structurable layer (6); - Application of a third structurable layer (9) adjacent to the metallic sacrificial layer (8); - Structuring the third structurable layer in such a way that the structure at least partially defines the shape of the core, and a Interface of the structure is formed by the adjacent metallic sacrificial layer (8); - Galvanic deposition of the core (11) in the structure of the third structurable layer (9); Further structuring of the third structurable layer (9) such that the structure defines the space between the core and the lateral coil regions and between the core and the upper coil region, and an interface of the structure is formed by the adjacent core; - Galvanic deposition of the metallic sacrificial layer (13) into the structure, so that the core (11) is completely covered by metallic sacrificial layers (8, 13) perpendicular to the coil axis; - Applying a fourth structurable layer (14) adjacent to the metallic sacrificial layer (13); - Structuring the fourth and underlying structurable layers in such a way that the structure at least partially defines the shape of the lateral coil areas and the upper coil area (16), and an interface of the structure is formed by the adjacent metallic sacrificial layer (13); - Galvanic deposition of the lateral and the upper coil area (16) into the structure of the fourth and underlying structurable layers; - Selective removal of the structurable layers (3, 6, 9, 14); - Selective removal of the metallic sacrificial layers (8, 13); - Selective removal of the electroplating start layer (2) at the exposed locations. Method according to Claim 4, characterized in that after the application of the metallic sacrificial layer (8) which is arranged between the lower coil region (5) and the core (11), the first (3) and the second structurable layer (6) are removed. 6. The method according to any one of claims 4 or 5, characterized in that as materials for the upper (16), lower (5) and the lateral coil regions (16) gold or copper, for the core (11) a Ni / Fe Alloy and copper or zinc can be used for the metallic sacrificial layer (8, 13). 7. The method according to any one of claims 4 to 6, characterized in that one layer of silicon nitride / gold or titanium / nickel or platinum is applied for the electroplating start layer (2). 8. The method according to any one of claims 4 to 7, characterized in that the thickness of the individual structurable layers (3, 6, 9, 14) is selected between 10 and 100 microns. 9. The method according to claim 1 or 2, characterized in that the following method steps are carried out to produce a rectangular cylinder with piston, which has the cylinder walls (29) and the piston (23) as electrically conductive regions: - Applying an electroplating layer (19) to the surface (18); - Applying a structurable layer (20) to the electroplating start layer (19); Structuring of the structurable layer according to the shape of the piston in such a way that an interface of the structure is formed by the galvanic starting layer; - Galvanic deposition of a metallic sacrificial layer (22) in the structure of the structurable layer (20), so that the sacrificial layer defines the distance between the piston (23) and the surface (18); - Galvanic deposition of the piston (23) on the metallic sacrificial layer (22) in the structure of the structurable layer (20); - Structuring the structurable layer (20) such that the structure of the piston and a region of the electroplating start layer (19) around the piston are exposed; - Galvanic deposition of the metallic sacrificial layer (26) into the structure, so that the piston is completely encased by metallic sacrificial layers (22, 26) which define the distance to the cylinder walls (29); - Removing the structurable layer (20, 24); - applying a further structurable layer (27) to the electroplating start layer and the sacrificial layer; Structuring of the further structurable layer (27) such that a part of the sacrificial layer around the piston and a region of the electroplating start layer around the piston are exposed by the structure; - Galvanic deposition of the cylinder walls (29) into the structure of the further structurable layer (27); - Removing the further structurable layer (27); - Selective removal of the metallic sacrificial layers (22, 26); - Selective removal of the electroplating start layer (19) at the exposed locations. 10. The method according to claim 9, characterized in that after the deposition of the piston (23), the structurable layer (20) is removed and a new structurable layer (24) is applied. 11. The method according to any one of claims 1 to 10, characterized in that UV-patternable photoresist layers are used as structurable layers and these are patterned by means of UV radiation and subsequent development in the immersion or spraying process. 12. The method according to claim 11, characterized in that that by suitable selection of the deposition parameters in the electroplating or by post-treatment, roughness differences are generated on the electroplated layers, which enable the exposure dose of overlying lacquer layers to be adjusted at different lacquer thicknesses. 13. The method according to claim 11 or 12, characterized in that the photoresist is removed with a solvent. 14. The method according to any one of claims 1 to 13, characterized in that the metallic sacrificial layer is removed with a selective etchant which does not attack the chip structure. 15. Application of the method according to one of claims 1 to 14 for the manufacture of capacitors, coils, transformers on contactless identification and communication systems or in portable telecommunication systems. 16. Application of the method according to one of claims 1 to 14 for the manufacture of micromechanical components on surfaces.