WO1996015509A1

WO1996015509A1 - Digitally storing identifying information on tape cartridges

Info

Publication number: WO1996015509A1
Application number: PCT/US1995/015863
Authority: WO
Inventors: Calvin B. Brown; Marold H. Lohrenz
Original assignee: Usiq Corporation
Priority date: 1994-11-14
Filing date: 1995-11-14
Publication date: 1996-05-23
Also published as: AU4613096A

Abstract

A system is disclosed for tracking back-up tape cartridges and for providing an index reflecting data stored on the tape cartridge. The system includes a memory chip (40) mounted on each cartridge (25) by an applique (100). The applique (100) includes a pair of conductive strips contacting the leads of the chip and a film carrier supporting the strips. A laminating film covers the chip with an aperture exposing a portion of the strips. The cartridges (25) are stored in a specially designed rack (50), which includes a plurality of slots (15) for receiving the cartridges and circuitry for completing a connection to the memory chip through the conductive strips.

Description

DIGITALLY STORING IDENTIFYING INFORMATION ON TAPE CARTRIDGES

The present case is a continuation-in-part of copending application U.S. Serial No. 08 296,107, filed on August 25, 1994, which is incorporated herein by reference as if set forth in its entirety. BACKGROUND OF THE INVENTION The present invention relates generally to the identification of high density back-up tape cartridges or other items, using digital identifying information. More specifically, the present invention relates to a system for automatically tracking back-up tape cartridges and for indexing the data contained on the tape cartridges to enable a user to easily locate and ascertain the content of the tape cartridges while the cartridge remains in its storage location. Still more specifically, the present invention relates to a tape cartridge having embedded therein a memory chip with external contacts, and to a system for storing the tape cartridge in a manner that allows access to information on the chip via the external contacts. Back-up tape cartridges are used extensively by businesses and individuals to store data that is downloaded from computing and accounting systems. Typically, computer users will back-up onto the tape data from computers on a relatively frequent basis to protect the integrity of that data in case the computer or operating system loses its date, or "crashes''. Back-up tapes also are used to free up space in the computer or network memory. Data is written or backed-up onto a tape cartridge by a writing device or driver that typically connects as a peripheral device to a computer system. Similarly, data is retrieved or restored from the back-up tape cartridge through the use of a read device. Typically, a single tape driver unit is provided to both back-up and restore data from a back-up tape cartridge. Methods and techniques for backing up data onto cartridges vary. Usually, however, a user will maintain multiple back-up copies of data to it sure the integrity of the stored data. For example, three different tape cartridges may be used in a rotating fashion to back-up all accounting data. Thus, for example, on Monday, tape 1 would be used to back-up the accounting data, while tapes 2 and 3 would be used on Tuesday and Wednesday, respectively. On Thursday, the user would again use tape 1 to back-up the data, and tape 2 would be used on Friday. In this fashion, each of the three tapes is completely supplemented once every three days. As a result, if one tape fails or is lost on the same day that a computer crashes, at most only one day of data would be lost. An entire industry has evolved that relates to equipment and methods for backing-up data from a computer onto a tape cartridge, and for keeping an inventory of the many back-up tapes that may exist. For example, robotic library systems have been developed which include a robotic arm to automatically place tape cartridges into tape drivers for backing up and restoring data. In these systems, the tape cartridge typically is identified by a bar code, which is read by a bar code scanner. A central computer connects to the bar code scanner and keeps track of the position of each cartridge. The cartridges are maintained in a circular library that rotates cartridges past the robotic arm and bar code scanner. These library systems, however, are very expensive, and require expensive robotic handling equipment to handle the tapes. In addition, the bar code is not capable of retaining information regarding the contents of the tape, and as such only identifies the tape cartridge without any detail regarding the contents or usage history of the cartridge. As a result, a separate table must be generated to identify the contents of the tape, or the tape must be retrieved from its storage location for further examination. In addition, there typically is no mechanism for determining if the automatic system has misfiled or misplaced a tape cartridge. The only method of determining the identity of the cartridges, is to move each cartridge past the bar code scanner. Other similar systems have been developed which use a hand-held bar code scanner for identifying tape cartridges kept on shelves or in horizontal libraries. In these systems, typically a bar code is provided in each storage slot that receives a cartridge, and on the cartridge itself. A central computer connects to the bar code scanner for associating the slot with the associated cartridge. These systems do not solve the problem of quickly identifying misfiled cartridges, or of identifying the contents of cartridges. In other applications where the user is unable to afford the bar code scanning equipment, the tape cartridges may only be identified by a handwritten notation on a label attached to the cartridge. Typically, the cartridges are stored in drawers or on shelves in no particular order, making it difficult to keep track of the location of cartridges. It would be advantageous if a relatively inexpensive system could be developed which could identify the location of a tape cartridge automatically, together with the contents of the tape cartridge, while the cartridge is maintained in its storage location. It would also be advantageous if a storage rack could be developed which includes circuitry to determine the identity and contents of each of the tape cartridges stored therein, and provide a visual indication of the cartridge, without die necessity of removing the cartridges. It would further be advantageous to develop a system which tracks the movement of tape cartridges and which automatically notes if a tape is misfiled. Copending application, Serial No. 08/296,107, discloses a tape cartridge having affixed thereto a chip including a pair of conducting strips and further discloses a system and apparatus for storing a cartridge in a rack that provides electrical contact with the strips. This allows a remote CPU to query each cartridge and obtain from the chip information relating to access and usage of the cartridge. Similarly, information relating to each cartridge can be modified by writing on the chip. The chip is carried on an applique that is adapted to be applied to the cartridge at any time subsequent to the manufacture of the cartridge. It has been determined that it would be advantageous if the chip were integrated into the tape cartridge itself. An integral chip eliminates the need to attach a chip to each new cartridge and ensures uniformity among cartridges. The integral chip also protects the chip and reduces the possibility that the chip could become dislodged from the cartridge. Similarly, it is desirable to provide means for accessing chip at the same time that information on the cartridge is changed. SUMMARY OF THE INVENTION The present invention solves the shortcomings and deficiencies of the prior art by providing a memory chip on each of the tape cartridges and storing die cartridges in a specially constructed rack design. The rack design includes circuitry to provide an electrical connection to the memory chip on each of the cartridges. Each of the memory chips may be specifically addressed by an addressable switch, which permits each of the chips to be independently read or written to for purposes of identifying the cartridge and its contents. Alternatively, all of the chips can be polled in a command mode to determine the presence or absence of any memory chip, and thus the presence or absence of the associated cartridge. In a similar fashion, the precise location of the tape cartridge may be determined. A host microcontroller or CPU connects to the rack design through an interface and functions as a master device to control all data transactions to the memory chips. In the preferred embodiment, a single data line is provided in each rack which connects to each of die memory chips at a data input terminal. A second return or ground line is provided to complete the connection between the memory chips and die CPU. The CPU can read information from the chip, including a unique ID number to identify the associated cartridge. In addition, the chip may include additional data reflecting the contents of the cartridge, which also can be read by the microcontroller. The CPU also can perform write operations to the memory chip to record or modify die data reflecting the contents and recent usage of the tape cartridge. In addition, die CPU can be used to store die ID numbers and die data reflecting contents of all of the memory chips, thereby permitting additional processing of this data. A plurality of racks may be provided, each of which connects to the host CPU. The connection to the CPU may either be through a hard-wire electrical connection (such as a two wire RS232 connector), or through a remote link, such as by an radio frequency link. In this embodiment, each of the plurality of racks includes an addressable switch to permit the racks to be addressed independently. The rack includes two springs at each slot location for providing the two wire electrical contact to the memory chip. In addition, an LED preferably is associated with each slot to provide a visual indication to an operator regarding a particular operation with respect to a particular cartridge. The LED preferably is independenύy addressable by an addressable switch. The touch memory chip may be mounted on the tape cartridge using a special applique. The applique preferably comprises a pair of conductive strips attached to the memory chip through a conductive adhesive. The conductive strips are mounted on a relatively rigid film carrier, which attaches to the cartridge by a pressure sensitive adhesive. The entire package, including die chip, is encapsulated with a laminating film. The laminating film includes apertures for exposing the underlying conductive strips to permit an electrical contact between the conductive strips and associated springs in the rack. The present invention avoids die problems associated with providing the chip in a separate label or applique that must be applied to the tape by providing a cartridge that includes an integral or inwardly positioned chip. The chip can be mounted in die cartridge either during or after manufacturing. According to d e present invention, the chip lies flush with an outer face of the cartridge and is less likely to be dislodged. The present invention further comprises improved electrical contacts that are easily manufactured and ensure access to die information on the chip. According to the present invention, a touch memory chip can be affixed to a tape using a flush-mount applique. The applique preferably comprises a chip affixed to one side of a substantially rigid film carrier. A pair of conducting pads are affixed to the other side of die film carrier. Each pad is connected to the chip by a conducting trace extending through the film carrier. A two-sided pressure sensitive adhesive is affixed to the underside of die film carrier and die upper surface of the carrier, with the exception of the pads, is encapsulated in a laminating film. In an alternative embodiment, the chip is embedded in the wall of the tape cartridge housing such that the conducting pads can be electrically connected to the chip terminals. In a second alternative embodiment, die chip, the conducting panels and die leads extending between the chip and die panels are all embedded in die cartridge housing such that the conducting pads are exposed for electrical contact. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of die invention will become apparent upon reading die following detailed description and upon reference to the accompanying drawings in which: Figure 1 is a schematic illustration of the general system configuration constructed in accordance with the preferred embodiment; Figure 2 is a perspective view of a three-slot rack for use in the system of Figure 1; Figure 3A is a perspective view, with a partial view of the rack in phantom, of the component side of a circuit board mounted inside d e rack of Figure 2; Figure 3B is a perspective view, with a partial cross-sectional view of the rack in phantom, of the contact side of the circuit board mounted inside the rack of Figure 2; Figure 4 is a schematic of the electrical circuitry used in die rack design of Figure 2; Figure 5 is a perspective view of a back-up tφe cartridge on which a memory chip has been applied for use in the system of Figure 1; Figure 6 is a perspective view illustrating the construction of the applique for mounting the memory chip on the tape cartridge of Figure 5; Figures 7A and 7B are side and top elevations, respectively, illustrating the preferred manner in which the cartridge is placed in the rack; Figure 8 is an illustration of a memory map providing die unique ID number for the memory chips and addressable switches used in the preferred embodiment of the present invention; Figure 9 depicts a flow chart of system operation during a typical back-up operation from a computer system to a tape cartridge; Figure 10 is a perspective view of an applique for flush-mounting a chip on a tφe; Figure 11 is an exploded perspective view illustrating construction of the chip of Figure 10; Figure 12 is a perspective view of an alternative applique for flush-mounting a chip on a tape; Figure 13 is an exploded perspective view illustrating construction of the chip of Figure 12; and Figure 14 is a perspective view, with a partial cross-sectional view of the rack in phantom, of an alternative embodiment of the contact side of d e circuit board mounted inside the rack of Figure 2, modified to correspond to die applique embodiment shown in Figure 12. While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit die invention to the particular form disclosed, but on die contrary, die intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by d e appended claims. As a specific example, the present invention relates to the configuration and construction of a system for storing and tracking back-up tape cartridges generally. The terms "back-up tape cartridge," "tφe cartridge," and "cartridge" are used generically and synonymously in this disclosure to refer to all portable mass storage devices, including but not limited to, magnetic tφe cartridges and cassettes, optical storage units, CD ROM storage units, and other disk storage units. Typical magnetic tφe cartridges include 4mm cartridges, 8mm cartridges and QIC cartridges. Other representative magnetic tape cartridges include 19mm, digital linear tφe (DLT), DI, D2, 3480-90, digital audio tapes (DAT) and VHS tapes. Odier tφe sizes may become available in d e future. The present invention is applicable to all of these various formats, and thus the term cartridge should not be construed as limiting d e present invention to a particular storage medium. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring initially to Figure 1, the present invention constructed in accordance with the preferred embodiment generally comprises a rack 50 with a plurality of slots 15 for receiving back- up tφe cartridges 25, a host central processing unit ("CPU") or microcontroller 35, and an interface 30 for electrically coupling the CPU 35 to circuitry contained in the rack 50. The host CPU 35 may comprise a microcontroller, personal computer, work-station, or other microprocessor-based controller. The system of Figure 1 may be used in either a robotic system in which the tφe cartridges 25 are handled automatically by a placement machine or may be implemented in a non-robotic system. In the preferred embodiment, a plurality of slots n are provided to accommodate n tφe cartridges 25. In addition, in the preferred embodiment, a visual indicator 45 is associated with each slot 15 and preferably is positioned adjacent die slot. Figure 1 shows a single rack 50 for housing the cartridges 25. The rack 50 may be designed to hold as many cartridges as necessary, or in the preferred embodiment, a plurality of racks may be used. The rack typically may be constructed to contain 5-200 slots. If a plurality of racks are used, each of die racks preferably connects to the host CPU 35 through the interface 30. In the preferred embodiment of Figure 1, d e interface 30 comprises an RS232 serial interface that connects electrically in series to each rack, so that the racks are connected together in a daisy- chain configuration. Alternatively, a star configuration can be implemented with the host CPU as the "center" of the star. The star configuration also is preferred if a radio link is used to couple die racks to the host CPU 35. As shown in Figure 1 and discussed in more detail below, each cartridge 25 preferably has mounted thereon a memory chip 40. The preferred physical construction of the rack 50 will now be described with reference to Figures 2, 3A and 3B. As best seen in Figure 2, die rack 50 generally includes a first side 17, a second side 19, a back portion 22, a front section 24, and a base 26. The two sides 17 and 19 preferably are positioned in parallel alignment, a distance x apart. The distance x is primarily determined by die number of slots 15 provided and d e width of each slot. The rack 50 may extend horizontally, with each slot 15 in parallel alignment along a horizontal plane defined by die base 26. Alternatively, the rack 50 may be positioned to extend vertically, if so desired by a user. To accommodate either d e horizontal or vertical position, the base 26 and first side 17 preferably are weighted to minimize tipping of the rack 50. The rack may be constructed of any suitable electrically insulating material. In the preferred embodiment, molded plastic is used as the material for the rack 50. Referring still to Figures 2, 3A and 3B, die rack 50 preferably includes a visual indicator 45 housed in die front section 24. As best seen in Figure 3A, the visual indicator 45 comprises a window 47 positioned in the exterior surface of front section 24, and an LED 49 mounted on a circuit board 55. The circuit board 55 preferably is mounted inside the rack structure 50, in die front section 24. The circuit board 55 includes die majority of the electrical circuitry for the rack design, and preferably includes a plurality (π) of LED's 49, a plurality (n) of resistors 57, a plurality (n) of addressable switches 61, a plurality (n) of addressable switches 63, and an addressable switch 67. The number n of resistors 57, LED's 49, and switches 61 and 63 is determined by the number of slots 15 provided in die rack 50. In the preferred embodiment, the electrical components are mounted on the front side or component side of die circuit board 55, as shown in Figure 3A. Referring to in Figures 3B and 7A, the back side or cartridge side of the circuit board 55 preferably includes a plurality (n) of electrical contacts 65 for electrically contacting memory chip 40, which mount on the cartridge 25. More detail regarding die memory chip 40 and the med od of attaching the memory chip 40 to the cartridge 25 will be provided below. Each of the electrical contacts 65 preferably comprises a pair of conductive springs 71, 73 which mount to the circuit board 55, and which extend into slot 15. Details regarding the slot configuration will now be described with reference to Figures 2, 7A and 7B. The slots 15 preferably have a generally three-dimensional, rectangular configuration to receive the generally rectangularly-shaped tφe cartridges 25. As one skilled in die art will immediately understand, however, odier slot configurations may be used to accommodate cartridges characterized by odier shapes. The slot 15 includes a channel 37 in die front section 24 of the rack to accommodate die touch memory chip 40. In the preferred embodiment, die widdi a of the slot 15 preferably is defined by die thickness of the cartridge plus 0.010" and die length b of the slot 15 preferably is defined as the widdi of the cartridge plus 0.030". Other tolerances also may be used without departing from the principles of the present invention. In die preferred embodiment, die rack 50 and slot 15 are configured so mat the cartridge 25 protrudes from the rack along its length, as shown in Figure 7A. The electrical circuit for the rack 50 will now be described in detail with reference to Figure 4. The circuit board 55 receives three external connections: a DC voltage power supply connection 81 (preferably of +5 volts), a data input line 85 from the host CPU 35 preferably via die RS232 interface 35, and a ground line 87 (GND) which also preferably forms part of die RS232 interface. The DC voltage power supply line 81 preferably provides operating power to the LED's 49. The data input line 85 from the electrical interface 35 preferably connects to the memory chips 40 through a plurality of electrical contacts 65 (which, as noted above, preferably comprises springs 71, 73). The data input line 85 also connects to LED addressable switches 61, slot addressable switches 63 and rack addressable switch 67. The addressable switches 61, 63, 67 preferably comprise DALLAS SEMICONDUCTOR* addressable switch, model number DS2405. The specification and description of protocol for the DS2405 is expressly incorporated by reference herein. In accordance with d e specification for the DS2405, the addressable switches 61, 63, 67 include diree terminals, a DATA terminal, a GROUND terminal, and an open drain output terminal PIO. The data line 85 connects to each of the DATA terminals of all of the switches 61, 63, 67 and to die memory chip 40 through spring 73 as shown in Figure 4. According to die preferred construction of the rack circuitry, the ground line 87 connects to the GROUND terminal of addressable switch 67. The PIO terminal of switch 67 preferably connects to the GROUND terminal of each of the addressable switches 63. The PIO terminal of switches 63 preferably connect to memory chip 40 via spring 71, and to die GROUND terminal of addressable switches 61. The PIO terminal of switches 61 connect to an associated LED 49 through a resistor 57. As will be discussed in more detail below and referring still to Figure 4, the addressable switch 67 determines whether the rack has been enabled by d e host CPU 35. If odier racks are provided, each of diose racks preferably includes an addressable switch 67 for enabling operation of that rack. As one skilled in die art will understand, each of addressable switches 67 have a different address to identify a particular rack. If switch 67 is activated, each of die addressable switches 63 become enabled by providing a path to ground for these switches. Addressable switches 63 enable selection or connection to a particular slot 15 in rack 50. If a switch 63 is activated, a connection is completed through contacts 65 to a memory chip 40. Each of the addressable switches 63 have a unique ID number to uniquely identify the associated slot location for independent selection by the host CPU. Selection of switch 63 also enables switch 61, and addressable switches 61 enable the associated LED 49. If activated, switch 61 functions to turn on LED 49. The memory chip 40 used in d e preferred embodiment comprises a DALLAS SEMICONDUCTOR* model number DS2401 touch memory chip. Alternatively, die DALLAS SEMICONDUCTOR* 1 Kbit Add-Only Memory device, model number DS2502 may be used instead. The specifications for the DS2401 and DS2502 are expressly incorporated by reference herein. The DS2401 touch memory chip includes a DATA terminal and a GROUND terminal, which connect via an applique 100 to the electrical contact 65 positioned in slot 15. Both the DS2401 and DS2502 include an electronic registration number that provides a unique identity. Both chips have a factory-lasered 64-bit ROM that includes a unique 48-bit serial number, an 8-bit chip return code (CRC), and an 8-bit Family code. Data is transferred serially to and from the memory chip 40 over a single data line 85 and ground return line 87 (Figure 4). Power for reading and writing to the touch memory device is obtained from the data line, without any need for an external power sour r The DS2401 and DS2502 devices comprise a Slave device for the host CPU (which comprises die Master). Preferably, the idle state for the memory chip 40 is high. The host CPU 35 preferably includes a pull-up resistor (not shown) to passively pull die data line 85 high. As will be apparent to one skilled in the art, the data line 85 may be asserted low by any Master or Slave connected to die data line 85 to perform a transaction. The DS2502 has the additional capability of a 1 kbit memory which can be used to provide an index on each memory chip 40 reflecting die contents of cartridge 25. Thus, for applications where it is desired to provide information on the memory chip 40 regarding the contents and usage of d e cartridge 25, the DS2502 chip is preferred as the memory chip. In accordance with die specifications of the DS2502, the memory is comprised of an EPROM circuit. Referring now to Figures 5, 6 and 7A, die manner in which the memory circuit 40 is attached to the cartridge 25 will now be described in accordance with die preferred embodiment. In a preferred embodiment an applique 100 is used to attach chip 40 to cartridge 25. The φplique 100 preferably includes a conductive surface 110 for connecting to electrical contact 65, a conductive adhesive 115 for attaching the conductive surface 110 to the chip 40, a film carrier 120 supporting die conductive surface 110, and a laminating film 125 encapsulating the chip 40. In die preferred embodiment, the chip 40 and φplique 100 are positioned in a molded recess 91 in cartridge 25, which typically is provided by cartridge manufacturers to accommodate labels. The chip 40 and applique 100 are sufficiently thin, however, that a recess is not absolutely required for implementation of the present invention. The overall thickness of the applique 100 preferably is between 0.010" - 0.015", except in the region of the chip 40 where the thickness preferably is approximately 0.170". The conductive surface 110 preferably comprises a pair of conductive strips 112, 114 for mating with respective ones of the springs 71, 73 when the cartridge has been inserted in die slot 15 (see Figure 7A). The strips 112, 114 preferably are oositioned in parallel and extend along die lengdi of the applique 100. Preferably the strips 112, 114 have a widdi greater than the widdi of die springs 71, 73 to insure a proper electrical contact. Typical dimensions for the strips are an inch in length and a quarter inch in widdi, although odier sizes may be used as desired. The conductive adhesive 115 functions to attach the chip 40 to the conductive strips 112, 114, and to provide an electrical connection between the DATA terminal and die GROUND terminal of the chip 40 and die conductive strips 112, 114. The conductive surface 110 preferably is fabricated by conventional techniques on a film carrier 120. The film carrier 120 is relatively rigid to provide support to d e conductive strips during handling and attachment of die φplique 100 to the cartridge 25. The film carrier 120 preferably comprises the base material of the φplique 100. Film carrier 120 attaches to the cartridge 25 by a suitable pressure sensitive adhesive 130. A laminating film 125 is used to encapsulate the chip and hold it securely in position within the φplique 100. In die preferred embodiment, d e laminating film 125 includes an aperture 127 for exposing die conductive strips 112, 114 so that an electrical connection can be made to springs 71 , 73. The preferred operation of die system will now be described with reference to the DALLAS SEMICONDUCTOR* protocol. If other memory chips or switches are used odier dian those listed herein, die operation of the system may be modified if necessary to accommodate different protocols of the substituted devices. Use of odier chips and switches can and may be used by one skilled in d e art, however, without departing from d e principles of die present invention. As described above, a memory chip 40 is mounted on each cartridge 25, and each cartridge is inserted in a slot 15 in one or more racks 50. The racks 50 connect via an interface 30 (such as an RS232 cable) to the host CPU 35. In die preferred embodiment, die interface comprises a single data line 85 and ground return line 87. Circuitry in the rack 50 connects the data line 85 to each of die memory chips 40. An LED 49 is mounted adjacent each slot 15 to indicate which cartridges have been selected for a particular job. Alternatively, bus lines could be used to provide direct connections between each memory chip and die host CPU. Connection of the data line 85 to a particular rack 50 is enabled by an addressable switch 67. Data signals transmitted from the host CPU 35 must reflect d e address of switch 67 for operation to that rack to be enabled. Once die particular rack has been enabled, addressable switches 63 determine which slots 15 (or cartridges 25) have been enabled by die host CPU 35. Similarly, addressable switches 61 determine which LED's 49 will be illuminated by die host CPU 25. The present invention preferably includes die ability of d e host CPU 35 to read and write to each of die memory chips 40. In addition, d e host CPU 35 has die cφability to determine which cartridges are stored in each rack (as identified by die ID number of d e associated memory chip 40), to determine each time a cartridge is removed or inserted, and to determine specifically die ID number of the removed or inserted cartridge. Other applications of the present invention include providing lists of cartridges in each rack, a listing of all back-up jobs contained in each cartridge, a listing of all back-up jobs available from a particular rack, search capabilities to identify die rack and cartridge where a particular back-up job can be found, audit trails to determine when back-up jobs were started and completed, die user who performed die back-up, die time that the cartridge was removed from die rack and die time it was returned, and a listing of back-up jobs by date or generation. The system also can determine if a user is removing cartridges without authorization, and if cartridges have been misfiled in die wrong rack or in the wrong slot. When a cartridge 25 is first introduced to the system, a memory chip 40 is placed on die chip using the φplique 100. The ID number of mat memory chip 40 then is correlated by a user to die back-up jobs already contained on that cartridge 25. This correlation preferably is made direcdy into the memory of the memory chip, if sufficient memory is provided. For this feature, the DALLAS SEMICONDUCTOR* DS2502 chip is preferred with 1 kbit of memory. If sufficient memory space is not available in the memory chip, or in addition to storage of that information in the chip, the correlation of chip ID number and die contents of d e cartridge can be made in die memory of the host CPU. After this initialization procedure, subsequent back-up operations are automatically recorded. Periodically thereafter (which may be a period of a few milliseconds to a few minutes, depending upon die requirements and desired precision of die system), d e host CPU 35 polls each slot 15 in each rack 50 to determine if a cartridge 25 is present in each slot. If a cartridge 25 is present in a slot 15, the host CPU 35 reads die memory chip ID number for that cartridge. The host CPU 35 then compares the location of each cartridge with its previous location (which can be stored in memory or software), or with a desired location (that can be similarly stored) and produces an output to d e operator or sets a flag in a control or status register in the host to indicate cartridges are missing or misfiled. Each of the addressable switches, including die switch for the rack (67), the switches for die slots (63) and die switches for the LED's (61) all include a unique address (or ID number) which is physically etched by known techniques into die chip at the time it is manufactured. The host CPU preferably includes a table in memory or in software that identifies die address of each switch in die system. In this fashion, the host CPU 35 can select die appropriate rack and slot (or LED) during polling of the slots, and for other system operations. Pursuant to the protocol of the various DALLAS SEMICONDUCTOR* chips, information is transferred in 60 microsecond time slots or windows (for potential frequency of 16.3 kHz). The time slots are synchronized by operation of die host CPU 35. The CPU 35 transmits a Reset pulse by asserting the data line 85 low for at least 8 time slots (or approximately 480 microseconds). Each Slave chip connected to die data line 85 is syndironized by die Reset pulse and in response will return a Presence pulse. The host CPU passively asserts the data line 85 high (dirough the pull-up resistor) for 8 time slots to allow sufficient time for the Slave chips to return a Presence pulse on the data line 85. Use of this protocol allows data transmissions to be terminated and restarted at any time. After the Slave devices and host CPU have been synchronized by die Reset and Presence pulses, the CPU 35 issues a Match ROM command for each of the memory chips 40 that are known to reside in any of die racks. Each of the Match ROM commands, according to die DALLAS SEMICONDUCTOR* protocol, includes an ID number for die memory chip 40 that die CPU is attempting to locate. To implement this feature, all of the slot switches 63 are enabled to permit transmission to each memory chip 40. Only the memory chip 40 with die matching ID number will respond to die Match ROM command. Once d e response is received subsequent transactions, such as read or write cycles, can be completed. The host CPU also can determine die slot 15 where die memory chip (and cartridge) are located dirough various techniques, including polling each slot switch 63 and sending die Match ROM command. A Search ROM command also is available in the DALLAS SEMICONDUCTOR* protocol which can be used by the host CPU 35 to determine die ID number of every memory chip 40 located in d e racks. Other commands and options may be available depending on the particular chip used. The various commands preferably are transferred serially bit-by-bit over the data line 85. A single bit (representing either a digital "0" or a digital "1") preferably is transferred in each time slot dirough die use of pulse width modulation techniques. In accordance with the preferred embodiment, d e transmitting device (eidier the CPU or a Slave device) begins the sequence by asserting die data line 85 low. According to the DALLAS SEMICONDUCTOR* specifications, a logic "1" is transferred if die widdi of die low pulse does not exceed 15 microseconds, while a logic "0" is transferred if d e width of d e pulse exceeds 60 microseconds. The receiving chip samples the data line 85 at thirty microseconds after the data line 85 is asserted low to determine if die data line is still low (to indicate a logic "0") or has been deasserted high (to indicate a logic " 1 "). Determination of die next bit does not occur until die data line 85 is again asserted low. All of die required number of bits are transmitted in similar fashion. Each of the memory chips 40 and addressable switches 61, 63, 67 have a similar internal data structure. Each of the chips and switches includes an internal read only memory (ROM) as shown in Figure 8. The ROM is mapped into an 8-bit (or single byte) Family code to identify die family (which typically indicates die functionality and capacity of that model). For example, d e DS2401 has a Family Code (in hexadecimal notation) of Olh, while die DS2405 has a Family Code of 05h, and the DS2502 has a Family Code of 09h. The next 48-bits (or 6 bytes) include the unique serial number or ID number for the chip or switch. The last 8-bits (or 1 byte) comprises a CRC Code, which is used to verify the accuracy of die transmitted data in accordance with known techniques. The CRC Code reflects certain characteristics of the ID number and Family Code and is recalculated by die receiving device and compared with die transmitted CRC Code in accordance with DALLAS SEMICONDUCTOR* protocol. If a discrepancy is detected, the transmission is repeated. As noted above, these 8 bytes are permanendy etched in the silicon of die chip or switch at the time it is manufactured. The operation of die system during a typical back-up operation will now be described widi reference to Figure 9. After a back-up operation is indicated by an operator, in step 202 the host CPU lists on an associated monitor all back-up jobs from all of the cartridges present in the system. This listing can be done chronologically, alphabetically, or by cartridge. In step 204 the user selects the back-up job to be supplemented preferably by highlighting the desired back-up job. In step 206 die host CPU identifies die cartridge containing die desired back-up files, and turns on the LED or LED's in the racks to indicate to the user the location of the cartridges with die desired back-up files. The system preferably defaults to the cartridge with die oldest generation for that back-up file, but the system permits the user to select any of die cartridges by ID number, contents or date. Next, in step 208, the CPU determines if die cartridge has been selected, or that a cartridge containing relevant files is missing, or that a new cartridge must be used. After the cartridge is removed, the CPU loads die back-up program (step 210) and executes die back-up program with suitable prompts to back-up files onto the cartridge. After the back-up is complete, the CPU exits the back-up program (step 212) and issues a prompt instructing the user to return the cartridge to the rack (step 214). The cartridge preferably can be placed in any empty slot in the same rack. If the cartridge is not returned within a preselected time period after completion of the back-up, die CPU may issue an alarm in step 216. Once the cartridge has been returned, in step 218 the CPU lists die information mat will be recorded for each cartridge, to provide time, usage and odier information pertaining to the most recent operation of that cartridge. The user can change this information if desired. In step 220, die CPU writes the new information to the memory chip to update the index contained therein, or alternatively modifies similar information stored in die CPU memory. The CPU may momentarily turn on an LED adjacent die respective cartridges to indicate that die update is complete for each cartridge. If a cartridge is removed while an update is being made to that cartridge, an error message will be displayed, and die update will be delayed. An almost identical operation may be used to perform a restore operation. In addition to die operations described above, it may be desirable to update information on the memory chip as the status of the chip changes. Typically, the status of the chip changes only when information is written onto or deleted off of it. Hence, it is preferred that the tφe driver assembly be adapted to include electrical connections such that die CPU can contact the chip simultaneously with any changes that are made to die contents of the tφe. Such an update is equivalent to linking steps 210 and 220 above, so that the CPU automatically updates die tracking information on die chip when it causes a back-up to that tφe. This has particular applicability in fully automated systems. Once in the storage rack, neither the contents of the tapes nor their chips are subject to change, and die chips may be read, or polled, repeatedly for tracking purposes. Referring now to Figures 10 and 11, die flush-mount φplique 300 of the present invention includes a film carrier 310 having an outer surface 312 and inner surface 314. A chip 320 is mounted on inner surface 314 and a pair of conductive contact pads 322, 324 are affixed to outer surface 312. Electrical leads 332, 334 form electrical connections between the terminals of chip 320 and d e conductive contact pads 322, 324 respectively. Because chip 320 and contact pads 322, 324 are on opposite sides of film carrier 310, film carrier 310 is provided with a pair of apertures 326, 328, dirough which leads 332, 334 pass. As stated above, film carrier 310 preferably comprises a thin rigid material capable of supporting die electrical components of the φplique. According to d e embodiment shown in Figures 10 and 11 , pads 322, 324 are sequentially positioned along die longitudinal axis of the applique 300, radier parallel to it as described above. In this manner, pads 322, 324 are reconfigured to facilitate electrical contact with d e conducting springs in die rack. In instances where the degree of lateral variation in die position of a tφe within die rack is too great to allow consistent contact with d e parallel-placed strips 112, 114 disclosed above, the transverse positioning of pads 322, 324 allows consistent contact regardless of variations in lateral placement. When pads 322, 324 are offset in this manner, the rack springs 371, 373 must likewise be offset along the longitudinal axis of d e φplique, so that each spring contacts one pad, as shown in Figure 14. In the embodiment shown in Figures 10 and 11, apertures 326, 328 are adjacent one anodier and d e leads 332, 324 pass dirough film carrier 310 side by side. Lead 332 connects direcdy to pad 322, while lead 334 skirts pad 322 to connect to pad 324. Referring briefly to Figures 12 and 13, an alternative embodiment is shown, wherein apertures 326, 328 are offset to correspond to die offset positions of pads 322, 324. Thus, while die portions of leads 332, 334 that are on inner surface 314 are of different lengths, pad 322 does not have to be shortened to avoid lead 334 and therefore can have a surface area equal to that of pad 324. The configuration shown in Figures 12 and 13 is advantageous in that it reduces d e chance that misalignment of a tφe in the rack will result in undesired cross-contact of springs 371, 373 with pads 322, 324. As shown in Figures 11 and 13, the inner surface 314 of carrier 310 is preferably received on one side of a double-sided pressure sensitive adhesive strip 340. Adhesive strip 340 is provided with a cut-out 342, which is sized and positioned to receive chip 320. Adhesive strip 340 covers leads 332, 334 and ensures a fixed relationship between the components on inner surface 314. The second side of adhesive strip 340 is affixed to the tφe cartridge. A laminating film 350 covers most of the outer surface 312 of carrier strip 310. Laminating film 350 preferably comprises a material that can be written on, so that film 350 is suitable for receiving a handwritten or printed identification. Laminating film 350 covers apertures 326, 328 and a portion of leads 332, 334, further helping to ensure that the electrical components of the applique do not move relative to each other. Because chip 320 is thicker than adhesive strip 340, it extends somewhat through cutout 342. The housing wall of the tφe cartridge is preferably provided with a corresponding cutout or indentation, in which chip 320 is received. In this manner, the outside of φplique 300 can be made flat and substantially flush with the outside of die tφe cartridge. In a second alternative embodiment, chip 320 can be incorporated into die housing itself when the housing is molded. In this embodiment, eidier the chip alone or the chip and die film carrier 310, including leads 332, 334, pads 322, 324, are included in die cartridge housing mold and die protective laminating film 350 is added when die housing is removed from die mold. Regardless of how the chip is affixed to die tφe cartridge, if it is affixed by the tφe manufacturer, testing of the φplique and of the chip itself can be incorporated into die post- manufacturing quality control systems. Providing a tφe cartridge having a touch memory chip already incorporated d erein allows the consumer to use die cartridge as-purchased, widiout having to undertake die additional step of affixing an applique. In addition, the chip mounted on die inner surface of film carrier 310 is better protected and allows a larger labelling space than would otherwise be possible. While a preferred embodiment of die invention has been shown and described, modifications thereof can be made by one skilled in die art without departing from die spirit of die invention. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims

WHAT IS CLAIMED IS:WE CLAIM:

1. A system for tracking back-up tape cartridges, comprising: a plurality of memory chips, one of which is mounted on each of said cartridges, with each of said memory chips including a unique identification number to specifically identify said cartridge on which it is mounted and additional information regarding die contents of die cartridge; an applique attaching each of said memory chips to said cartridge, said applique including; a film carrier which attaches to said cartridge; an exposed conductive surface electrically coupled to said memory chip, said conductive surface provided on an upper surface of said film carrier; a rack widi a plurality of slots for receiving said plurality of cartridges dierein, wherein each of said rack slots includes an electrical contact for electrically contacting said conductive surface when each of said cartridges is inserted in said slots; and said rack includes circuitry for transferring signals to and from said plurality of memory chips to permit tracking and monitoring of said cartridges in said system.

2. A system as in claim 1, wherein said applique further comprises a laminating film encapsulating the upper surface of said memory chip, said laminating film including an aperture for exposing a portion of said conductive surface.

3. A system as in claim 1, wherein said conductive surface comprises a pair of conductive strips.

4. A system as in claim 3, wherein said conductive strips are aligned substantially in parallel.

5. A system as in claim 3, wherein one of said conductive strips electrically connects to a DATA terminal of said memory chip, and die other of said conductive strips electrically connects to a GROUND terminal of said memory chip.

6. A system as in claim 5, further comprising a conductive adhesive for connecting said memory chip terminals to said conductive strips.

7. A system as in claim 1, further comprising a host CPU connected to said rack circuitry via an interface.

8. A system as in claim 7, wherein said interface comprises a data line and a ground line.

9. A system as in claim 8, wherein said rack circuitry includes a rack addressable switch for enabling said rack circuitry in response to a proper address signal from said host CPU.

10. A system as in claim 9, wherein said rack circuitry further includes a plurality of slot addressable switches which provide a unique address for each slot.

11. A system as in claim 10, wherein said host CPU enables individual slots by transmitting the unique address of die associated slot addressable switch.

12. A system as in claim 11, wherein a communication path is completed to said memory chip on said associated cartridge when the slot receiving said cartridge is enabled.

13. A system as in claim 12, further comprising an LED associated widi each slot.

14. A system as in claim 13, wherein each of said LED's includes an LED addressable switch associated therewith.

15. A system as in claim 14, wherein said host CPU polls each of said slots to determine if a particular location is positioned therein.

16. A system as in claim 1, wherein said electrical contact comprises a first conductive spring for contacting one of said conductive strips and a second conductive spring for contacting the other of said conductive strips.

17. A system for receiving a plurality of tape cartridges, wherein said tape cartridges each include a memory chip widi a unique number identifying said tape cartridge, said system comprising: a central processing unit electrically coupled to said memory chips, said central processing unit capable of performing data transactions to said memory chips; a rack for receiving said plurality of tape cartridges, said rack including a plurality of slots, with each of said plurality of slots receiving one of said cartridges; an electrical contact in each slot for coupling to said memory chip on said cartridge; a circuit board electrically connected to said electrical contacts.

18. A system as in claim 17, wherein said plurality of slots are positioned in parallel along the length of said rack, and said circuit board extends perpendicularly to said slots, along the length of said rack.

19. A system as in claim 18, wherein said electrical contacts extend from one side of said circuit board.

20. A system as in claim 19, wherein said electrical contacts comprise a pair of conductive springs.

21. A tracking system, comprising: a plurality of cartridges, wherein each of said cartridges includes a chip with a unique identification number; a rack wid a plurality of slots for receiving said cartridges; a host CPU electrically coupled to said chips; wherein said host CPU is capable of writing data to said chip reflecting d e contents of said cartridge on which said chip is mounted.

22. A system as in claim 21 , wherein said CPU also is capable of correlating die unique identification number of die chip with the slot in which the associated cartridge is located.

23. A system as in claim 22, wherein the CPU is capable of detecting d e removal of a cartridge from said rack based upon die absence of the associated chip's unique identification number.

24. A system as in claim 22, wherein CPU is capable of detecting die insertion of a cartridge into said rack.

25. A system as in claim 24 wherein CPU is capable of identifying the unique identification number of die chip attached to the newly inserted cartridge into said rack.

26. A system as in claim 23 wherein the CPU is capable of identifying die time of removal or insertion of a cartridge widi in said rack.

27. A system as in claim 26 wherein die CPU is capable if identifying die specific slot from which die cartridge was removed or inserted within said rack.

28. A system as in claim 22, wherein said CPU also is capable of correlating the unique identification number of die chip within a specific rack wherein multiple racks are interconnected.

29. A system as in claim 21, wherein die CPU is capable of reading from said chip data reflecting the contents of the cartridge on which said chip is mounted.

30. A system as in claim 21, wherein the CPU is capable of identifying die operator who removes or inserts a cartridge.

31. A system for tracking back-up tape cartridges, comprising: a plurality of memory chips, one of which is affixed to each of said cartridges such diat an outer surface of said chip is flush with an outer surface of the cartridge, widi each of said memory chips including a unique identification number to specifically identify said cartridge on which it is mounted; a conductive surface electrically coupled to said memory chip, said conductive surface affixed to an outer surface of said cartridge.

32. A system as in claim 31 , further including a laminating film encapsulating die outer surface of said memory chip while exposing a portion of said conductive surface.

33. A system as in claim 31, wherein said memory chip extends through a cutout in the outer surface of the cartridge.

34. A system as in claim 31 , wherein said conductive surface comprises a pair of conductive contact pads.

35. A sy as in claim 34, wherein said contact pads are aligned in series.

36. A sys.em as in claim 34, wherein one of said conductive pads electrically connects to a DATA terminal of said memory chip, and die odier of said conductive pads electrically connects to a GROUND terminal of said memory chip.

37. A system as in claim 35, further comprising a pair of conducting leads for connecting said memory chip terminals to said conductive pads.

38. A system as in claim 37, wherein said contact pads are affixed to a first side of a film carrier and said memory chip is affixed to a second side of said film carrier and said leads extend dirough said film carrier.

39. A system as in claim 38, further comprising a rack widi a plurality of slots for receiving said plurality of cartridges dierein.

40. A system as in claim 39, wherein said slots include an electrical contact for connecting electrically to said conductive pads.

41. A system as in claim 40, wherein said electrical contact comprises a first conductive spring for contacting one of said conductive pads and a second conductive spring for contacting the other of said conductive pads.

42. A system as in claim 41, wherein said memory chip has a memory for storing data reflecting information stored in said cartridge.

43. A system for tracking back-up tape cartridges, comprising: a plurality of memory chips, one of which is embedded in a wall of each of said cartridges, widi each of said memory chips including a unique identification number to specifically identify said cartridge on which it is mounted; a conductive surface electrically coupled to said memory chip, said conductive surface affixed to an outer surface of said cartridge.

44. A system as in claim 43 wherein an outer surface of said chip is flush with an outer surface of the cartridge.

45. A tape cartridge, comprising: a tape having first and second ends; a pair of spools for winding said tape, said first tape end being affixed to one spool and said second tape end being affixed to die other spool; a cartridge housing in which said spools are mounted and said tape is housed, said housing including a cutout; and a chip applique affixed to said housing, said applique comprising a film carrier having first and second sides; a touch memory chip affixed to a said first side; and a plurality of contact pads affixed to said second side; said film carrier being affixed to said housing such that said chip is received in said cutout.

46. A tape cartridge, comprising: a tape having first and second ends; a pair of spools for winding said tape, said first tape end being affixed to one spool and said second tape end being affixed to die odier spool; a cartridge housing in which said spools are mounted and said tape is housed; a chip embedded in said housing; and a pair of contacts affixed to die outside of said housing and electrically connected to said chip.