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WO1997048019A1 - Procede de fabrication d'un photomasque, procede de fabrication d'un masque a dephasage, et procede de fabrication d'un composant a semi-conducteur - Google Patents

Procede de fabrication d'un photomasque, procede de fabrication d'un masque a dephasage, et procede de fabrication d'un composant a semi-conducteur Download PDF

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Publication number
WO1997048019A1
WO1997048019A1 PCT/JP1996/001574 JP9601574W WO9748019A1 WO 1997048019 A1 WO1997048019 A1 WO 1997048019A1 JP 9601574 W JP9601574 W JP 9601574W WO 9748019 A1 WO9748019 A1 WO 9748019A1
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WO
WIPO (PCT)
Prior art keywords
data
design
change
drawing data
manufacturing
Prior art date
Application number
PCT/JP1996/001574
Other languages
English (en)
Japanese (ja)
Inventor
Eiji Tsujimoto
Yasuo Sato
Toshio Suzuki
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/001574 priority Critical patent/WO1997048019A1/fr
Publication of WO1997048019A1 publication Critical patent/WO1997048019A1/fr

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50

Definitions

  • the present invention relates to a method for manufacturing a photomask, a method for manufacturing a phase shift mask, and a method for manufacturing a semiconductor device.
  • the present invention relates to a mask manufacturing technology, and more particularly to a technology effective when applied to a computer-aided automatic layout of a mask pattern of a photomask for forming circuit elements on a semiconductor wafer.
  • Japanese Unexamined Patent Publication No. 5-323655 describes a technique for managing the log for each mask layer to prevent erroneous correction of the layout data.
  • Japanese Patent Application Laid-Open No. 4-3727155 discloses a reference pattern and a change pattern. A technique is described in which a difference is checked and a change miss is checked, and a pattern is corrected in an edit.
  • Japanese Patent Application Laid-Open No. Hei 4-2385979 the changed subnet was deleted from the data before the change, the portion which was not placed due to the deletion was relocated, and further added. It describes techniques for arranging blocks and nets.
  • Japanese Patent Application Laid-Open No. H5-677756 describes a technique for interactively changing an endless dress information file and generating a mask pattern for a mask ROM according to the changed file.
  • Japanese Patent Application Laid-Open No. 3-206646 describes a technique of combining a plurality of mask data into integrated circuits having different design rules into one integrated circuit.
  • Japanese Patent Application Laid-Open No. Sho 61-1985889 discloses a technique of integrating a master and mask data of a changed portion to form a wiring pattern in a region having no wiring.
  • Japanese Patent Application Laid-Open No. 3-2699767 describes a technique for designing an electronic circuit by specifying a remodeled portion accompanying a design change.
  • an object of the present invention is to provide a technique capable of creating a mask pattern of a photomask in a short time according to a design change.
  • the method for manufacturing a photomask according to the present invention includes the following steps (a) to (e).
  • the step (C) includes the following steps (C 1) to (C 1).
  • (C,) a step of obtaining parent data that is design data of the smallest block that includes the change area in the hierarchically designed design data
  • (c2) a step of transforming the graphic coordinates of the child data relating to the change area into the coordinate system of the parent data among the child data which are the design data of the lower hierarchy of the parent data;
  • the method of manufacturing a photomask according to the present invention is characterized by including the following steps (a) to (f).
  • a method of manufacturing a phase shift mask according to the present invention is characterized by including the following steps (a) to (f).
  • a method of manufacturing a semiconductor device transfers a pattern formed on a photomask onto a semiconductor wafer to form a predetermined electronic circuit, and includes the following steps (a) to (h). It is assumed that.
  • step (c) may comprise the following steps (C l) ⁇ (c 3 ).
  • (c 2 ) a step of converting the graphic coordinates of the child data relating to the change area to the coordinate system of the parent data among the child data which is the design data of the lower hierarchy of the parent data;
  • the method for manufacturing a semiconductor device according to the present invention includes transferring a pattern formed on a photomask onto a semiconductor wafer to form a predetermined electronic circuit.
  • a pattern formed on a phase shift mask is transferred onto a semiconductor wafer to form a predetermined electronic circuit.
  • the following steps ( a ) to (i) It is characterized by including.
  • step (d) If there is an area that needs correction, create new drawing data for that area according to the details of the correction. If it does not exist, move to step (f).
  • the drawing data is created while performing an exposure prediction operation in a limited manner on the corrected area.
  • FIG. 1 is a process diagram showing the flow of photomask design and development
  • FIG. 2 is a flow chart showing an outline of a photomask manufacturing method according to an embodiment of the present invention
  • FIG. 5 is a flow chart showing a part of the flow chart of FIG. 2 in detail
  • FIG. 6 is an output figure of a change area when the flow chart of FIG. 5 is executed.
  • FIG. 7 is a flowchart showing another part of the flowchart of FIG. 2 in detail
  • FIG. 8 is an explanatory diagram conceptually showing the contents of a photomask design change
  • FIG. 9 is a diagram of FIG.
  • FIG. 10 is an explanatory diagram showing a hierarchical structure of design data constituting a photomask
  • FIG. 10 is an explanatory diagram showing a hierarchical structure of design data constituting a photomask
  • FIG. 10 is a conceptual diagram showing a data structure of design data stored in a layout design
  • FIG. 11 is still another flowchart of FIG. Flow chart showing some details
  • 12 is a schematic diagram showing an exposure apparatus using the manufactured photomask.
  • FIG. 13 is a flow chart schematically showing a photomask manufacturing method according to another embodiment of the present invention. Is an explanatory diagram conceptually showing the contents of the photomask design change
  • FIG. 15 is an explanatory diagram showing the hierarchical structure of the design data constituting the photomask in FIG. 14, and
  • FIG. 16 is a diagram showing still another embodiment of the present invention.
  • FIG. 17 is a flow chart schematically showing a method of manufacturing a phase shift mask which is a photomask of the embodiment.
  • FIG. 17 is an explanatory view showing a transfer pattern formed on a semiconductor substrate according to the flow chart of FIG.
  • FIG. 18 is an explanatory diagram showing a mask pattern
  • FIG. 19 is an explanatory diagram showing a transfer pattern formed on a semiconductor substrate by the mask pattern of FIG. 18, and
  • FIG. 20 is for forming the transfer pattern of FIG.
  • Shows the mask pattern of FIG. 21 is an explanatory diagram showing another transfer pattern formed on the semiconductor wafer in accordance with the flowchart of FIG. 16,
  • FIG. 22 is an explanatory diagram showing a mask pattern
  • FIG. FIG. 24 is an explanatory view showing a transfer pattern formed on the semiconductor wafer by the mask pattern of FIG. 2, and
  • FIG. 24 is an explanatory view showing a mask pattern for forming the transfer pattern of FIG. 21.
  • Fig. 1 is a process diagram showing the flow of photomask design and development.
  • Fig. 2 is a flowchart showing an outline of a photomask manufacturing method according to an embodiment of the present invention.
  • Figs. 3 and 4 are diagrams. 2 is an explanatory diagram along the flowchart of FIG. 2
  • FIG. 5 is a flowchart showing a part of the flowchart of FIG. 2 in detail
  • FIG. 6 is an output of a change area when the flowchart of FIG. 5 is executed.
  • Fig. 7 is an explanatory diagram showing a figure
  • Fig. 7 is a flowchart showing another part of the flowchart of Fig. 2 in detail
  • FIG. 8 is an explanatory diagram conceptually showing the contents of a design change of a photomask
  • Fig. 9 is a diagram. 8 is an explanatory diagram showing a hierarchical structure of design data constituting a photomask
  • FIG. 10 is a conceptual diagram showing a data structure of design data stored in a layout design
  • FIG. 11 is a flow chart of FIG. A flowchart detailing yet another part of the 1 2 is a schematic diagram showing an exposure device manufactured photomasks are used.
  • a function specification of a semiconductor device is created based on the system specification, and details of operation are designed.
  • the operation of the semiconductor device is determined using a function description language and a state transition diagram, and the architecture, for example, the number of bits and the number of function registers of the logic block is determined.
  • the logic 'test design process S 2 is described in the logic 'test design process S 2, is described a system function design step S, the
  • the shape and electrical performance such as Bok Rungis evening based on production conditions of the semiconductors devices with structure description language or schematic of the foregoing is designed. Furthermore, basic circuits and circuit cells are designed on the basis of these, and the entire circuit is designed.
  • layout design process S 4 the arrangement of the logic gate Bok using logic cell library that has been prepared by a logical 'test design process S connection information obtained by 2 and the circuit device design step S 3, the wiring is performed
  • design data that is an outline of the pattern of the photomask M is determined.
  • this design data is generally designed in a hierarchical manner, and the design efficiency is improved by reducing the complexity of the design.
  • the artwork process S 5, against the design data in the layout design process S 4, it is an drawing data subjected to a treatment capable processed by the drawing device. Then, as described above, when the drawing data is applied to the drawing apparatus A, a photomask M on which a predetermined pattern is formed is obtained.
  • a photomask M is manufactured according to the flowchart shown in FIG. That is, the design data before and after the layout pattern design change is compared (100). Next, the influence range of the design data before the change in the design data after the change, that is, the change area in the design data after the design change is obtained from the comparison result (200). New drawing data is created based on the data (300).
  • FIG. 3 (a) shows the design data D before the design change.
  • 3 (b) is a design data D N after the design change.
  • the pattern P shown in Fig. 3 (a) was changed due to a design change.
  • FIG. 3 (b) a case where the pattern P N has been moved downward in the drawing is shown. Therefore, by comparing the two design data Do and DN with each other, the changed area R is obtained (FIG. 3 (c)).
  • FIG. 4 (b) new drawing data S N is created for the change area R, and the drawing data S N and the drawing data So other than the change area R shown in FIG. rendering data S a of the whole when synthesizing the (drawing data excluding the modified area R by graphical operation from before the change drawing data) pattern is obtained, et al. (FIG. 4 (c)).
  • a photomask M is created using the drawing data S A shown in FIG. 4 (c).
  • the photomask M After the photomask M is prepared, including the embodiments described below, exposure is performed using the photomask M. Although the details will be described later, the exposure is to transfer a pattern formed on the photomask M onto the semiconductor wafer W to form a predetermined printed circuit. Each of the masks M is set at a predetermined position to perform pattern exposure.
  • FIG. 5 is a flowchart of the process
  • FIG. 6 shows an output figure of a changed region R obtained by executing the process.
  • an EOR Exclusive OR
  • FIG. 6 only different patterns ⁇ and PN (in the illustrated case, the pattern PO before the change and the pattern P N after the change) are extracted from the design data before and after the change.
  • the obtained minimum value is rounded down to a coordinate value that is a multiple of the minimum drawing unit (for example, 0.025 m) of the drawing device (203). Specifically, for example, if the minimum value of the X coordinate is 1.53 m, set it to 1.525 / m. Similar processing is performed for the minimum value of the Y coordinate. As a result, the minimum correction value that can be handled accurately by the drawing device
  • the maximum value is rounded up to a coordinate value that is a multiple of the minimum drawing unit of the drawing device (204). This is done in the same way as finding the modified minimum, for example, if the maximum value of the X coordinate is 2.56 m, it will be 2.575 m. In this case, the same applies to the minimum value of the Y wing.
  • the corrected maximum value (Xmu-i, ⁇ ,.,-. Di) is obtained.
  • modified maximum value (X m ,, H, Ym, -.. Di) may be obtained earlier towards the.
  • the E 0 R area becomes the change area R as it is.
  • each region of the C has a range surrounded by a broken line illustrated in the figure there range respectively have patterns P a, PB, and Pc as a graphic data.
  • Each block A, B, respectively block D in the C, E, block F, G, block H, I have cage containing Marete by a range surrounded by a broken line a figure existing range, respectively pattern P D , PE, PF, PG, PH, P, as graphic data.
  • Each graphic data is the coordinate system of the block to which it belongs (i.e., for example, the coordinate system of the pattern P A block A, the coordinates of the pattern P D block D System) is expressed.
  • the pattern P CN indicated by the chain line pattern P c is two points is a graphic data of the block C are respectively changed to a pattern P HN
  • the pattern P H is the graphic data of the block H is indicated by the two-dot chain line You.
  • the shaded portion is the change area R.
  • FIG. 9 shows the arrangement relationship of FIG. As shown in this figure, FIG. 8 shows design data hierarchically designed with block T as a vertex. For example, block T is parent data of blocks A, B, and C, and block A is blocks D, E Parent data.
  • design data of the smallest block including the change area R obtained as described above is obtained, This is set as parent data (301).
  • this is the parent data.
  • the design data of the lower hierarchy of the parent data that is, the child data is related to the change area R (302).
  • the block H is the force applied to the change area scale, and the block I is not applied. Therefore, in this case, the graphic coordinates of the block H covering the change area R in the child data are converted into the coordinate system of the block C which is the parent data (303). Thereby, the relative positional relationship of the graphic data of the block H in the block C is determined.
  • such processing is not performed on the block I that does not cover the change area R.
  • the above processing is performed for the following reason. That is, all figures in the drawing data are expressed in the coordinate system of the semiconductor chip, and the change region R is also expressed in this coordinate system.
  • the design data is hierarchically designed as described above. Therefore, it is only necessary to convert only the part of the child data in which the figure exists in the change region R to the coordinate system of the parent data and change them. If the figure existence range does not extend to the change area R, the child data is not subjected to coordinate conversion. As a result, only the necessary design data can be extracted and processed, and the change processing can be performed at high speed.
  • FIG. Illustrated the data structure of the design data for performing the change processing is shown in FIG. Illustrated As shown, this data structure is composed of block I, child block list, parent block list, layout information, and graphic data. This structure will be described by taking block A in the hierarchical structure in FIG. 9 as an example.
  • the block name of the target block (Block A), the head address of the child block list of the block (Block D), the head address of the parent block list (Block T), the figure existence range (Minimum value of coordinates of block A (X mi).
  • the child block list that has received the head address of the child block list stores the block list address (block D for block A) and the address of the next child block list (block E). Then, when the block list address is searched for the block list of the desired child block, various data centering on the block are expanded.
  • the parent block list that received the parent block list head address includes the block block K (block T for block A) and the address of the next parent block list (where block A has only block T as the parent block). There is none), and the location information address to the parent block (location information of block A in block T) is stored. And, as in the case of the child block list! If you search the block list of the desired parent block from the address, various data centered on that block will be developed.
  • the arrangement information stores the arrangement coordinates of the child block in the parent block (the arrangement coordinates of block A in block T). This data is used when the graphic coordinates are converted to the coordinate system of the parent block.
  • the figure data having received the figure data head address stores the layer name of the figure data, the next figure data address, the number of vertices of the figure data, and specific figure vertices.
  • the photomask M created by the above method is set in, for example, an exposure apparatus as shown in FIG. 12 and exposed.
  • a photomask (including a phase shift mask) M in the embodiment described below also has a pattern image transferred onto a semiconductor wafer W by the same procedure using, for example, the same exposure apparatus as in the present embodiment. You.
  • the illustrated exposure apparatus 10 is a reduced projection exposure apparatus that forms a mask pattern on a semiconductor wafer W by, for example, an area of 15 to 20 square meters by step and repeat.
  • the photomask M is a step-and-scan type light exposure device employing a catadioptric reduction optical system, an X-ray exposure device using soft X-rays,
  • the registry is spin-coated.
  • the semiconductor wafer W is placed on the housing 21 and is moved vertically and horizontally by the Z-axis carriage 22, the X-axis carriage 23, and the Y-axis carriage 24. It is designed to be step driven.
  • the photomask M for transferring a predetermined pattern onto the prebaked semiconductor wafer W is, for example, a reticle on which an original image of an integrated circuit pattern having a size five times the actual size is formed. Therefore, the pattern image is formed on the semiconductor wafer W. Exposure is performed by reducing the projection to 1/5.
  • the semiconductor wafer W is mounted on the wafer stage 21 and driven by the X, ⁇ , and Z-axis carriages 2, 2, 23, and 24. This is positioned at the exposure position. Further, the photomask M is set on the mask moving table 20 and is arranged on the optical path from the exposure light source 11 to the semiconductor wafer W, and is moved horizontally to perform the same positioning. After setting as described above, when the exposure light L is irradiated from the exposure light source 11, the exposure light L is incident on the photomask M, and is converted into a spot light beam by the reduction projection lens 19, and the light of the stage 21 is adjusted. The light is incident on the resist surface of the upper semiconductor wafer W. As a result, the pattern image is transferred to the semiconductor wafer W.
  • the resist After exposure, the resist is developed using a developer to form a resist pattern. The developer and rinse remaining in the resist are removed by evaporation to cure the resist. Finally, the mask pattern is finally transferred through the following processes: ashing and oxidizing removal of the unnecessary resist. The obtained semiconductor wafer w is obtained.
  • FIG. 13 is a flowchart showing an outline of a photomask manufacturing method according to another embodiment of the present invention.
  • FIG. 14 is an explanatory view conceptually showing the details of a photomask design change.
  • FIG. 15 is an explanatory diagram showing a hierarchical structure of design data constituting the photomask of FIG. 14.
  • the process up to the step of narrowing down the design data before and after the design change (600) and obtaining the change area in the design data after the change (700) is the same as that of the previously described embodiment.
  • the parent block, which is the design data of the minimum block including the change area, and the child block, which is the design data of the lower hierarchy, are extracted (80). 0).
  • each block has the same hierarchical structure as FIG. 9 as shown in FIG.
  • the shaded portion is the change area R.
  • the block C which is the minimum block including the change area R
  • the block C and the two blocks H.I which are the design data of the lower hierarchy, are extracted. . Therefore, as shown in the hatched portion in FIG. 14 and the hatched portion in FIG. 5, the blocks to be changed are C, H, and I.
  • the change area R Block I which is not affected by this, is different from the above-mentioned embodiment, which is excluded from the change.
  • new drawing data is created for the parent data (in the illustrated case, block C) and the child data (similarly, blocks H and I) according to the changed contents (900). Then, in the manner described above, the created drawing data and the unchanged drawing data are merged (100), and a photomask M is created (110). In this way, the parent data for the change area R and all the child data of this parent data Even if data is extracted and new drawing data is created for them,
  • a mask pattern for the accompanying photomask M can be created in a short time.
  • FIG. 16 is a flowchart showing an outline of a method for manufacturing a phase shift mask (photomask) according to still another embodiment of the present invention.
  • FIGS. 17 to 20 are explanatory diagrams of a phase shift mask with an auxiliary pattern, and FIG. 17 is an explanatory diagram showing a transfer pattern formed on a semiconductor wafer according to the flowchart of FIG.
  • FIG. 18 is an explanatory view showing a mask pattern,
  • FIG. 19 is an explanatory view showing a transfer pattern formed on a semiconductor substrate by the mask pattern of FIG. 18, and
  • FIG. 20 is a transfer pattern of FIG.
  • FIG. 4 is an explanatory diagram showing a mask pattern for forming a transfer pattern.
  • FIG. 21 to 24 are explanatory diagrams of a Levenson type phase shift mask
  • FIG. 21 shows a transfer pattern formed on a semiconductor device in accordance with the flowchart of FIG. 22 is an explanatory view showing a mask pattern
  • FIG. 23 is an explanatory view showing a transfer pattern formed on a semiconductor substrate by the mask pattern of FIG. 22, and
  • FIG. 24 is a transfer pattern of FIG. 21.
  • FIG. 4 is an explanatory view showing a mask pattern for forming a mask.
  • phase shift mask For example, a phase shift mask with an auxiliary pattern applied to the formation of a contact hole or the like is provided with an auxiliary opening having a size that is not transferred onto the substrate, and a phase shifter is provided at the opening or the auxiliary opening. And inverts the phase of light transmitted through the portion where the phase shifter is provided. Thereby, the spread of the skirt of the light intensity distribution of the transmitted light is suppressed, a steep light intensity distribution is obtained, and pattern formation is performed with good resolution.
  • a Levenson-type phase shift mask applied to the formation of a wiring layer has a phase shifter for inverting the phase on one side adjacent to an opening on the mask. Since the phases of the adjacent transmitted lights are inverted, they act to cancel each other out, so that the light intensity at the boundary of the transfer region becomes 0, and the pattern is formed with good resolution.
  • the present invention is not limited to a self-aligned phase shift mask or a transmission type phase shift mask. It is also applied to other phase shift masks such as a foot mask.
  • This embodiment is a method for manufacturing a phase shift mask for transferring a pattern onto a semiconductor substrate while selectively shifting the phase of light.
  • a provisional phase shift mask is prepared. Create typical drawing data (12000).
  • the phase shift mask with the auxiliary pattern is a pattern to be formed as shown in FIG. 18 (a).
  • auxiliary apertures 32 are formed automatically in which a sub-resolution phase shifter made of, for example, PMMA (polymethyl methacrylate) or SiO 2 film is formed.
  • Figure 18 (b) By synthesizing such a mask pattern, provisional drawing data S shown in FIG. 18 (c) is created.
  • the phase shift mask has a defect peculiar to the phase structure called a shift pattern defect. Therefore, in order to prevent the occurrence of shift pattern defects, an exposure prediction operation is performed on the drawing data S shown in FIG. 18 (c) in the physical mask pattern state by, for example, the die ratio reduction method (1). 3 0 0), and compares the calculation result with the design pattern. Then, an area where a shift pattern defect occurs in the drawing data S, that is, an area requiring correction, that is, a correction area R is obtained from the exposure prediction calculation result (140).
  • FIG. 19 shows the prediction result based on the drawing data S in FIG. 18 (c), that is, the pattern formed on the semiconductor wafer.
  • the drawing data S of FIG. 18 (c) an unnecessary pattern is formed between two transfer patterns as shown in the figure. Therefore, in the drawing data S, the auxiliary opening 32 between the transfer regions 31 becomes the correction region R.
  • new drawing data S according to the correction contents is created only for the area R (1500). That is, data correction is performed by restricting the automatic generation mode of the auxiliary opening 32, and the correction region R is formed as an integrated auxiliary opening 32 as shown in FIG. 20 (b). Then, the entire area is merged with the part that does not need to be corrected to form an auxiliary opening 32 shown in FIG.
  • the Levenson-type phase shift mask is designed to invert the phase of the transmitted light between adjacent transfer areas. Every other phase shifter is provided. Therefore, in order to form such a transfer pattern 30, a mask pattern having a transfer region 31a without a phase shifter shown in FIG. 22 (a) and a phase shifter shown in FIG.
  • the provisional drawing data S shown in FIG. 22 (c) is created using the mask pattern formed with the transfer region 31b having the following (1200).
  • new drawing data S is created for the correction area R only in accordance with the correction contents (1500).
  • a correction to form an auxiliary pattern 31c having a width W is made, and this is merged with Figs. 24 (a) and (b) to 4
  • the drawing data S shown in (d) is used (16000).
  • the left transfer area 31a becomes wider than the others by the width W in anticipation of the pattern narrowing.
  • the process (1) is performed until there is no area that needs to be corrected. 3 0 0-1 6 0 0) is repeated. At this time, it is desirable to perform the exposure prediction calculation only for the correction region R.
  • a phase shift mask is created (1700).
  • the correction region R is obtained based on the result of the exposure prediction calculation, and a new drawing data S is created only for the changed region R.
  • Overtime correction work can be performed in a short time.
  • the method for manufacturing a photomask, the method for manufacturing a phase shift mask, and the method for manufacturing a semiconductor device according to the present invention are suitable for use in a technique for changing the layout of a photomask forming a circuit element.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

Cette invention se rapporte à un procédé de fabrication d'un photomasque, qui comprend une étape (100) consistant à comparer les données de dessin précédant un changement de dessin avec les données suivant le changement de dessin, une étape (200) consistant à repérer les zones dans lesquelles des données de dessin ont été changées par rapport aux données de dessin d'origine, une étape (300) consistant à préparer de nouvelles données de tracé pour les zones à données changées selon les données changées, une étape (400) consistant à combiner les données de tracé des zones à données changées avec les données de tracé déjà préparées concernant les zones à données inchangées, et une étape (500) consistant à fabriquer un photomasque après le changement de dessin sur la base des données de tracé combinées.
PCT/JP1996/001574 1996-06-11 1996-06-11 Procede de fabrication d'un photomasque, procede de fabrication d'un masque a dephasage, et procede de fabrication d'un composant a semi-conducteur WO1997048019A1 (fr)

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PCT/JP1996/001574 WO1997048019A1 (fr) 1996-06-11 1996-06-11 Procede de fabrication d'un photomasque, procede de fabrication d'un masque a dephasage, et procede de fabrication d'un composant a semi-conducteur

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PCT/JP1996/001574 WO1997048019A1 (fr) 1996-06-11 1996-06-11 Procede de fabrication d'un photomasque, procede de fabrication d'un masque a dephasage, et procede de fabrication d'un composant a semi-conducteur

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009181147A (ja) * 2009-05-21 2009-08-13 Dainippon Printing Co Ltd 描画用基板の供給方法および基板選択装置

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JPH04344644A (ja) * 1991-05-22 1992-12-01 Hitachi Ltd マスクのパターンデータ作成方法および製造方法
JPH05249651A (ja) * 1992-03-05 1993-09-28 Fujitsu Ltd データ処理方法
JPH06110969A (ja) * 1992-09-29 1994-04-22 Nec Ic Microcomput Syst Ltd 集積回路のマスクパターン設計におけるエラー修正装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04155336A (ja) * 1990-10-18 1992-05-28 Fujitsu Ltd 図形処理装置
JPH04344644A (ja) * 1991-05-22 1992-12-01 Hitachi Ltd マスクのパターンデータ作成方法および製造方法
JPH05249651A (ja) * 1992-03-05 1993-09-28 Fujitsu Ltd データ処理方法
JPH06110969A (ja) * 1992-09-29 1994-04-22 Nec Ic Microcomput Syst Ltd 集積回路のマスクパターン設計におけるエラー修正装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009181147A (ja) * 2009-05-21 2009-08-13 Dainippon Printing Co Ltd 描画用基板の供給方法および基板選択装置

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