[go: up one dir, main page]

WO1997011485A1 - Dispositif a semiconducteur et son procede de fabrication - Google Patents

Dispositif a semiconducteur et son procede de fabrication Download PDF

Info

Publication number
WO1997011485A1
WO1997011485A1 PCT/JP1996/002591 JP9602591W WO9711485A1 WO 1997011485 A1 WO1997011485 A1 WO 1997011485A1 JP 9602591 W JP9602591 W JP 9602591W WO 9711485 A1 WO9711485 A1 WO 9711485A1
Authority
WO
WIPO (PCT)
Prior art keywords
film
copper
semiconductor device
gas
opening
Prior art date
Application number
PCT/JP1996/002591
Other languages
English (en)
Japanese (ja)
Inventor
Kenichi Takeda
Kenji Hinode
Hiroshi Miyazaki
Seiichi Kondo
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1997011485A1 publication Critical patent/WO1997011485A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53233—Copper alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a wiring made of copper or a copper alloy having low resistance and high reliability. It concerns the equipment and its manufacturing method.
  • wiring made of aluminum or aluminum alloy has been mainly used for wiring of large-scale integrated circuits (LSIs).
  • LSIs large-scale integrated circuits
  • aluminum does not have to have a low melting point (660 ° C) and has poor migration resistance, so aluminum is not.
  • wiring made of an anolymium alloy tends to cause accidents such as disconnection, and it is difficult to cope with high integration and high speed of LSI.
  • copper has a much higher melting point than aluminum (1,083 ° C) and low electrical resistivity (bulk value). Approximately 23) of aluminum is regarded as a promising wiring material for next-generation LSIs.
  • a groove having a predetermined shape is formed in an insulating film, and copper is embedded in the groove. and Tsu by the and this you remove excess copper that exist outside, how formed form a copper wiring having a predetermined shape have been proposed (KOKOKU 6 - 1 0 3 6 8 1) 0
  • a groove having a width of 0.25 to 8 ⁇ and a depth of 0. cm is formed by using a dry etching method.
  • CVD chemical vapor deposition
  • a 50-nm-thick titanium nitride film and a 0.5-m-thick copper film are sequentially formed on the entire surface by the method to fill the grooves, and the excess titanium nitride film and copper are removed.
  • the film is removed by a CMP (chemical mechanical polishing) method to form a copper wiring.
  • the copper film formed by the CVD method has high reliability due to the presence of significant concaves and convexes on the surface, which may cause cavities inside the copper wiring. It is difficult to form thin copper wiring by the above method.
  • the copper film since the copper film is heat-treated in a mixed gas atmosphere of oxygen and hydrogen, the copper film may be oxidized and the resistivity of the copper film may increase. In addition, mixed gases of oxygen and hydrogen can explode, and extreme care must be taken to implement them.
  • the purpose of the present invention is to solve the problems of the above-mentioned conventional method.
  • An object of the present invention is to provide a method for manufacturing a semiconductor device, which can easily form a copper wiring having a property without causing the above explosion.
  • an opening or a groove formed in an insulating film is filled with a film of copper and an alloy of an element which accelerates surface diffusion of copper. In this way, the wiring is formed.
  • the wiring according to the present invention is made of not only copper but also an alloy containing an element which accelerates the surface diffusion of copper, so that only copper is used.
  • the fluidity is remarkably improved, and the opening and the groove can be easily filled by the heat treatment at a much lower temperature. Therefore, compared to the case of using only copper, it is possible to fill the inside of the groove with a much smaller width, so wiring with a very small line width is required. It is possible to form the cavities, and there is no fear that the above cavities are generated inside the wiring.
  • Elements accelerating the above-mentioned surface diffusion of copper include lead, bismuth, soot, zinc, nitrogen, sulfur, indium, sodium, and gallium. , Talmium, iron and selenium, at least one selected from the group consisting of: Is set to 0.05% to 0.5% to obtain a favorable effect. These elements If the content is less than 0.05%, the effect of the present invention will be insufficient, and if it is more than 0.5%, the electrical resistance will increase. It is inappropriate for wiring of semiconductor devices.
  • a second insulating film having a second opening is interposed between the insulating film and the semiconductor substrate, and the second opening is electrically connected to the wiring. It can be filled with the conductive film. As a result, direct contact between the copper wiring and the semiconductor substrate is prevented, and the reliability of the semiconductor device is further improved.
  • the conductive film that fills the second opening may include tungsten, titanium, tantalum, niob, nonadium, nickel, and the like. And at least one selected from the group consisting of cobalts and alloys or compounds based on at least one of these. Can be used.
  • a tungsten film can be interposed between the wiring and the conductor film and the insulating film, whereby copper and silicon dioxide can be interposed. Interaction during the wiring is effectively prevented, and the reliability of the wiring is further improved.
  • an insulating film having an opening is formed on a semiconductor substrate, and an alloy film of an element having a function of accelerating the surface diffusion of copper and a copper is formed in the opening. Then, the alloy film formed on the portion other than the opening is removed to form the alloy film.
  • Elements that have the effect of accelerating the surface diffusion of copper include ship, bismuth, soot, zinc, nitrogen, sulfur, indium, sodium, and the like. Gallium, talium, iron and selenium can be used.
  • a first method of filling the opening with the alloy film is a method of forming an alloy film of copper and an element having an action of accelerating the surface diffusion of the copper, and then performing a heat treatment.
  • the above-mentioned alloy film can be formed by a sputtering method or a CVD (chemical vapor deposition) method, and the heat treatment is performed by hydrogen, helium, or aluminum. It can be performed in a gon, nitrogen or vacuum atmosphere.
  • a second method of filling the opening with the alloy film is to form a film by laminating a copper film and a film containing an element having an action of accelerating the surface diffusion of the copper.
  • This is a method of heat treatment.
  • the heat treatment can be performed in an atmosphere of hydrogen, helium, argon, nitrogen, or a vacuum.
  • a third method of filling the opening with the alloy film is to form, after forming a copper film, a gas containing an element having an action of accelerating the surface diffusion of the copper.
  • This is a method of heat treatment.
  • the above elements contained in the above gas are adsorbed on the surface of the above copper film, and then diffused into the copper film to form an alloy film.
  • the inside of the opening is filled with this alloy.
  • a gas selected from a group consisting of a gas containing lead, a sulfide gas, a halogen gas, a halogenide gas, and a fluoride gas is used as the above gas.
  • Hydrogen sulfide as the sulfide gas, fluorine, chlorine, bromine or iodine as the halogen gas, and the halogenated compound include sulfur fluoride, hydrogen fluoride, silicon fluoride, carbon fluoride, selenium fluoride, sulfur chloride, carbon chloride, silicon chloride or bismuth bromide. , Respectively.
  • the second heat treatment is performed in a second gas atmosphere not containing the above gas. Since the above-mentioned hydrogen sulfide and halogen gas contained in the wiring are removed, the resistance of the wiring is reduced, which is extremely preferable.
  • a gas selected from the group consisting of hydrogen gas, helium gas, argon gas and nitrogen gas is used. it can .
  • a second insulating film having a second opening is formed on the semiconductor substrate, and the inside of the second opening is formed by a conductive film.
  • the conductive film includes a group consisting of tungsten, titanium, tantalum, niob, vanadium, nickel, and copper. At least one selected from these, and at least one of the alloys or compound films composed mainly of at least one of them, can be used.
  • FIG. 1 (a) is a process diagram showing Example 1 of the present invention
  • FIG. 1 (b) is a process diagram showing Example 1 of the present invention
  • FIG. 1 (c) is a process diagram showing Example 1 of the present invention
  • FIG. 1 (d) is a process diagram showing Example 1 of the present invention
  • FIG. 2 is a diagram showing the dependency of the minimum embeddable wiring width and wiring resistivity on the amount of added lead.
  • FIG. 3 (a) is a process diagram showing a second embodiment of the present invention
  • FIG. 3 (b) is a process diagram showing a second embodiment of the present invention
  • FIG. 4 is a sulfide having a minimum embeddable wiring width. Figure showing dependence on hydrogen fraction
  • FIG. 5 (a) is a process diagram showing a third embodiment of the present invention
  • FIG. 5 (b) is a process diagram showing a third embodiment of the present invention
  • FIG. 5 (c) is a third embodiment of the present invention.
  • the process diagram shown in Fig. 6 is a curve diagram showing the relationship between the minimum line width that can be embedded and the number of lead atomic layers.
  • FIGS. 1 (a) to 1 (d) are process diagrams showing a first embodiment of the present invention.
  • a second opening is formed on a silicon substrate 100 on which a semiconductor element (not shown) is formed.
  • a second insulating film 200 made of a Si02 film having a thickness of 200 nm was formed.
  • a tungsten plug 300 is formed to fill the second opening, and then the opening 400 is formed. to form a thickness of 4 0 0 nm of S i 0 2 film or al na Ru insulating film 2 0 1 that Yusuke.
  • a 30 nm-thick tungsten film 310 and a 500 nm thick film are formed on the insulating film 201.
  • An nm-thick copper-lead alloy film (99% of copper, 1% of lead) 302 was sequentially formed by a well-known snottling method.
  • the tungsten film 30 1 formed in a region other than the opening 400 by using a well-known CMP method. Excluding copper alloy film 302 Then, a copper wiring 302 A was formed, and a semiconductor device was formed.
  • the same treatment was carried out by changing the lead content of the copper-copper alloy film 302 to produce several types of semiconductor devices.
  • the minimum width of the hole that can be embedded without the generation of cavities is 0.25 ⁇ m, and the added amount of lead is increased.
  • the width of the groove that can be filled without forming a cavity inside the wiring becomes narrower, and a wiring with a smaller line width can be formed. Has been confirmed.
  • the resistivity of the wiring consisting of copper-lead metal at room temperature increases with the amount of lead added. But the amount of added ship is 0.0
  • the resistivity of the wiring is 1.0.
  • the heat treatment is performed in a hydrogen atmosphere.
  • the heat treatment may be performed in a helium, argon, or nitrogen atmosphere, and these heat treatments may be performed.
  • the heat treatment can be performed in a vacuum without using gas.
  • the tungsten film 31 is provided immediately below the copper base metal film 302.
  • the present invention is not limited to the tungsten film, but is not limited to the tungsten film. It may be any one of a metal, a vanadium, a nickel, a knuckle, or a film of an alloy or a compound containing the same as a main component. Further, the method of forming these films may use not only the snorting method but also the CVD method.
  • the element which accelerates the surface diffusion of copper is This is an example using sulfur, and this embodiment will be described with reference to FIGS. 3 (a) and 3 (b).
  • a second opening is provided on a silicon substrate 100 on which a semiconductor element (not shown) is formed.
  • a tungsten layer is formed using a well-known selective growth method by a CVD method.
  • An unplug 300 was formed, and the second opening was filled.
  • a tungsten film having a thickness of 30 nm is formed.
  • a copper film 301 and a copper film 303 having a thickness of 500 nm and a film thickness of 500 nm by using a well-known sputtering method, hydrogen sulfide and hydrogen sulfide are formed. In a mixed gas atmosphere of hydrogen, a heat treatment was performed at 400 ° C. for 20 minutes.
  • the sulfur in the hydrogen sulfide is added to the copper film 303 to form an alloy film of copper and sulfur, and the copper film and the sulfur film are flown out. Filled with alloy film.
  • the tungsten film 301 formed in the region other than the first opening and the above-mentioned alloy film of copper and sulfur are etched.
  • the wiring was formed to form a wiring 303A made of alloy of copper and sulfur, thereby forming the semiconductor device shown in FIG. 3 (b).
  • a plurality of semiconductor devices were fabricated by changing the mixture ratio of hydrogen sulfide and hydrogen in the above heat treatment, and performing the other treatment in the same manner.
  • the heat treatment was performed using a mixed gas of hydrogen sulfide and hydrogen.
  • hydrogen was not used, and only hydrogen sulfide was used, and instead of hydrogen, the heat was used.
  • Lithium, argon or nitrogen may be used. Similar effects can also be obtained by using, instead of hydrogen sulfide, a gas containing an element that accelerates the surface diffusion of copper, such as fuzi gas, chlorine and chloride gas. It was obtained.
  • pure copper is used as a material for forming the wiring 303A made of a copper-sulfur alloy, but it is formed by adding a different element to copper. It is also possible to use copper alloys that have been used.
  • tungsten film 301 instead of the tungsten film 301 provided immediately below the copper film 303, titanium, tantalum, niob, nobdium, niobium are used. Either of nickel and copper, or a film made of an alloy or a compound containing the same as a main component may be used. Further, the method of forming these films 301 is not limited to the snortering method, and a CVD method may be used.
  • the feature is that the resistivity of copper wiring can be lower than when these elements are added to copper in advance.
  • the present embodiment is an example in which lead is used as an element for accelerating the surface diffusion of copper, and this embodiment will be described with reference to FIGS. 5 (a) to 5 (c).
  • FIG. 5 is a process diagram showing a third embodiment of the present invention.
  • a second opening is provided on a silicon substrate 100 on which a semiconductor element (not shown) is formed.
  • a second insulating film 200 made of a film is formed, and a tungsten * plug 300 is formed by a well-known selective growth method by a CVD method.
  • the opening of No. 2 was filled.
  • an insulating film 201 made of a silicon oxide film having a thickness of 400 nm and having an opening is formed, and a tungsten film having a thickness of 3 O nm is formed.
  • a copper film 301 having a thickness of 50 nm and a thickness of 50 O nm was sequentially formed on the entire surface by using a well-known sputtering method.
  • a thin film 304 having a thickness of one atomic layer was formed on the copper film 303 by a vacuum evaporation method.
  • a heat treatment is performed at 400 ° C. for 20 minutes to diffuse the lead film 304 into the copper film 303 to form a copper-lead alloy film and flow. Then, the inside of the opening was filled with this copper-shipped alloy film.
  • the tungsten film 301 and the copper alloy film formed in the region other than the above-described opening are removed by a known CMP method to form a wiring made of a copper-lead alloy 3
  • the semiconductor device shown in FIG. 5 (c) was formed by forming 0 3 A.
  • a plurality of semiconductor devices were prepared by changing the thickness of the above lead film 304 and processing the other parts in the same manner.
  • a lead film 304 is formed on the copper film 303 by adding one lead film. If the above heat treatment was performed after forming an atomic layer or more, it was possible to form a wiring by filling a groove having a width of 0.3 cm without generating a cavity.
  • the thickness of the lead film 304 on the copper film 303 is less than '1 atomic layer, the cavity can be buried without forming a cavity inside the wiring.
  • the width increased rapidly, and the minimum groove line width that could be buried without forming the lead film 304 was 1 im.
  • the wiring having a smaller line width than the conventional one can be formed inside the cavity. It was confirmed that they could be formed without generating phenomena.
  • a vacuum deposition method was used as a method for forming the lead film 304 on the surface of the copper foil 303.
  • lead such as an aqueous solution of sulfuric acid ship was used. It is also possible to use a method of immersing the copper film surface in a solution containing the same.
  • a lead film was formed on a copper film, but bismuth, tin, zinc, halogen, sulfur, zinc, sodium, and sodium were used instead of lead.
  • Gallium, tarium, iron, selenium, etc., or the surface of the copper film can be treated with hydrogen sulfide, fluoride gas, chlorine, etc.
  • similar effects can be obtained by exposure to chloride gas or the like.
  • the heat treatment is performed in a hydrogen atmosphere.
  • the heat treatment may be performed in a vacuum, and instead of the hydrogen, the heat treatment may be performed.
  • Platinum, argon or nitrogen gas may be used.
  • the resistance of the copper wiring is lower than the method of adding the different element to copper. You can do it.
  • a copper alloy is placed in a very narrow groove at a low temperature and a short time without oxidizing the copper wiring.
  • the wiring can be formed by embedding, and a highly reliable copper wiring can be obtained.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un dispositif à semiconducteur pourvu d'une interconnexion en alliage de cuivre présentant une largeur de ligne inférieure à celle des interconnexions traditionnelles en cuivre, une faible résistance et une grande fiabilité. L'invention concerne également un procédé de fabrication dudit dispositif à semiconducteur. Une ouverture (400) pratiquée dans un film isolant (201) formé sur un substrat semiconducteur (100) est obturée avec une interconnexion (302A) en alliage de cuivre et avec un élément qui accélère la diffusion superficielle du cuivre. Etant donné que l'interconnexion contient du cuivre ainsi que l'élément qui accélère la diffusion superficielle du cuivre, l'ouverture (400) présentant une largeur extrêmement réduite est obturée de façon extrêmement simple avec l'alliage de cuivre (302), et il est possible d'obtenir une interconnexion fine (302A) en alliage de cuivre d'une grande fiabilité.
PCT/JP1996/002591 1995-09-18 1996-09-11 Dispositif a semiconducteur et son procede de fabrication WO1997011485A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP23794595 1995-09-18
JP7/237945 1995-09-18

Publications (1)

Publication Number Publication Date
WO1997011485A1 true WO1997011485A1 (fr) 1997-03-27

Family

ID=17022795

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/002591 WO1997011485A1 (fr) 1995-09-18 1996-09-11 Dispositif a semiconducteur et son procede de fabrication

Country Status (1)

Country Link
WO (1) WO1997011485A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003517190A (ja) * 1998-06-30 2003-05-20 セミトウール・インコーポレーテツド ミクロ電子工学の適用のための金属被覆構造物及びその構造物の形成法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248538A (ja) * 1988-03-30 1989-10-04 Hitachi Ltd 半導体装置
JPH05267299A (ja) * 1992-03-19 1993-10-15 Hitachi Ltd 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01248538A (ja) * 1988-03-30 1989-10-04 Hitachi Ltd 半導体装置
JPH05267299A (ja) * 1992-03-19 1993-10-15 Hitachi Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003517190A (ja) * 1998-06-30 2003-05-20 セミトウール・インコーポレーテツド ミクロ電子工学の適用のための金属被覆構造物及びその構造物の形成法

Similar Documents

Publication Publication Date Title
US6143658A (en) Multilevel wiring structure and method of fabricating a multilevel wiring structure
KR100339179B1 (ko) 상호 접속 구조 및 그 형성 방법
US7851924B2 (en) Method of manufacturing semiconductor device, and semiconductor device
US7319071B2 (en) Methods for forming a metallic damascene structure
KR20070053636A (ko) 반도체 장치 및 반도체 장치의 제조 방법
JP2002075994A (ja) 半導体装置及びその製造方法
JP2007180407A (ja) 半導体装置およびその製造方法
JPH11186261A (ja) 半導体装置の製造方法
JPH07283219A (ja) 半導体装置および半導体装置の製造方法および半導体装 置の製造装置
JP2001176842A (ja) シリコン窒化膜のエッチング方法及び半導体装置の製造方法
JP2007059660A (ja) 半導体装置の製造方法および半導体装置
JP2002134612A (ja) 半導体装置及びその製造方法
JP5667485B2 (ja) 半導体装置の製造方法、及び半導体装置
TW201227826A (en) Method for manufacturing semiconductor device
JP2573621B2 (ja) 電気的相互接続部の製造方法
JP2000252278A (ja) 半導体装置およびその製造方法
JP4492919B2 (ja) 半導体装置の製造方法
WO1997011485A1 (fr) Dispositif a semiconducteur et son procede de fabrication
JP2007335578A (ja) 半導体装置及びその製造方法
JP4195432B2 (ja) 相互接続用の自己封止型銀合金
TWI281233B (en) A novel device structure having enhanced surface adhesion and failure mode analysis
JPH06204218A (ja) 半導体装置の製造方法
JPH1041298A (ja) 半導体装置及びその製造方法
JP3087692B2 (ja) 半導体装置の製造方法
CN107369645B (zh) 半导体结构的形成方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase