WO1997013193B1 - Instruction buffer organization method and system - Google Patents
Instruction buffer organization method and systemInfo
- Publication number
- WO1997013193B1 WO1997013193B1 PCT/US1996/015417 US9615417W WO9713193B1 WO 1997013193 B1 WO1997013193 B1 WO 1997013193B1 US 9615417 W US9615417 W US 9615417W WO 9713193 B1 WO9713193 B1 WO 9713193B1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- instruction
- variable
- length
- instructions
- length instructions
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims 4
- 230000008520 organization Effects 0.000 title 1
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000006243 chemical reaction Methods 0.000 abstract 1
Abstract
Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format. The instruction buffer circuit prepares the variable-length instructions for decoding by converting the instruction alignment from a memory alignment to an instruction alignment on the basis of the instruction length indication. The instruction buffer circuit also assists the preparation of variable-length instructions for decoding of multiple instructions in parallel by facilitating a conversion of the instruction length indication to an instruction pointer.
Claims
-50-
AMENDED CLAIMS
[received by the Internauonal Bureau on 3 April 1997 (03.04.97); original claims 3 and 11 amended; new claims 25 and 26 added; remaining claims unchanged (9 pages)] 1 An apparatus for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution compnsing an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for stonng predecode information corresponding to the vaπable- length instructions stored in each instruction storage element, a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable-length instruction, a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the vanable length instructions from the memory alignment to an instruction ahgnment, and designating the first instruction byte location of a vanable-length instruction, and a decoder circuit coupled to the instruction cache to receive the vanable-length instructions tn the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of vanable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of vanable-length instructions in parallel
2 An apparatus according to Claim 1 wherein the buffer circuit further compπses an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new vanable-length instructions as vanable-length instructions are decoded by the decoder circuit; and a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length
3 An apparatus according to Claim 1 wherein the buffer circuit further compnses. an instruction buffer coupled to the instruction cache including a multiple instruction byte storage for stonng a predefined number of bytes of the variable-length instructions, and a multiple-bit predecode element storage having the predefined number of bits corresponding to the predefined number of bytes instruction byte storage; and a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length and stonng the instruction length in an instruction byte storage -51-
4. An apparatus according to Claim 1 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; and a plurality of instruction multiplexers respectively coupled to the plurality of decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment.
5. An apparatus according to Claim 1 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; a plurality of instruction multiplexers respectively coupled to the plurality of decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment; and a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions, the program count being combined with the predecode information indicative of instruction length to designate the first instruction byte location of a variable-length instruction.
6. An apparatus according to Claim 1 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache; a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and an instruction lookahead logic circuit coupled to the instruction buffer, the program counter and the plurality of decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the decoders decode variable-length instructions in parallel.
7. An apparatus according to Claim 1 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache; a plurality of instruction multiplexers respectively coupled to the plurality of decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment; a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and an instruction lookahead logic circuit coupled to the instruction buffer, the plurality of instruction multiplexers, the program counter and the plurality of decoders, the instruction lookahead logic circuit for denving the first instruction byte location of a vanable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the decoders decode vanable-length instructions in parallel.
8 An apparatus according to Claim 7 wherein the instruction lookahead logic circuit further compnses- a circuit for determining whether the predecode information is valid based on the predecode information indicative of instruction length
9 An apparatus for receiving a plurality of vanable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution compπsing- an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the vanable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for stoπng predecode information corresponding to the vaπable- length instructions stored in each instruction storage element, a predecoder coupled to the instruction cache for accessing the vanable-length instmctions, assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a vanable-length instruction, and designating the variable-length instructions as first-type and second-type variable-length instructions based on the information indicative of instruction length, a buffer circuit coupled to the predecoder for holding the vanable-length instructions and the corresponding predecode information, converting the vanable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a vanable-length instruction; and a decoder circuit coupled to the instruction cache to receive the vanable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of first type decoders and a second type decoder, the first type decoders for receiving a plurality of first-type vanable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of first-type vanable-length instructions in parallel, the second type decoder for decoding a second-type vanable length instruction.
10 An apparatus according to Claim 9 wherein the buffer circuit further compnses- an instruction buffer coupled to the instrucuon cache for holding first-type and second-type vanable-length instructions and for continually reloading with new vanable-length instructions as vanable-length instructions are decoded by the decoder circuit; and a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length -53-
11. An apparatus according to Claim 9 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache including a multiple instruction byte storage for storing a predefined number of bytes of the variable-length instructions, and a multiple-bit predecode element storage corresponding to the predefined number of bytes instruction byte storage; and a predecode expansion circuit coupled to the instruction buffer for converting the predecode information indicative of instruction length to an instruction length and storing the instruction length in an instruction byte storage.
12. An apparatus according to Claim 9 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; and a plurality of instruction multiplexers respectively coupled to the plurality of first type decoders, the instruction multiplexers for converting the first-type variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment.
13. An apparatus according to Claim 12 wherein one instruction multiplexer of the plurality of instruction multiplexers is coupled to the second type decoder and coupled to one respective first type decoder.
14. An apparatus according to Claim 9 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache for holding the variable-length instructions and for continually reloading with new variable-length instructions as variable-length instructions are decoded by the decoder circuit; a plurality of instruction multiplexers respectively coupled to the plurality of first type decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment; and a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions, the program count being combined with the predecode information indicative of instruction length to designate the first instruction byte location of a variable-length instruction.
15. An apparatus according to Claim 14 wherein one instruction multiplexer of the plurality of instruction multiplexers is coupled to the second type decoder and coupled to one respective first type decoder.
16. An apparatus according to Claim 9 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache; a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and an instruction lookahead logic circuit coupled to the instruction buffer, the program counter and the plurality of first type decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the first type decoders decode variable-length instructions in parallel.
17. An apparatus according to Claim 9 wherein the buffer circuit further comprises: an instruction buffer coupled to the instruction cache; a plurality of instruction multiplexers respectively coupled to the plurality of first type decoders, the instruction multiplexers for converting the variable-length instructions in the instruction buffer from a memory alignment to an instruction alignment; a program counter coupled to the plurality of instruction multiplexers and supplying a program count representing an initial point for decoding instructions; and an instruction lookahead logic circuit coupled to the instruction buffer, the plurality of instruction multiplexers, the program counter and the plurality of first type decoders, the instruction lookahead logic circuit for deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the first type decoders decode variable- length instructions in parallel.
18. An apparatus according to Claim 17 wherein the instruction lookahead logic circuit further comprises: a circuit for determining whether the predecode information is valid based on the predecode information indicative of instruction length.
19. An apparatus according to Claim 9 further comprising: a branch target buffer coupled to the instruction cache and the buffer circuit, the branch target buffer for storing a plurality of target instructions, the branch target buffer and the instruction cache alternatively supplying variable-length instructions to the buffer circuit.
20. A method of receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution, comprising the steps of: receiving the plurality of variable-length instructions from the instruction source; storing the variable-length instructions in a plurality of instruction storage elements, each of the variable- length instructions being stored in one or more instruction storage elements in the memory alignment; -55- accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable-length instruction; storing predecode information corresponding to the variable-length instructions stored in a plurality of predecode storage elements corresponding to the plurality of instruction storage elements; holding the variable-length instructions and the corresponding predecode information in a buffer; converting the variable length instructions from the memory alignment to an instruction alignment; designating the first instruction byte location of a variable-length instruction; receiving the variable-length instructions in the instruction alignment at a plurality of decoders, each variable-length instruction beginning at the designated first instruction byte locations; and decoding the plurality of variable-length instructions in parallel.
21. A method according to Claim 20, further comprising the steps of: supplying a program count representing an initial point for decoding instructions; and deriving the first instruction byte location of a variable-length instruction based on the program count and the predecode information indicative of instruction length, the first instruction byte locations being rapidly derived so that the decoders decode variable-length instructions in parallel.
22. A method of receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution, comprising the steps of: receiving the plurality of variable-length instructions from the instrucuon source; storing the variable-length instructions in a plurality of instruction storage elements, each of the variable- length instructions being stored in one or more instruction storage elements in the memory alignment; accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable-length instruction; storing predecode information corresponding to the variable-length instructions stored in a plurality of predecode storage elements corresponding to the plurality of instruction storage elements; holding the variable-length instructions and the corresponding predecode information in a buffer; converting the variable length instructions from the memory alignment to an instrucuon alignment; designating the first instruction byte location of a variable-length instruction; designating the variable-length instructions as first-type and second-type variable-length instructions based on the information indicative of instruction length; receiving the variable-length instructions in the instruction alignment at a plurality of decoders including a plurality of first type decoders and a second type decoder, the first type decoders for receiving a plurality of first-type variable-length instructions, each variable-length instruction beginning at the designated first instruction byte locations; decoding the plurality of first-type variable-length instructions in parallel; and decoding a second-type variable length instruction. -56-
23. A computer system comprising: a memory subsystem which stores data and instructions; and a processor operably coupled to access the data and instructions stored in the memory subsystem, wherein the processor includes a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing die instructions for execution, the circuit including: an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable- length instructions stored in each instruction storage element; a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable- length instruction; a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel.
24. In a processor having an instruction cache and a decoder, an apparatus for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution, the apparatus being characterized in that the apparatus comprises: an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable- length instructions stored in each instruction storage element; a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable-length instruction; -57- a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instnicuons from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel.
25. A network server comprising: a superscalar processor including a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution including: an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a corresponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable-length instructions stored in each instruction storage element; a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable- length instruction; a buffer circuit coupled to the predecoder for holding the variable-length instructions and the conesponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel; a memory; a processor bus coupled between the memory and the superscalar processor; a local bus and an I/O bus; first and second bridges, respectively coupling the processor bus to the local bus and the local bus to d e I/O bus; and a LAN adapter coupled to one of the local bus and the I O bus. -58-
26. A network server comprising: a superscalar processor including a circuit for receiving a plurality of variable-length instructions arranged in a memory alignment from an instruction source and preparing the instructions for execution including: an instruction cache coupled to the instruction source and having a plurality of instruction storage elements and a conesponding plurality of predecode storage elements, each of the variable-length instructions being stored in one or more instruction storage elements in the memory alignment and the predecode storage elements for storing predecode information corresponding to the variable- length instructions stored in each instruction storage element; a predecoder coupled to the instruction cache for accessing the variable-length instructions and assigning predecode information indicative of instruction length to the instruction storage elements assuming each instruction storage element stores a first instruction of a variable- length instruction; a buffer circuit coupled to the predecoder for holding the variable-length instructions and the corresponding predecode information, converting the variable length instructions from the memory alignment to an instruction alignment, and designating the first instruction byte location of a variable-length instruction; and a decoder circuit coupled to the instruction cache to receive the variable-length instructions in the instruction alignment and the predecode information, the decoder circuit including a plurality of decoders for receiving a plurality of variable-length instructions, each beginning at the designated first instruction byte locations, and decoding the plurality of variable-length instructions in parallel; and a LAN adapter coupled to the superscalar processor.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP96935973A EP0853781B1 (en) | 1995-10-06 | 1996-10-03 | Instruction buffer organization method and system |
| AU73733/96A AU7373396A (en) | 1995-10-06 | 1996-10-03 | Instruction buffer organization method and system |
| DE69629709T DE69629709D1 (en) | 1995-10-06 | 1996-10-03 | COMMAND BUFFER STORAGE ORGANIZATION METHOD AND SYSTEM |
| JP9514324A JPH11510287A (en) | 1995-10-06 | 1996-10-03 | Instruction buffer configuration method and system |
Applications Claiming Priority (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US506995P | 1995-10-06 | 1995-10-06 | |
| US502195P | 1995-10-10 | 1995-10-10 | |
| US59376596A | 1996-01-26 | 1996-01-26 | |
| US593,765 | 1996-05-16 | ||
| US60/005,021 | 1996-05-16 | ||
| US60/005,069 | 1996-05-16 | ||
| US649,995 | 1996-05-16 | ||
| US08/649,995 US5819056A (en) | 1995-10-06 | 1996-05-16 | Instruction buffer organization method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1997013193A1 WO1997013193A1 (en) | 1997-04-10 |
| WO1997013193B1 true WO1997013193B1 (en) | 1997-05-15 |
Family
ID=27485443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US1996/015417 WO1997013193A1 (en) | 1995-10-06 | 1996-10-03 | Instruction buffer organization method and system |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US5819056A (en) |
| EP (1) | EP0853781B1 (en) |
| JP (1) | JPH11510287A (en) |
| AU (1) | AU7373396A (en) |
| DE (1) | DE69629709D1 (en) |
| WO (1) | WO1997013193A1 (en) |
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| US5438668A (en) * | 1992-03-31 | 1995-08-01 | Seiko Epson Corporation | System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer |
| US5386534A (en) * | 1992-10-27 | 1995-01-31 | Motorola, Inc. | Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value |
| US5689672A (en) * | 1993-10-29 | 1997-11-18 | Advanced Micro Devices, Inc. | Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions |
| US5659700A (en) * | 1995-02-14 | 1997-08-19 | Winbond Electronis Corporation | Apparatus and method for generating a modulo address |
-
1996
- 1996-05-16 US US08/649,995 patent/US5819056A/en not_active Expired - Lifetime
- 1996-10-03 EP EP96935973A patent/EP0853781B1/en not_active Expired - Lifetime
- 1996-10-03 AU AU73733/96A patent/AU7373396A/en not_active Abandoned
- 1996-10-03 WO PCT/US1996/015417 patent/WO1997013193A1/en active IP Right Grant
- 1996-10-03 DE DE69629709T patent/DE69629709D1/en not_active Expired - Lifetime
- 1996-10-03 JP JP9514324A patent/JPH11510287A/en active Pending
-
1998
- 1998-10-06 US US09/166,322 patent/US6141742A/en not_active Expired - Lifetime
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