[go: up one dir, main page]

WO1997013193B1 - Procede et systeme d'organisation pour tampon instruction - Google Patents

Procede et systeme d'organisation pour tampon instruction

Info

Publication number
WO1997013193B1
WO1997013193B1 PCT/US1996/015417 US9615417W WO9713193B1 WO 1997013193 B1 WO1997013193 B1 WO 1997013193B1 US 9615417 W US9615417 W US 9615417W WO 9713193 B1 WO9713193 B1 WO 9713193B1
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
variable
length
instructions
length instructions
Prior art date
Application number
PCT/US1996/015417
Other languages
English (en)
Other versions
WO1997013193A1 (fr
Filing date
Publication date
Priority claimed from US08/649,995 external-priority patent/US5819056A/en
Application filed filed Critical
Priority to EP96935973A priority Critical patent/EP0853781B1/fr
Priority to AU73733/96A priority patent/AU7373396A/en
Priority to DE69629709T priority patent/DE69629709D1/de
Priority to JP9514324A priority patent/JPH11510287A/ja
Publication of WO1997013193A1 publication Critical patent/WO1997013193A1/fr
Publication of WO1997013193B1 publication Critical patent/WO1997013193B1/fr

Links

Abstract

Des instructions en longueur variable sont préparées en vue du décodage et de l'exécution simultanés d'une pluralité d'instructions en parallèle par la lecture des instructions en longueur variable à partir d'une source d'instructions et de la détermination du point de départ de chaque instruction, de façon à présenter simultanément à un décodeur des instructions multiples en vue de leur décodage en parallèle. Dès qu'il a accédé aux instructions en longueur variable provenant d'une mémoire d'instructions, un prédécodeur dérive une information de prédécodage pour chaque octet d'instructions en longueur variable en déterminant pour celui-ci une indication de la longueur de l'instruction, en supposant que chaque octet est un octet code d'opération puisque le véritable octet code d'opération n'est pas identifié. Le prédécodeur associe une information de longueur d'instruction à chaque octet d'instructions. Les instructions et l'information de prédécodage sont fournies à un circuit tampon instruction dans un format aligné sur la mémoire. Celui-ci prépare les instructions en longueur variable en vue de leur décodage en convertissant l'alignement d'instruction provenant d'un alignement de mémoire en un alignement d'instruction sur la base de l'indication de la longueur de l'instruction. Le circuit tampon instruction participe également à la préparation des instructions en longueur variable en vue du décodage des instructions multiples en parallèle en facilitant la conversion de l'indication de la longueur d'instruction en un pointeur de programme.
PCT/US1996/015417 1995-10-06 1996-10-03 Procede et systeme d'organisation pour tampon instruction WO1997013193A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP96935973A EP0853781B1 (fr) 1995-10-06 1996-10-03 Procede et systeme d'organisation pour tampon instruction
AU73733/96A AU7373396A (en) 1995-10-06 1996-10-03 Instruction buffer organization method and system
DE69629709T DE69629709D1 (de) 1995-10-06 1996-10-03 Befehlspufferspeicher-organisationsverfahren und system
JP9514324A JPH11510287A (ja) 1995-10-06 1996-10-03 命令バッファ構成方法及びシステム

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US506995P 1995-10-06 1995-10-06
US502195P 1995-10-10 1995-10-10
US59376596A 1996-01-26 1996-01-26
US593,765 1996-05-16
US60/005,021 1996-05-16
US60/005,069 1996-05-16
US649,995 1996-05-16
US08/649,995 US5819056A (en) 1995-10-06 1996-05-16 Instruction buffer organization method and system

Publications (2)

Publication Number Publication Date
WO1997013193A1 WO1997013193A1 (fr) 1997-04-10
WO1997013193B1 true WO1997013193B1 (fr) 1997-05-15

Family

ID=27485443

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/015417 WO1997013193A1 (fr) 1995-10-06 1996-10-03 Procede et systeme d'organisation pour tampon instruction

Country Status (6)

Country Link
US (2) US5819056A (fr)
EP (1) EP0853781B1 (fr)
JP (1) JPH11510287A (fr)
AU (1) AU7373396A (fr)
DE (1) DE69629709D1 (fr)
WO (1) WO1997013193A1 (fr)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5884059A (en) * 1996-01-26 1999-03-16 Advanced Micro Devices, Inc. Unified multi-function operation scheduler for out-of-order execution in a superscalar processor
US6122729A (en) * 1997-05-13 2000-09-19 Advanced Micro Devices, Inc. Prefetch buffer which stores a pointer indicating an initial predecode position
JP3003782B2 (ja) * 1997-07-31 2000-01-31 日本電気株式会社 開発支援装置
US6170055B1 (en) * 1997-11-03 2001-01-02 Iomega Corporation System for computer recovery using removable high capacity media
US6122638A (en) * 1997-11-26 2000-09-19 International Business Machines Corporation Object-oriented processor and method for caching intermediate data in an object-oriented processor
SE9704476L (sv) 1997-12-02 1999-06-23 Ericsson Telefon Ab L M Utökad instruktionsavkodning
ATE297567T1 (de) * 1998-03-18 2005-06-15 Qualcomm Inc Digitaler signalprozessor zur reduzierung des zugriffswettbewerbs
US6961801B1 (en) * 1998-04-03 2005-11-01 Avid Technology, Inc. Method and apparatus for accessing video data in memory across flow-controlled interconnects
US7634635B1 (en) * 1999-06-14 2009-12-15 Brian Holscher Systems and methods for reordering processor instructions
US7089404B1 (en) 1999-06-14 2006-08-08 Transmeta Corporation Method and apparatus for enhancing scheduling in an advanced microprocessor
US6393446B1 (en) 1999-06-30 2002-05-21 International Business Machines Corporation 32-bit and 64-bit dual mode rotator
US6748589B1 (en) 1999-10-20 2004-06-08 Transmeta Corporation Method for increasing the speed of speculative execution
US6807623B2 (en) * 2000-07-27 2004-10-19 Matsushita Electric Industrial Co., Ltd. Data processing control system, controller, data processing control method, program, and medium
US6832307B2 (en) 2001-07-19 2004-12-14 Stmicroelectronics, Inc. Instruction fetch buffer stack fold decoder for generating foldable instruction status information
US7168067B2 (en) * 2002-02-08 2007-01-23 Agere Systems Inc. Multiprocessor system with cache-based software breakpoints
KR100518567B1 (ko) * 2003-04-15 2005-10-04 삼성전자주식회사 독출 동작과 기입 동작이 동시에 수행되는 메모리 셀어레이 구조를 가지는 집적 회로
US7134000B2 (en) * 2003-05-21 2006-11-07 Analog Devices, Inc. Methods and apparatus for instruction alignment including current instruction pointer logic responsive to instruction length information
US7665078B2 (en) * 2003-08-21 2010-02-16 Gateway, Inc. Huffman-L compiler optimized for cell-based computers or other computers having reconfigurable instruction sets
US7243170B2 (en) * 2003-11-24 2007-07-10 International Business Machines Corporation Method and circuit for reading and writing an instruction buffer
US20060155961A1 (en) * 2005-01-06 2006-07-13 International Business Machines Corporation Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor
US7769983B2 (en) 2005-05-18 2010-08-03 Qualcomm Incorporated Caching instructions for a multiple-state processor
US20070226454A1 (en) * 2006-03-01 2007-09-27 Marius Stoian Highly scalable MIMD machine for java and .net processing
US20080177979A1 (en) * 2006-03-01 2008-07-24 Gheorghe Stefan Hardware multi-core processor optimized for object oriented computing
JP4902854B2 (ja) * 2006-09-12 2012-03-21 パナソニック株式会社 動画像復号化装置、動画像復号化方法、動画像復号化プログラム、動画像符号化装置、動画像符号化方法、動画像符号化プログラム、及び動画像符号化復号化装置
US7644204B2 (en) * 2006-10-31 2010-01-05 Hewlett-Packard Development Company, L.P. SCSI I/O coordinator
US7711927B2 (en) * 2007-03-14 2010-05-04 Qualcomm Incorporated System, method and software to preload instructions from an instruction set other than one currently executing
US7818543B2 (en) * 2007-07-10 2010-10-19 Globalfoundries Inc. Method and apparatus for length decoding and identifying boundaries of variable length instructions
US7818542B2 (en) * 2007-07-10 2010-10-19 Globalfoundries Inc. Method and apparatus for length decoding variable length instructions
US8417730B2 (en) * 2008-04-14 2013-04-09 Objectif Lune Inc. Block compression algorithm
US7870160B2 (en) * 2008-04-14 2011-01-11 Objectif Lune Inc. Block compression algorithm
US8942490B2 (en) * 2008-07-08 2015-01-27 Yin-Chun Blue Lan Method of high performance image compression
US8103850B2 (en) * 2009-05-05 2012-01-24 International Business Machines Corporation Dynamic translation in the presence of intermixed code and data
CN102426516A (zh) * 2011-09-29 2012-04-25 杭州中天微系统有限公司 基于两级片上缓存的可变长度指令集的预解码装置
CN104781786B (zh) * 2012-12-26 2018-05-08 英特尔公司 使用延迟重构程序顺序的选择逻辑
US20140244932A1 (en) * 2013-02-27 2014-08-28 Advanced Micro Devices, Inc. Method and apparatus for caching and indexing victim pre-decode information
US9710278B2 (en) * 2014-09-30 2017-07-18 International Business Machines Corporation Optimizing grouping of instructions
US11500643B2 (en) * 2020-11-13 2022-11-15 Centaur Technology, Inc. Spectre fixes with indirect valid table

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3731283A (en) * 1971-04-13 1973-05-01 L Carlson Digital computer incorporating base relative addressing of instructions
US5131086A (en) * 1988-08-25 1992-07-14 Edgcore Technology, Inc. Method and system for executing pipelined three operand construct
US5101341A (en) * 1988-08-25 1992-03-31 Edgcore Technology, Inc. Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO
US5113515A (en) * 1989-02-03 1992-05-12 Digital Equipment Corporation Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer
JP2725450B2 (ja) * 1989-08-28 1998-03-11 日本電気株式会社 マイクロプロセッサ
US5185868A (en) * 1990-01-16 1993-02-09 Advanced Micro Devices, Inc. Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy
US5201056A (en) * 1990-05-02 1993-04-06 Motorola, Inc. RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output
CA2037708C (fr) * 1990-05-04 1998-01-20 Richard J. Eickemeyer Generateur universel d'instructions composees pour processeurs paralleles
JP2834289B2 (ja) * 1990-07-20 1998-12-09 株式会社日立製作所 マイクロプロセッサ
WO1992006426A1 (fr) * 1990-10-09 1992-04-16 Nexgen Microsystems Procede et appareil de decodage parallele d'instructions avec elements de consultation de prediction de branchement
JPH04156613A (ja) * 1990-10-20 1992-05-29 Fujitsu Ltd 命令バッファ装置
US5222244A (en) * 1990-12-20 1993-06-22 Intel Corporation Method of modifying a microinstruction with operands specified by an instruction held in an alias register
EP0498654B1 (fr) * 1991-02-08 2000-05-10 Fujitsu Limited Antémémoire à traitement des données d'instruction et processeur de données comprenant une telle antémémoire
JP3181307B2 (ja) * 1991-04-25 2001-07-03 株式会社東芝 命令処理装置
JP3441071B2 (ja) * 1991-07-08 2003-08-25 セイコーエプソン株式会社 マイクロプロセッサ及びデータ処理装置
GB2263985B (en) * 1992-02-06 1995-06-14 Intel Corp Two stage window multiplexors for deriving variable length instructions from a stream of instructions
GB2263987B (en) * 1992-02-06 1996-03-06 Intel Corp End bit markers for instruction decode
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5386534A (en) * 1992-10-27 1995-01-31 Motorola, Inc. Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value
US5689672A (en) * 1993-10-29 1997-11-18 Advanced Micro Devices, Inc. Pre-decoded instruction cache and method therefor particularly suitable for variable byte-length instructions
US5659700A (en) * 1995-02-14 1997-08-19 Winbond Electronis Corporation Apparatus and method for generating a modulo address

Similar Documents

Publication Publication Date Title
WO1997013193B1 (fr) Procede et systeme d'organisation pour tampon instruction
US5233696A (en) Microprocessor having precoder unit and main decoder unit operating in pipeline processing manner
US7493474B1 (en) Methods and apparatus for transforming, loading, and executing super-set instructions
EP0689128B1 (fr) Compression d'instructions d'un ordinateur
US6141742A (en) Method for reducing number of bits used in storage of instruction address pointer values
US5826054A (en) Compressed Instruction format for use in a VLIW processor
US5878267A (en) Compressed instruction format for use in a VLIW processor and processor for processing such instructions
DE69631778T2 (de) Flexible implementierung eines systemverwaltungsmodus in einem prozessor
US4532590A (en) Data processing system having a unique address translation unit
US4701842A (en) Method and apparatus for avoiding excessive delay in a pipelined processor during the execution of a microbranch instruction
EP0363222A2 (fr) Méthode et dispositif de distribution simultanée d'instructions à plusieurs unités fonctionnelles
US6009508A (en) System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis
CA1204218A (fr) Systeme de traitement de donnees avec dispositif de traduction d'adresses logiques en adresses physiques
US6131152A (en) Planar cache layout and instruction stream therefor
GB2225884A (en) Locating rom code in computer memory space
US5390311A (en) Method and apparatus for accessing microcoded instructions in a computer system
KR940011594B1 (ko) 공유 제어 기억부를 가진 멀티프로세서 제어기 및 그 동기화 방법
US5920713A (en) Instruction decoder including two-way emulation code branching
JPH03233630A (ja) 情報処理装置
US5752271A (en) Method and apparatus for using double precision addressable registers for single precision data
US6049897A (en) Multiple segment register use with different operand size
US20100115498A1 (en) Adaptive production of assembler
EP0945784A1 (fr) Dispositif et procédé de stockage de structures de données faisant appel aux pointeurs d'addresses
KR960024924A (ko) 애넥스 레지스터 파일용 식별비트 발생 방법 및 장치
US5155818A (en) Unconditional wide branch instruction acceleration