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WO1998031101A1 - Circuit logique combinant un circuit a transistors a canaux et un circuit cmos, et procede mettant en oeuvre cette combinaison - Google Patents

Circuit logique combinant un circuit a transistors a canaux et un circuit cmos, et procede mettant en oeuvre cette combinaison Download PDF

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Publication number
WO1998031101A1
WO1998031101A1 PCT/JP1998/000003 JP9800003W WO9831101A1 WO 1998031101 A1 WO1998031101 A1 WO 1998031101A1 JP 9800003 W JP9800003 W JP 9800003W WO 9831101 A1 WO9831101 A1 WO 9831101A1
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WO
WIPO (PCT)
Prior art keywords
logic circuit
circuit
node
gate
logic
Prior art date
Application number
PCT/JP1998/000003
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English (en)
Japanese (ja)
Inventor
Shunzo Yamashita
Kazuo Yano
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/633,053 external-priority patent/US5923189A/en
Priority claimed from JP00054897A external-priority patent/JP3625973B2/ja
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to US09/331,780 priority Critical patent/US6313666B1/en
Publication of WO1998031101A1 publication Critical patent/WO1998031101A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Definitions

  • the present invention relates to a small-area, high-speed, low-power-consumption logic circuit combining a pass transistor circuit and a CMOS circuit. Also, the present invention relates to a small-area, high-speed, low-consumption circuit combining a pass transistor circuit and a CMOS circuit from a logical function. The present invention relates to a method for synthesizing a power logic circuit.
  • pass transistor logic circuit which is one of the logic circuits
  • one transistor can have various logic functions. For this reason, pass transistor logic circuits are well-structured and all conventional CMOS logic circuits are replaced with pass transistor logic circuits to increase the scale, while significantly reducing the number of LSI transistors.
  • Many studies have been published with the aim of reducing the area and power consumption of LSI. C Among them, a binary decision graph (Binary Dececion on Diagram) was created from logical functions, and There is a method that replaces the node with a 2-input, 1-output, and 1-control input pass transistor selector and synthesizes a pass transistor logic circuit with the desired logic function.
  • a binary decision diagram is a node binary tree with two branches, called one and zero. Rather, it is a graphic representation of logical functions, and has the property that complex logical functions can be expressed simply. For this reason, this method has attracted attention as a method for synthesizing a compact pass transistor logic circuit having a target logic function with a small number of transistors.
  • a 2-input, 1-output pass transistor selector is an n-channel.
  • a method has been proposed in which a target pass transistor logic circuit is composed of field-effect transistors only, and a buffer inverter for reducing the delay time is inserted as necessary.
  • CMOS logic circuits have poor performance! ) Requires the same number of channel field effect transistors as n channel field effect transistors.
  • CMOS logic circuits have poor performance! ) Requires the same number of channel field effect transistors as n channel field effect transistors.
  • a pass transistor logic circuit synthesized by the method described in Reference 1 most of the circuit, except for the buffer inverter, can be composed only of high-performance n- channel field-effect transistors. .
  • a circuit that is smaller in area, delay time, and power consumption than conventional CMOS logic circuits and has superior i-life can be obtained.
  • Reference 2 proposes a method that further develops Reference 1. This method is characterized in that a pass transistor logic circuit is synthesized from a multi-stage BDD (hereinafter referred to as a multi-stage BDD).
  • a multi-stage BDD is created by the following procedure.
  • a multi-level BDD can express a logical function with fewer nodes than an ordinary BDD. For this reason, it is possible to synthesize a pass-transistor logic circuit with the desired logic function using fewer transistors than in Reference 1. And it is possible. Also, the number of nodes connected in series is reduced, so that the number of stages of the combined pass transistor circuit is reduced. For this reason, it is possible to synthesize a pass transistor logic circuit having a smaller delay time and a smaller area and lower power consumption than in Reference 1.
  • IEICE Technical Report VLD 955-1115, Vol. 95, No. 119, PP 1-6 (hereafter referred to as reference 3) states that pass transistors with low power consumption are used.
  • a method aimed at synthesizing a logic circuit has been proposed. In this method, as in Reference 2, a pass transistor logic circuit is synthesized from a multi-stage BDD, but by narrowing the buffer inverter for delay time improvement to the minimum necessary, a pass transistor logic circuit with even lower power consumption is used. Can be synthesized.
  • the pass transistor circuit is disclosed in Japanese Unexamined Patent Application Publication No. 1-12961 (published on May 22, 1989) and Japanese Unexamined Patent Application Publication No. 11-216622 (19989). Published on August 30), Japanese Unexamined Patent Application Publication No. 1-25619 (published on October 12, 1998), Japanese Unexamined Patent Application Publication No. (Published May 19, 5).
  • the present inventors made a BDD for some logic functions and actually synthesized pass transistor logic circuits by the methods described in literatures 2 and 3. As a result, for a certain logic function, we were able to synthesize a pass transistor logic circuit that has much less transistors than conventional CMOS logic circuits, and that has a small area, delay time, and low power consumption. For other logic functions, the area, delay time, and power consumption have turned out to be large.
  • CMOS logic circuit For example, if a simple two-input NAND logic is synthesized with a transistor logic circuit according to the methods described in Documents 1, 2, and 3, a circuit with six C1 transistors in Figure 4A is obtained. However, a CMOS logic circuit would be a simpler circuit with four transistors (C 2 in Figure 4A). Also, for the two-input NOR logic, pass transistor logic The circuit is a powerful six-transistor circuit (C3 in Figure 4A), and a CMOS logic circuit is a four-transistor circuit (C4 in Figure 4A).
  • the pass transistor selector circuit is not suitable for NAND logic or N0R logic, but is suitable for selector logic that selects a certain signal with another signal.
  • NAND logic and NOR logic are the basic circuits of CMOS circuits, and it can be said that CMOS circuits can be used to build logic circuits with better performance. In terms of power and power consumption, the pass transistor circuit can be smaller in both NAND logic and NOR logic.
  • Logic circuits are now designed in high-level languages such as (Ha r dwa re De scripti on Langu age). It is very important how the logic can be realized by a compact logic circuit.
  • the pass transistor circuit alone is not enough to create a logic circuit with excellent circuit characteristics.
  • a pass transistor circuit and a CM0S circuit can cooperate well within a single logic circuit. Need to make. It also provides a method for automatically synthesizing such a high-performance path transistor / CM0S coordination logic circuit in a computer system. This is extremely important for making high performance LSI chips with small area, small delay time and low power consumption.
  • the delay time may be slower depending on the logic that could reduce the number of transistors.
  • the inventors independently analyzed this and found that there were the following problems. That is, in the pass transistor logic circuit synthesized from the multi-stage BDD, a circuit having a configuration connected to a control input of a subsequent pass transistor selector via a certain buffer transistor selector and a buffer inverter can be formed. In this case, it was found that the delay time was inevitably slow because the buffer member and the inverter in the subsequent pass transistor selector were connected in series. In other words, this method of synthesizing a pass transistor logic circuit from a multistage BDD may not be practical due to the above-mentioned delay time problem when the delay time condition is severe. found.
  • An object of the present invention is to construct a conventional logic circuit composed only of pass transistors or only a CM ⁇ S by combining the advantages of a pass transistor circuit and a CMOS circuit for any kind of logic.
  • the purpose is to provide a method for automatic synthesis by using.
  • Another object of the present invention is to combine the advantages of the pass transistor circuit and the CMOS circuit for any type of logic by combining only the pass transistors from the conventional multistage BDD. Solves the problem of the delay time of the logic circuit, and reduces the delay time and the number of transistors.
  • the pass transistor has excellent circuit characteristics such as area, delay time, and power consumption. Is to provide a way.
  • Another object of the present invention is to provide a logic circuit which is more desirable in terms of area, or circuit characteristics such as delay time and power consumption, or a combination thereof, by a pass transistor
  • the purpose of the present invention is to provide a method for synthesizing and combining a path and a CM ⁇ S circuit.
  • the gate is controlled by a first input (I 1), and a gate is provided between a first operating potential point (VDD) and a first node (NP 1).
  • a first p-channel field-effect transistor (TP 1) connected to the source-drain path;
  • a second p-channel field effect whose gate is controlled by the second input (IN 2) and whose source-drain path is connected between the first operating potential point (VDD) and the first node (NP 1)
  • a first n-channel field effect in which the gate is controlled by a first input (IN 1) and a source / drain path is connected between a first node (NP 1) and a fourth node (NP 4)
  • a second n-channel whose gate is controlled by the second input (IN2) and whose source-drain path is connected between the fourth node (NP4) and the second operating potential point (GND)
  • a third p-channel field effect transistor having a gate controlled by a first node (NP 1) and a source / drain path connected between a first operating potential point (VDD) and a second node (NP 2) (TP 3)
  • a fourth channel field-effect transistor whose gate is controlled by a third node (NP3) and whose source-drain path is connected between the first operating potential point (VDD) and the first output (OUT1); TP 4)
  • Fig. 1 This is a logic circuit (Fig. 1) that includes a selector logic with Boolean processing and a transistor (TN4).
  • the gate is controlled by a 10th input (IN 10), and a gate between a first operating potential point (VDD) and a 10th node (NP 10) is connected.
  • the gate is controlled by the 10th input (IN10), and the first drain is connected between the 10th node (NP10) and the second operating potential point (GND).
  • the gate is controlled by the 10th input (IN10), and the source / drain path is connected between the 12th input (IN12) and the first node (NP11).
  • the gate of which is controlled by the first node (NP11) and the source-drain path is connected between the first operating potential point (VDD) and the first node (NP12).
  • a p-channel field-effect transistor (TP15) is connected between the first node (NP11) and the source-drain path.
  • the gate is controlled by the first node (NP11), and the source and drain paths are connected between the first node (NP12) and the second operating potential point (GND).
  • N-channel field-effect transistor (TN15) N-channel field-effect transistor
  • the gate is controlled by the 12th node (NP12), and the source-drain path is connected between the first operating potential point (VDD) and the 10th output (OUT10).
  • the gate is controlled by the first and second nodes (NP12), and the source and drain paths are connected between the tenth output (OUT10) and the third node (NP13).
  • 4 n-channel field effect transistors (TN1 4) A gate whose gate is controlled by a first input (IN 13) and a source-drain path connected between a first operating potential point (VDD) and a first output (OUT 10).
  • the gate is controlled by the 13th input (IN 13), and the first drain (source / drain path) is connected between the 10th output (OUT 10) and the second operating potential point (GND).
  • This is a logic circuit (Fig. 2) that includes selector logic with Boolean processing and has three n-channel field-effect transistors (TN13).
  • the gate is controlled by a twentieth input (IN 20), and a gate is connected between a first operating potential point (VDD) and a twentieth node (NP 20).
  • VDD first operating potential point
  • NP 20 twentieth node
  • the gate is controlled by the second input (IN 21), and the source-drain path is connected between the first operating potential point (VDD) and the twentieth node (NP 20).
  • a twentieth n-channel field-effect transistor in which the gate is controlled by the twentieth input (IN 20) and the source / drain path is connected between the twentieth node (NP 20) and the twenty-fourth node (NP 24) (TN20)
  • the gate is controlled by the 21st input (IN21) and the source / drain path is connected between the 24th node (NP24) and the second operating potential point (GND).
  • a second p-channel electric field whose gate is controlled by the 22nd input (IN22) and whose source-drain path is connected between the first operating potential point (VDD) and the 22nd node (NP22) Effect transistor (TP 22),
  • the gate is controlled by the 22nd input (IN 22), and the 22nd n-channel field effect in which the source / drain path is connected between the 22nd node (NP 22) and the second operating potential point (GND)
  • the gate is controlled by the 22nd node (NP22), and the 23rd n-channel field effect transistor (source and drain) is connected between the 23rd input (IN23) and the 23rd node (NP23).
  • TN23 The gate is controlled by the 22nd input (IN22), and the source and drain paths are connected between the 20th node (NP20) and the 23rd node (NP23).
  • the 25th p-channel whose gate is controlled by the 23rd node (NP23) and whose source-drain path is connected between the first operating potential point (VDD) and the 20th output (OUT20)
  • the gate is controlled by the 23rd node (NP23), and the source and drain paths are connected between the 20th output (OUT20) and the second operating potential point (GND).
  • NP23 23rd node
  • TN25 n-channel field-effect transistor
  • the present invention creates a binary decision graph or a multi-stage binary decision graph from a logical function, and creates a node. Create a pass transistor logic circuit by mapping to a 2 input 1 output 1 control input pass transistor selector.
  • the input power of one of the two inputs ⁇ The logic constant is fixed to 1 or 0, and it operates as NAND logic or NOR logic (or AND logic, OR logic)
  • CMOS gate such as NAND or NOR
  • the pass transistor selector with a logically equivalent CMOS gate such as NAND or NOR
  • calculate the values of the circuit characteristics such as area, delay time, and power consumption and replace it with the CMOS gate to obtain the desired circuit characteristics. If the value of is closer to the optimum, replace the pass transistor selector with a CMOS gate.
  • the above operation is tried for all the pass transistor selectors to synthesize a pass transistor ZCMOS cooperative logic circuit having a predetermined circuit characteristic that is optimal. Circuit characteristics used for such optimization include, for example, area, delay time, or power consumption, or any suitable combination thereof.
  • Another desirable aspect of the present invention is to create a BDD or a multi-stage BDD from a logical function, and to use only one of two branches (0 branch, 1 branch) among the nodes of the graph.
  • CMOS gates such as NAND and NOR that are logically equivalent to that node are mapped.
  • two-input one-output pass transistor selectors Matching is performed to synthesize a pass transistor ZCMOS cooperative logic circuit.
  • FIG. 1 shows a preferred embodiment of the present invention.
  • FIG. 2 shows another preferred embodiment of the present invention.
  • FIG. 3 shows another preferred embodiment of the present invention.
  • Figures 4A to 4C are comparison diagrams of the case where NAND logic and NOR logic are configured with pass transistor selectors and the case where CMOS logic is configured.
  • FIG. 5 shows a pass transistor / CMOS cooperative logic circuit according to a first embodiment of the present invention and a conventional circuit. The figure which compared the transistor logic circuit and the CMOS logic circuit.
  • FIG. 6 is a layout example of the pass transistor ZCMOS cooperative logic circuit according to the first embodiment of the present invention.
  • FIG. 7 is a schematic configuration diagram of a computer system for synthesizing a logic circuit and a logic circuit synthesis program used therein according to the second embodiment of the present invention.
  • FIG. 8 is a flowchart from the synthesis of a logic circuit to the manufacture of a semiconductor integrated circuit according to the second embodiment of the present invention.
  • FIG. 9 is a flowchart of the pass transistor ZCMOS cooperative logic circuit synthesis program of the second embodiment.
  • FIG. 10 is a circuit diagram of a CMOS logic circuit synthesized from the logic function of the second embodiment by a known method.
  • FIG. 11 is a diagram showing an example of a multi-stage binary decision diagram created by the binary decision diagram creation routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG.
  • FIG. 12 is a diagram showing a matching rule of the pass transistor selector.
  • FIG. 13 is a circuit diagram of a pass transistor logic circuit created from the multi-stage binary decision graph of FIG. 11 by the pass transistor mapping routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG.
  • FIGS. 148 to 14D are diagrams showing the pattern of the pass transistor selector which is converted to a CMOS gate when the pass transistor ZCMOS cooperative logic circuit is synthesized by the method of the present invention, and the conversion rules thereof.
  • FIG. 15 is a circuit diagram of an intermediate circuit created during the CMOS gate assignment routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG.
  • FIG. 16 is a circuit diagram of an intermediate circuit created during the CMOS gate assignment routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention shown in FIG.
  • FIG. 17 is a circuit diagram of a pass transistor / ZCMOS cooperative logic circuit synthesized when the area is given the highest priority in the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention in FIG.
  • Figure 18 is a circuit diagram of a logic circuit created by converting the CMOS gate to a pass transistor selector from the CMOS logic circuit of Figure 10.
  • FIG. 19 is a circuit diagram of the pass transistor ZCMOS cooperative logic circuit synthesized when the delay time is set to the highest priority in the pass transistor ZCM OS cooperative logic circuit synthesis program of the present invention in FIG.
  • Figure 20 shows both p-channel and n-channel
  • FIG. 3 is a circuit diagram of a pass transistor selector constituted by transistors of the following types.
  • Figure 21 shows the result of changing the cost from the area priority to the delay time priority in the pass transistor ZCMOS cooperative logic circuit synthesis program of the present invention.
  • Fig. 22 shows a logic circuit synthesized by the pass transistor ZCM ⁇ S cooperative logic circuit synthesis program of the present invention, a CMOS logic circuit and a pass transistor synthesized by an existing known method for one or two different logics. Diagram comparing area and power consumption with logic circuit.
  • FIG. 23 is a flowchart of a synthesis program for a pass transistor / CMOS cooperative logic circuit according to the sixth embodiment of the present invention.
  • FIG. 24 is a diagram showing an example of a BDD created by the pass transistor ZCMOS cooperative logic circuit synthesis program of the present invention in FIG. 23.
  • FIG. 25 is a circuit diagram of an intermediate circuit created in the middle of the pass transistor selector ZCMOS gate mapping routine of the pass transistor / CMOS cooperative logic circuit synthesis program of the present invention of FIG.
  • FIG. 26 is a circuit diagram of a pass transistor ZCMOS cooperative logic circuit synthesized by the pass transistor ZCMOS cooperative logic circuit synthesis program of the present invention in FIG.
  • FIG. 27 is a circuit diagram of a pass transistor logic circuit synthesized from the BDD of FIG.
  • FIG. A, b, and c in FIG. 5 show the logic given by the following logic functions, respectively, when the pass transistor ZCMOS cooperative logic circuit of the present invention is used, and when the conventional pass transistor logic circuit and the CM0S logic circuit are used.
  • FIG. 7 is a diagram comparing the cases where the configuration is made.
  • the inverter and the CMOS gate indicated by the simplified symbols in FIG. 5 are composed of the transistor circuit shown in FIG.
  • the pass-transistor ZCMOS cooperative logic circuit of the present invention is a circuit composed of an inverter I50, a pass-transistor selector S50, and a CMOS gate G50.
  • the conventional pass transistor logic circuit requires inverters 150 and 151 and pass transistor selectors S50 and S51.
  • a CMOS logic circuit requires inverters I52 and I54 and CMOS gates G50 to G53.
  • NAND logic and NOR logic that are not suitable for the pass transistor circuit must be formed by the pass transistor circuit (S51).
  • the selector logic that is not suitable for being configured by the CMOS circuit is also CM 0 S It must be composed of circuits (G51-G53).
  • the pass transistor / CMOS cooperative logic circuit of the present invention in a given logic, a part corresponding to the selector logic is assembled with a pass transistor selector (S50) suitable for the selector logic, and For the other NAND and NOR logic parts, it is possible to form circuits with CMOS gates (G50) suitable for them.
  • S50 pass transistor selector
  • G50 CMOS gates
  • the pass transistor logic circuit requires 14 transistors and the CMOS logic circuit requires 20 transistors, whereas the pass transistor / CMOS cooperative logic circuit of the present invention requires only 11 transistors to achieve the target. It can be seen that the circuit is capable of implementing logic functions and has excellent performance with small area and low power consumption.
  • the portion corresponding to the selector S51 and the inverter I51 of the pass-transistor logic circuit can be reduced to one CMOS gate G50.
  • the pass transistor logic circuit it is possible to reduce the delay time required for the inverter in the selector S51 ⁇ selector S51—buffer receiver I51 to the delay time of the CMO S gate G50 only. In monkey.
  • the pass transistor / CM ⁇ S cooperative logic circuit of the present invention is compared with the pass transistor logic circuit.
  • the delay time can be significantly reduced.
  • CMOS logic circuits do not. 5 1 to 05 3, 15 2 and 15 4
  • the path of the pass transistor / CMOS cooperative logic circuit of the present invention can be shortened to S 50 and 150, so that the pass transistor of the present invention / CMOS
  • the cooperative logic circuit has a smaller delay time.
  • FIG. 6 shows a layout example of the pass transistor / CMOS cooperative logic circuit of the present invention shown in FIG. 5A.
  • cell 1 corresponds to the NAND gate (G50) of the CMOS circuit
  • cell 2 corresponds to the pass transistor selector (S50).
  • the height h1 of cell 1 and the height h4 of cell 2 and cell 1 The width of the power lines (VDD and GND) of the cell] i 2 and h 3, and the width of the power lines (VDD and GND) of cell 2 h 5 and h 6, It becomes possible to actually produce a logic circuit that combines a pass transistor circuit and a CMOS circuit into one circuit. This is the same in the following embodiments.
  • the transistor 116 composed of the inverter 160, the pass transistor selector S60, and the CMOS gate G60 is used.
  • a circuit with the desired logic function can be constructed with the individual components.
  • the pass transistor logic circuit requires the inverters I60 and I61 and the pass transistor selectors S60 and S61, and requires 14 transistors.
  • a CMOS logic circuit requires inverters 16 2, 16 4, and CMOS gates G 60 to G 63, and requires 20 transistors. That is, also in this case, it can be seen that the pass transistor / CMOS cooperative logic circuit of the present invention has the best performance.
  • the portion corresponding to the selector S61 and the inverter I61 of the pass transistor logic circuit is a CMOS gate of 1 "" 3. Since the delay time can be reduced to 60, the delay time taken by the inverter in the selector S61 of the pass transistor logic circuit, the selector S61, and the buffer inverter I61 can be reduced by the delay time of only the CMOS gate G50. In particular, since the slow inversion in the selector S61 can be eliminated, the delay time can be significantly reduced as compared with the pass transistor logic circuit.
  • the path of the G61 to G63, 162, and I64 portions of the CMOS logic circuit is represented by S60 in the pass transistor Z CMOS cooperative logic circuit of the present invention.
  • I 60 the delay time of the pass transistor / CMOS cooperative logic circuit of the present invention is shorter.
  • the transistor 117 composed of the inverter 170, the pass transistor selector S70, and the CM gate G70 is used.
  • a circuit having a desired logic function can be configured.
  • a pass transistor logic circuit requires inverters I 70 and I 71 and a transistor selector S 70, S 71, and 14 transistors are required. is there.
  • a CMOS logic circuit requires inverters 172 and 174, CMOS gates G70 to G73, and 20 transistors. That is, also in this case, it can be seen that the pass transistor / CMOS cooperative logic circuit of the present invention has the best performance.
  • the path transistor / CM ⁇ S coordination logic circuit of the present invention is the smallest for the same reason as in FIGS.
  • the pass transistor ZCM0S cooperative logic circuit of the present invention has been described using simple logic as an example.
  • a high-performance pass transistor / CMOS coordination logic circuit having excellent circuit characteristics such as area, delay time, and power consumption for more complex logic is implemented by a computer system shown in FIGS. 7 and 8. A method for automatic synthesis will be described below.
  • the designer inputs a logic circuit specification 10 that describes a specification of a logic function of a target semiconductor integrated circuit.
  • the logic circuit specification 10 describes a logic function that describes the logic function of the circuit.
  • it describes target values of circuit characteristics such as the area, delay time, and power consumption of the circuit, and information on which circuit characteristics should be prioritized.
  • the pass transistor ZCMOS cooperative logic circuit synthesis program 100 peculiar to the present embodiment refers to the library 11 based on the information described in the logic circuit specification 10, and refers to the circuit such as the area, the delay time, and the power consumption.
  • the pass transistor / CMOS cooperative logic circuit 12 having the logic function of the logic circuit specification 10 is synthesized so as to satisfy the target value of the characteristic.
  • the automatic rate program 160 refers to the library 11 to determine an optimal layout for the logic circuit, and creates layout data 20.
  • the mask data creation program 170 determines a plurality of mask patterns for generating the synthesized logic circuit using the semiconductor integrated circuit technology in accordance with the layout data 20, and the mask data representing those mask patterns is determined. 2 Generates 1.
  • the semiconductor manufacturing apparatus 180 uses the mask data 21 to manufacture a semiconductor integrated circuit having a target logic function.
  • Each of the programs 100, 160, and 170 is executed on a different computer assigned to each. Of course, these programs can be executed on the same computer.
  • FIG. 7 shows a schematic structure of a pass transistor / CMOS cooperative logic circuit synthesis program 100 of the present invention and a computer system for executing the program.
  • This computer system includes an input device, for example, a keyboard, a central processing unit (CPU) 2, a display device (CRT) 3, a magnetic tape device 4, and a magnetic disk device 5 for storing a logic circuit synthesis program 100.
  • the program 100 includes a binary decision graph creation routine 110, a pass transistor selector mapping routine 120, and a CMOS gate assignment routine 130. This program is loaded from the magnetic disk device 5 to the CPU 2 and executed by the designer giving instructions from the keyboard 1.
  • the pass transistor ZCMOS cooperative logic circuit synthesized by the program 100 is displayed on the CRT 3 and passed to the automatic rate program 160 in FIG. 8 via the magnetic tape device 4 and the like.
  • a binary decision diagram is created, a portion of the pass transistor circuit synthesized by mapping the pass transistor selectors is found to have a better performance when changed to a CMOS circuit, and the portion is identified as a CMOS circuit. It is characterized by the fact that a pass-transistor ZCMOS cooperative logic circuit with better performance than the conventional pass-transistor-only logic circuit or CMOS-only logic circuit is synthesized. Specifically, one of the two inputs is fixed to a logical constant of 1 or 0, and a pass transistor selector operating as NAND logic or NOR logic (AND logic or OR logic) is logically connected.
  • CMOS logic circuit can be obtained from this logic function using an existing and well-known method. Is obtained, a circuit composed of G100 to G111 in FIG. 10 is obtained.
  • This routine 110 generates a BDD from the logic circuit specification 10.
  • the logical circuit specification 10 includes input variables and output variables corresponding to input signals and output signals of a logic circuit to be synthesized, and a logical function representing a logic function of the circuit.
  • a graph composed of the nodes N100 to N111 in FIG. 11 is created.
  • the number of nodes is reduced from that of a normal BDD by making nodes N 104 to N 109 common and squeezing them into a multi-stage.
  • the order of input variables when creating the graph is very important. Decisions can be made using decision graphing tools.
  • this routine converts each node of the BDD created by the BDD routine 110 into a pass transistor selector, inverter, etc. according to the type of node. To generate a path transistor logic circuit. Furthermore, an inverter for a buffer is inserted as needed.
  • the n-channel field-effect transistors T0 and T1 and the inverter Corresponds to the 2-input 1-output pass transistor selector SO composed of I0.
  • the control input of the pass transistor selector S 0 is assigned an input variable A corresponding to the node of the binary decision graph, and the input in 1 selected when the control input is 1 is connected to one branch. Assign the output of the node.
  • the output of the node connected to the 0 branch is assigned to the input i n 0 selected when the control input is 0.
  • the output of this node is the input variable A of that node. 1 is output when is 1, and 0 is output when input variable A is 0. That is, The input signal A may be directly connected to a subsequent circuit.
  • the output of this node is When one branch is connected to the logical constant 0 and the 0 branch is connected to the logical constant 1, as in a node N3 shown in FIG. 12C, the output of this node is When the input variable A is 1, 0 is output, and when the human variable A is 0, 1 is output. In other words, the input signal A can be inverted by the inverter and connected to the subsequent circuit.
  • a pass transistor logic circuit having the same logic function as the BDD is synthesized.
  • the pass-transistor logic circuit is synthesized from the binary decision diagram in Fig. 11, it consists of the pass transistor selectors S100 to S105 and the inverters I100 to I105 shown in Fig. 13. The synthesized transistor transistor logic circuit is synthesized.
  • 110, 1103, and 1105 are buffer buffers.
  • nodes N 102, N 103, and N 109 correspond to the b of the matching rule of FIG. 12
  • nodes N 106, N 107, N 1 1 1 corresponds to c in FIG.
  • Other nodes correspond to a in Fig. 12.
  • a pass transistor selector corresponding to the conversion patterns a to d in FIG. 14A is selected.
  • transistor selectors a to d shown in Fig. 14A one of the two inputs is fixed to the VDD or GND potential, that is, the logical constant 1 or the logical constant 0 is fixed.
  • NAND logic, and NOR logic or AND logic, OR logic.
  • these pass transistor selectors are converted to CMOS gates according to the conversion pattern of FIG. 14A.
  • the two-input NAND gate (Fig. 11B) and the two-input NOR gate (Fig. 14C) of the CM0S circuit indicated by simplified symbols are used.
  • Imba Overnight Fig. 14 D
  • Imba Overnight is composed of transistors T10 to ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ 13, ⁇ 20 to 2323, and ⁇ 30 to 31 at the transistor level.
  • the circuit area, delay time, and power consumption are calculated for the circuit after the inverter propagation and buffer insertion.
  • the cost of this circuit is calculated from the values of these circuit characteristics.
  • the cost of the circuit after conversion to the CMOS gate thus obtained is compared with the cost of the circuit before conversion to the CMOS gate previously obtained (process 133). If the circuit converted to the CMOS gate is more expensive, select the circuit converted to the CMOS gate. If the path transistor selector is more costly than the CMOS gate, return the circuit to the circuit before the conversion to the CMOS gate. In this way, the one with the better cost is selected from the CMOS gate and the pass transistor selector (process 134).
  • the above processing 1 3 1 to 1 3 4 is performed for all the pass transistor selectors corresponding to the conversion pattern of FIG.
  • the circuit characteristics are better when reconfigured with a CMOS gate. All pass transistor selectors are reconfigured with CMOS gates, and pass transistor / CMOS cooperative logic with excellent circuit characteristics such as area, delay time, and power consumption. Create a circuit.
  • a method for synthesizing a transistor ZCMOS cooperative logic circuit will be described.
  • the selector S 100 corresponds to “a” in the conversion pattern of FIG. 14 ⁇ , and thus is converted into a CMOS gate by the processing 13, and the intermediate circuit of FIG. 15 is created.
  • the pass transistor selector S101 is powerful, and as it is, the CMOS gate G100 is directly driven. Purchased.
  • Inverter 1101 is also introduced to adjust the polarity of this inverter 1108.
  • This inverter I 107 sandwiches the selector S 101 and is redundant with two inverters I 101 and I 102 connected in series. Since it is a simple inverter, it is removed by the inverter propagation process of process 132. In addition, the inverters 110, 110 and 106 are redundant and can be removed, and the pass transistor / CMOS cooperative logic circuit shown in FIG. 16 can be obtained.
  • cost is the same value as the value of this area.
  • pass transistor select Evening area before reassembled the S 1 00 to the CMOS gate one Bok is 1 1 6 4 ⁇ M 2, cost also becomes this value.
  • Table 1 shows the pass transistor ZCMOS cooperative logic circuit synthesized from the logic function of the second embodiment according to the present invention, and the CMOS logic circuit, the pass transistor logic circuit, and the logic created by replacing the CMOS logic circuit with the pass transistor selector. This is a table comparing the circuit area, delay time, and power consumption.
  • the pass-transistor ZCMOS cooperative logic circuit which was synthesized with the area first in this method, succeeded in reducing the area by nearly 40% compared to the logic circuit composed of CMOS alone (Fig. 10).
  • the delay time and power consumption have been reduced by 5% and 60%, respectively.
  • the desired pass transistor ZCMOS cooperative logic circuit with a small area is synthesized, although the delay time and power consumption are inferior. 'I'm sorry.
  • the pass transistor selector is best at not using NAND logic or NOR logic, but selecting a signal of a certain type with another signal. Selector logic.
  • NOR logic or AND logic, OR logic. Convert the pass transistor selector functioning as a CMOS gate into a CMOS gate and reconfigure the logic circuit.
  • a pass transistor selector is assigned to a part corresponding to the selector logic in a given logical function, and the other NAND logic, NOR logic (or AND logic, A CMOS gate can be assigned to the part corresponding to (OR logic).
  • NOR logic or AND logic,
  • a CMOS gate can be assigned to the part corresponding to (OR logic).
  • CMOS-only logic circuit For example, in the completely opposite procedure, a CMOS-only logic circuit is created, and then a portion of the CMOS gate that is suitable for a pass transistor selector is found, and that portion is identified as a pass transistor selector. Can be converted to a circuit that combines a pass transistor and a CMOS gate.
  • CMOS logic circuits all logic is composed of a combination of NAND logic and NOR logic (or AND logic or OR logic), so that a given logic function is suitable for pass transistor selection. Even if a selector logic part exists, it is difficult to find the corresponding part. In fact, when the CMOS logic circuit (FIG.
  • the pass transistor circuit shown in FIG. 18 is obtained.
  • all pass transistor selectors are used as NAND logic or NOR logic, one of the two inputs is fixed to VDD or GND potential, which is not suitable for the pass transistor selector. ing.
  • the circuit of Fig. 18 has a smaller area and a larger area than either a CMOS-only logic circuit (Fig. 10) or a logic circuit composed of pass transistors alone (Fig. 13). Delay time and power consumption for all circuit characteristics Inferior.
  • CMOS complementary metal-oxide-semiconductor
  • the pass transistor selector was configured only with n-channel field effect transistors.
  • a pass transistor selector configured with both p-channel and n-channel transistors (for example, as shown in FIG. 20)
  • the selector composed of the transistors T200 to T203 and the transistor I200 is also used in the same manner as in the second embodiment, and the pass transistor ZC M ⁇ S cooperative logic having a small area can be obtained by this method. It is possible to make a circuit. This is completely the same in the following examples.
  • An example of synthesizing a pass transistor / CMOS cooperative logic circuit by setting is described below.
  • a binary decision diagram is created by the binary decision diagram creation routine 110, and the pass transistor logic circuit of FIG. 13 is created by the past transistor mapping routine 120.
  • the pass transistor logic circuit shown in FIG. 13 first, the pass transistor selector S 100 is selected, and is converted into a CMOS gate by processing 13. Next, by processing 1 32, the buffer inverter is inserted into the output of the selector S101.
  • the delay time of the circuit is calculated instead of the area, and the value of the delay time becomes the cost of this circuit.
  • the delay time of the circuit (Fig. 13) before re-assembly to the CMOS gate is determined by the input F ⁇ selector S104 ⁇ selector S102—Inverter for buffer I103 ⁇ inverter in selector S100 1 ⁇ selector S 100 —The delay time of the path of the buffer inverter I 100.
  • the path corresponding to the circuit reassembled with a CMOS gate Fig.
  • the pass transistor selector of the succeeding stage is passed through a certain pass transistor selector and a buffer inverter.
  • a circuit can be constructed that is connected to the control input (S102—I103—S100 in FIG. 13).
  • the delay time is inevitably slowed because the buffer inverter and the inverter in the subsequent path transistor selector are connected in series.
  • the subsequent pass transistor selector can be successfully reconfigured with a CMOS gate as in this example, it is possible to omit the slow inversion in the transistor selector. Therefore, it is possible to make a logic circuit with a small delay time.
  • the delay time can be reduced by re-assembling a logic circuit having only a pass transistor into a pass transistor / CMOS cooperative logic circuit.
  • S104 and S105 correspond to the conversion pattern of FIG. 14A.
  • S105 is also converted into the CMOS gate. .
  • the reason is that, as in the case of S100, by converting the selector S105 to a CMOS gate, the slow inverter in the selector S105 can be eliminated, and the delay time can be further reduced. Because.
  • a pass transistor Z CMOS cooperative logic circuit shown in FIG. 19 is obtained.
  • the delay time was reduced by nearly 20% by synthesizing the pass transistor / CMOS cooperative logic circuit by this method, compared to the logic circuit composed of CMOS alone (Fig. 10). You have been successful. Also, compared with a logic circuit composed of a single pass transistor (Fig. 13), the delay time was successfully reduced by nearly 10%.
  • the power consumption of the circuit is calculated, and the value of the power consumption becomes the cost of the circuit.
  • the power consumption of the pass transistor ZC MOS cooperative logic circuit in FIG. 16 is calculated with reference to the library 11, the result is 143 ⁇ W MHz.
  • the power consumption of the circuit before conversion to the CMOS gate (Fig. 13) is 140 ⁇ W / MHz, so unlike the case of the second and third embodiments, the circuit is changed by the pass transistor selector. Cost is better to configure.
  • what is selected in process 134 is not a circuit reassembled with a CMOS gate, but a circuit configured with a pass transistor selector.
  • the remaining pass transistor selectors corresponding to the conversion pattern of FIG. 14A are S104 and S105. Unlike Embodiments 2 and 3, these two selectors are also configured by pass transistor selectors.
  • the circuit has lower power consumption and higher cost. For this reason, in this embodiment where power consumption is the highest priority, the pass transistor logic circuit of FIG. 13 is output as it is without being reassembled in the CMOS gate at all.
  • the power consumption of the pass transistor selector is lower than that of the CMOS gate, as shown in the comparison result of the pass transistor selector and the CMOS gate in Fig. 4A. Is also significantly smaller (less than half the CMOS gate). This is because, in the path transistor selector, the selector part occupying the majority of the selector circuit is composed of only n-channel field-effect transistors, and the number of p-channel field-effect transistors with lower performance is reduced, thereby improving the performance. This is because it is possible to suppress the total gate width of the transistors in the selector circuit without deteriorating, thereby reducing the power consumption.
  • the circuit operates as NAND logic or NOR logic (or AND logic, OR logic), which is considered to have better circuit performance when converted to a CMOS gate.
  • the pass transistor selector is converted to a CMOS gate, but the actual conversion to a CMOS gate depends on the circuit area, delay time, and power consumption by converting the pass transistor selector to a CMOS gate. Calculate the defined cost and judge whether the cost improves. For this reason, in the present method, as can be seen from the above Embodiments 2, 3, and 4, the cost defined by the area, delay time, and power consumption when synthesizing the pass transistor / CMOS cooperative logic circuit is changed.
  • FIG. 21 shows an example of a logical function (approximately 100,000 gates in terms of CMOS gate) larger than those of the second, third and fourth embodiments.
  • This is the result of synthesizing the pass transistor ZC MOS cooperative logic circuit by changing the priority and the power consumption priority y from 0 to 1 to change from the area top priority to the power consumption top priority.
  • the ratio of pass transistors suitable for reducing power consumption increases, and the pass transistor / CMOS cooperative logic circuit with priority on power consumption increases. It can be seen that the road is synthesized.
  • the pass transistor ZCMOS cooperative logic circuit synthesized by the present method it is possible to easily control the characteristics of the synthesized circuit by controlling the ratio of the pass transistor selector and the CMOS gate. is there. From these results, we can construct a pass-transistor ZCMOS cooperative logic circuit with actual large-scale logic. It is clear for the first time that the three circuit characteristics of area, delay time, and power consumption have the best balance when the area ratio of the pass transistor circuit is about 10 to 60% of the entire circuit. It has become.
  • the pass transistor selector is converted to a CMOS gate only when the circuit characteristics such as the circuit area, delay time, and power consumption are actually improved. For this reason, this method synthesizes a logic circuit consisting of a pass transistor alone for any logic function or a pass transistor / CMOS cooperative logic circuit with better circuit characteristics than a logic circuit consisting of only a CMOS gate.
  • Fig. 22 shows the synthesis of 12 types of logic (10000 to 10000 gates in terms of CMOS gate) larger than the logic of Fig. 21 by this method.
  • a binary decision diagram is created by the binary decision diagram creation routine 110 as in the second to fifth embodiments.
  • the pass transistor selector / CMOS gate mapping routine 300 allows the pass transistor Z CMOS cooperative logic circuit to be directly passed without passing through the pass transistor logic circuit. This is the point of composition.
  • the pass transistor selector ZCMOS gate mapping routine 300 will be described with reference to the BDD of FIG. 24 as an example.
  • the node N301 corresponds to b in FIG. 14A, so that it is mapped to the CMOS gate according to the conversion pattern in FIG. 14A (G3 in FIG. 25). 0 1, 1 3 0 0).
  • Other nodes N 300, N 302, N 3 03 is mapped at the bus transistor selector and the receiver according to the matching rule in FIG. 12 (S300, 1301 in FIG. 25).
  • the intermediate circuit of FIG. 25 is generated.
  • the inverters I300 and I301 are redundant inverters, so they are removed by processing 302, and finally the circuit of Fig. 26 is synthesized. .
  • a pass transistor logic circuit is created once, and then pass transistors operating as NAND logic or NOR logic (or AND logic or OR logic) are created.
  • the selector calculates the cost defined from circuit characteristics such as circuit area, delay time, and power consumption, and converts it to a CMOS gate if the cost increases. This guarantees that a logic circuit with excellent circuit characteristics can be synthesized in any case.
  • circuit characteristics such as circuit area, delay time, and power consumption, and the like each time, there is a disadvantage that it takes a little time to synthesize the circuit.
  • a pass transistor selector operating as NAND logic or NOR logic is synthesized by converting it to a CMOS gate.
  • the characteristics of the circuit are improved. Therefore, even if a pass-transistor ZCMOS cooperative logic circuit is created directly from a BDD without calculating costs as in the present embodiment, it can be expected that a logic circuit with excellent circuit characteristics can be synthesized. .
  • the pass transistor logic circuit is synthesized from the BDD of Fig. 24, the circuit of Fig. 27 is synthesized.
  • the pass transistor synthesized by this method ZCMOS cooperative logic circuit ( Fig. 25 shows that the number of transistors is smaller and that an excellent logic circuit can be synthesized.
  • the ratio of pass transistor selector and CMOS gate is changed, and the area and delay time of the synthesized pass transistor ZCMOS cooperative logic circuit are changed. It is possible to flexibly control circuit characteristics such as power consumption and the like.

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Abstract

L'invention porte sur un circuit logique à transistors à canaux formé à l'aide d'un chemin de décision par dichotomie à partir d'une fonction logique et par la mise en correspondance de chacun de ses noeuds avec un sélecteur de transistor à canaux sélectionnant deux entrées de commande à une entrée et à une sortie de façon à former un circuit logique présentant d'excellentes caractéristiques de circuit telles que surface, temps de retard et consommation d'énergie en combinant le circuit logique à transistors à canaux avec un circuit logique MOS. Dans le circuit logique à transistors à canaux, un sélecteur de transistors à canaux fonctionnant comme un circuit logique ET ou un circuit logique NI, l'une des deux entrées excluant une entrée de signal de commande fixe par rapport à une constante logique 1 ou 0, est remplacé par la grille CMOS d'un circuit ET, NI ou analogue à équivalence logique, et si la valeur de la caractéristique de circuit spécifiée est plus proche d'un optimum (par exemple, surface, temps de retard, consommation d'énergie ou autre valeur inférieure) dans le cas où elle est remplacée plutôt par la grille CMOS, le sélecteur de transistors à canaux est alors remplacé par la grille CMOS.
PCT/JP1998/000003 1996-04-16 1998-01-05 Circuit logique combinant un circuit a transistors a canaux et un circuit cmos, et procede mettant en oeuvre cette combinaison WO1998031101A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/331,780 US6313666B1 (en) 1996-04-16 1998-01-05 Logic circuit including combined pass transistor and CMOS circuit and a method of synthesizing the logic circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/633,053 US5923189A (en) 1995-04-25 1996-04-16 Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections
PCT/JP1996/001104 WO1996034351A1 (fr) 1995-04-25 1996-04-24 Procede de conception de circuits integres a semi-conducteurs et appareil de conception automatique
JP00054897A JP3625973B2 (ja) 1997-01-07 1997-01-07 論理回路、論理回路の合成方法、半導体装置の製造方法及び半導体集積回路装置
JP9/548 1997-01-07

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130856A (ja) * 1993-11-08 1995-05-19 Hitachi Ltd 半導体集積回路およびその製造方法
JPH07168874A (ja) * 1993-12-16 1995-07-04 Hitachi Ltd 論理回路の構成方法
JPH0851354A (ja) * 1994-08-08 1996-02-20 Hitachi Ltd パストランジスタ型セレクタ回路及び論理回路
JPH08321770A (ja) * 1995-05-25 1996-12-03 Sanyo Electric Co Ltd 論理回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130856A (ja) * 1993-11-08 1995-05-19 Hitachi Ltd 半導体集積回路およびその製造方法
JPH07168874A (ja) * 1993-12-16 1995-07-04 Hitachi Ltd 論理回路の構成方法
JPH0851354A (ja) * 1994-08-08 1996-02-20 Hitachi Ltd パストランジスタ型セレクタ回路及び論理回路
JPH08321770A (ja) * 1995-05-25 1996-12-03 Sanyo Electric Co Ltd 論理回路

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