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WO1998037583A1 - Procede pour fabriquer un dispositif a semi-conducteurs - Google Patents

Procede pour fabriquer un dispositif a semi-conducteurs Download PDF

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Publication number
WO1998037583A1
WO1998037583A1 PCT/JP1998/000599 JP9800599W WO9837583A1 WO 1998037583 A1 WO1998037583 A1 WO 1998037583A1 JP 9800599 W JP9800599 W JP 9800599W WO 9837583 A1 WO9837583 A1 WO 9837583A1
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WO
WIPO (PCT)
Prior art keywords
film
forming
layer
semiconductor
semiconductor device
Prior art date
Application number
PCT/JP1998/000599
Other languages
English (en)
Japanese (ja)
Inventor
Jiro Yugami
Yasushi Goto
Toshiyuki Mine
Toshihiko Itoga
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1998037583A1 publication Critical patent/WO1998037583A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/664—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a MISFET using a semiconductor or a metal material as a gate electrode.
  • a conventional polycrystalline structure was formed by forming a gate electrode into a laminated structure composed of polycrystalline silicon, a metal nitride film, and a metal film. Proposals have been made to reduce the resistance of the gate electrode while maintaining the reliability of the gate oxide film in the case of silicon gate.
  • titanium nitride is used as the barrier layer, and a metal film for lowering resistance, for example, a laminated film made of tungsten is used. It is difficult to select a chemical solution for cleaning the source / drain formation surface after electrode pattern application.
  • thermal oxidation treatment is performed to recover the dry etch damage received by the gate oxide film in the gate etch portion, titanium nitride becomes abnormally oxidized, and the gate electrode becomes phthalate, or the titanium nitride and the tungsten are removed. There is a problem that is peeled off.
  • the gate under the gate electrode is used.
  • the issue is how to recover the dry etch damage of the oxide film (measure against insulation failure).
  • an object of the present invention is to provide a method of manufacturing a semiconductor device having a low-resistance gate electrode and capable of improving reliability.
  • Another object of the present invention is to provide a method for manufacturing a semiconductor device which has a gate electrode of low resistance, is fine and can improve reliability.
  • Still another object of the present invention is to provide a method for manufacturing a semiconductor device suitable for high speed and high integration. Disclosure of the invention
  • a gate electrode formed of a conductive laminate in which the lowermost layer is a semiconductor layer and another conductive film containing a metal material (metal film) for reducing resistance is laminated on the semiconductor layer
  • the processing (pattern etch) of the lower layer the etching of the lowermost semiconductor layer is stopped halfway and left thinly, and the side wall of the upper conductive laminated film is covered with an insulating first side wall film.
  • the thinned lowermost semiconductor layer is etched, cleaned, and thermally oxidized to improve the reliability by recovering the dry etching damage of the gate oxide film in the gate edge portion.
  • Etching of the semiconductor film that will become the gate electrode is performed so that the semiconductor film remains, and an insulating film is provided on the sidewall of the etched semiconductor film to protect the gate edge from cleaning, wet etching, and the like. It is possible to do.
  • a gate electrode structure in which a gate electrode is formed by laminating a semiconductor film and a metal film it becomes possible to prevent abnormal oxidation of the metal film and separation of the metal films during thermal oxidation treatment.
  • the semiconductor film of the gate electrode is preferably etched so that the thickness of the semiconductor film remains at least 5 nm.
  • a gate electrode in which a semiconductor film and a metal film are stacked it is not always necessary to stop the etching of the semiconductor film in the middle, and the gate electrode is formed on the side wall of the gate electrode, for example, at the interface between the semiconductor film and the metal film.
  • the etching of the gate electrode may be stopped, and an insulating film may be formed on the side wall of the etched film.
  • a first impurity layer is formed in the semiconductor substrate in a self-aligned manner with respect to the first side wall film.
  • a groove having a desired depth is formed in a selected area of the main surface of the semiconductor substrate, and an insulating film is formed on the main surface of the semiconductor substrate including the groove.
  • the present invention it is possible to easily perform a process of recovering damage to a gate oxide film in a metal-contaminated ⁇ gate-etched portion) after processing the gate electrode, which is a problem when forming a gate electrode having a laminated structure including a metal.
  • the gate electrode resistance can be drastically reduced without increasing the junction leakage current due to metal contamination and without deteriorating the reliability of the gate oxide film.
  • the use of the SAC and the group isolation enables a miniaturized MOSFET structure to be achieved and a highly integrated semiconductor device to be obtained.
  • FIG. 1 is a fragmentary cross-sectional view showing a manufacturing step of a semiconductor device according to one embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 1;
  • FIG. 3 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 2;
  • FIG. 4 is a fragmentary cross-sectional view following FIG. 3 showing the semiconductor device manufacturing process.
  • FIG. 5 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 4;
  • FIG. 6 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 5;
  • FIG. 5 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 5;
  • FIG. 5 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 5;
  • FIG. 5 is a fragmentary cross-section
  • FIG. 7 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. FIG. 8 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG.
  • FIG. 9 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG.
  • FIG. 10 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 9
  • FIG. 11 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 1.0.
  • FIG. 12 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 11
  • FIG. 13 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 12;
  • FIG. 12 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 12;
  • FIG. 14 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 13;
  • FIG. 15 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 14;
  • FIG. 16 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 15;
  • FIG. 17 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 16;
  • FIG. 18 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 17;
  • FIG. 19 is a fragmentary cross-sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention.
  • FIG. 20 is a semi-continuation of Figure 19 It is principal part sectional drawing which shows the manufacturing process of a body device.
  • FIG. 21 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 20;
  • FIG. 22 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 21;
  • FIG. 23 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG.
  • FIG. 24 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device, following FIG.
  • FIG. 25 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 24.
  • FIG. 21 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 20
  • FIG. 22 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 21
  • FIG. 23 is a cross-sectional
  • FIG. 26 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 25;
  • FIG. 27 is a cross-sectional view of a principal part showing a manufacturing step of a semiconductor device, following FIG. 26.
  • FIG. 28 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 27.
  • FIG. 29 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG.
  • FIG. 30 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 29.
  • FIG. 31 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 30;
  • FIG. 30 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 30;
  • FIG. 32 is a cross-sectional view of a principal part showing a manufacturing step of a semiconductor device, following FIG.
  • FIG. 33 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 32.
  • FIG. 34 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 33.
  • FIG. 35 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device, following FIG. FIG. 36 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 35; BEST MODE FOR CARRYING OUT THE INVENTION
  • FIGS. 1 to 18 A first embodiment of the present invention will be described with reference to FIGS. 1 to 18.
  • a selective oxide film 102 for isolation is formed on a P-type single crystal Si substrate 101 by a normal selective oxidation method (LOCOS technology). I do.
  • This selective oxide film is formed to a thickness of, for example, 30 Onm.
  • a gate oxide film 103 having a thickness of about 5 nm was formed on the surface of the Si substrate 101 partitioned by the selective oxide film by a thermal oxidation method.
  • a 5 nm thick Si (polycrystalline silicon) film 104 is formed on the gate oxide film 103 by low pressure chemical vapor deposition.
  • a 20 nm-thick titanium nitride film 105 as a Si film 104 barrier layer is deposited by sputtering.
  • a low-resistance metal material having a high melting point that can withstand heat treatment for example, a tungsten film 106 is deposited on the titanium nitride film 105 to a thickness of 100 nm by sputtering.
  • a silicon nitride film 107 having a thickness of 150 nm is formed on the surface of the tungsten film 106. It is formed by low pressure chemical vapor deposition.
  • the resist 108 is patterned by a lithography technique.
  • the silicon nitride film 107, the tungsten film 106, and the titanium nitride film 105 were sequentially processed by dry etching using the resist 108 as a mask.
  • the lowermost Si film 104 On the other hand, etching of about 20 nm was performed, and after removing the resist mask, the shape shown in FIG. 4 was obtained.
  • cleaning with an organic cleaning solution is performed for the purpose of removing contaminants such as dry etching residues.
  • a silicon nitride film 109 having a thickness of 10 to 20 nm is deposited by low pressure chemical vapor deposition.
  • the silicon nitride film is formed on the polycrystalline silicon film 104 and on the side walls of the gate, but the polycrystalline silicon film is oxidized to form an oxide film to protect the gate edge portion. You may.
  • the cap layer patterned by performing anisotropic etching by dry etching technology.
  • the first insulating side wall coating 11 made of, for example, oxidation-resistant silicon nitride is formed on the side walls of (107) and the gate electrodes (106, 105, and a part of 104). 0, a so-called side wall film is formed.
  • a gate electrode is formed by completely patterning the Si film 104 using the cap layer and the insulating side wall film 110 of the side wall as a mask.
  • the oxide film 103 is removed by cleaning with a mixed solution of ammonia and hydrogen peroxide and wet etching with a dilute hydrofluoric acid aqueous solution.
  • the oxide film 103 is slightly etched.
  • the cleaning means usually used in an LSI process including a hydrofluoric acid aqueous solution treatment is made of metal. It can be used while avoiding problems such as elution of water.
  • the thermal oxide film 1 1 1 is Ri by the thermal oxidation in a dry ⁇ 2 atmosphere was 5 nm grown on the substrate.
  • the thermal oxidation at this time since the titanium nitride 105 and the tungsten film 106 are covered with the first insulating sidewall film 110 and the cap layer 107 which are oxidation-resistant, Since the material exposed to the silicon nitride film and silicon is limited to silicon nitride film and silicon, it can be easily performed without the problem of blistering and peeling as in the conventional case described above.
  • arsenic ions are implanted by ion implantation to match the first insulating side wall film 110 to form a first N-type impurity layer 112. I do.
  • the ion implantation energy is 15 KeV
  • the implantation concentration is 2 ⁇ 10 13 atoms / cm 2 .
  • a silicon nitride film 113 having a thickness of 50 to 100 nm is deposited by low pressure chemical vapor deposition.
  • a second insulating sidewall film 114 is obtained by performing anisotropic dry etching.
  • a second N-type impurity layer 115 is formed by implanting phosphorus ions by ion implantation in alignment with the second insulating side wall film 114.
  • the ion implantation energy is 25 to 30 KeV, and the implantation concentration is 5 ⁇ 10 14 atomscm 2 . Therefore, the second N-type impurity layer 115 is formed as a contact region deeper than the first N-type impurity layer 114.
  • the SiO 2 insulating film 1 serving as an interlayer insulating film between wirings was formed. 16 is formed by the plasma CVD technique. This SiO 2 -based insulating film 116 has a thickness of about 300 nm.
  • a resist 117 is patterned on the SiO 2 -based insulating film 116 by using a lithography technique.
  • SAC Se1fA1ign Contact
  • a conductor layer of aluminum and silicon was used as a conductor layer on the opening and on the top of the Si 2 -based insulating film 116 by a Snotter method. Is deposited to a thickness of 200 to 250 nm. For this conductive layer, a refractory metal such as tungsten or a refractory metal silicide can be applied.
  • the conductive layer 118 is processed according to a desired wiring pattern by using lithography and dry etching techniques to form a wiring layer 119.
  • the conductive layer 118 can be formed as a plug electrode (electrode structure embedded in the opening) to be a structure optimal for a multilayer wiring structure having flattening.
  • the gate electrode structure is a polycrystalline silicon / titanium nitride (barrier layer of polycrystalline silicon and tungsten) Z tungsten from the lower layer.
  • other gate electrode structures such as polycrystalline silicon non-crystalline silicon silicide (metal silicide film) and polycrystalline silicon Z nitride titanium nitride (metal nitride film) are used.
  • metal silicide film When forming polycrystalline silicon Z tungsten silicide (metal silicide film), after forming the polycrystalline silicon film, a metal film made of tungsten is deposited on the polycrystalline silicon film. Then, by performing the heat treatment, a tungsten silicide (metal silicide film) can be easily formed.
  • Example 1 a selective oxidation method (LOCOS technology) was employed as an isolation region for separation between a plurality of MOS FETs (elements).
  • LOCOS technology a selective oxidation method
  • a bird's beak is generated at the end of the selective oxide film, and it is a problem to miniaturize the element, particularly to obtain a MOSFET having a uniform gate oxide film of 5 nm or less.
  • the second embodiment shown in FIGS. 19 to 34 has a thickness of 10 nm or less, In particular, it is easy to obtain a MOS FET having a gate oxide film with a thickness of 3 to 5 nm, and it solves the conventional problems.
  • the present embodiment is a method of manufacturing a semiconductor device in the case where the groove isolation technology is used as the isolation.
  • a thermal oxide film 202 with a thickness of 1 O nm is formed on the silicon substrate 201, and a silicon oxide with a thickness of 150 nm is formed on the thermal oxide film 202.
  • a nitride film 203 is formed.
  • a resist 204 for forming an isolation is buttered by a lithographic technique.
  • the silicon nitride film 203, the thermal oxide film 202, and the silicon substrate 201 are etched by dry-etching technology using the resist as a mask.
  • a groove (depth about 0.3111) is formed in the portion where the solution is to be formed.
  • the silicon nitride film 203 is flattened as a polishing stopper using a so-called CMP (Chemical Mechanical Polishing) technique. Groove isolation is obtained by chemical modification. In this case, a parse beak unlike the above embodiment is not formed.
  • CMP Chemical Mechanical Polishing
  • the group isolation (G (Roove Isolation)
  • a gate oxide film 207 having a thickness of about 3 to 5 nm is formed on the surface of the Si substrate 201 partitioned by the GI by a thermal oxidation method.
  • a 50 nm thick Si (polycrystalline silicon) film 20 was formed on the good oxide film 207 by a low pressure chemical vapor deposition method.
  • Form 8 a titanium nitride film 209 having a thickness of 200 nm and a tungsten film 210 having a thickness of 100 nm are deposited by a sputtering method. Then, a silicon nitride film 211 having a thickness of 150 ⁇ m is formed on the surface of the tungsten film 210 by a low pressure chemical vapor deposition method. Then, the resist 2 12 is patterned by lithography technology.
  • the silicon nitride film 211, the tungsten nitride film 210, and the titanium nitride film 209 were processed by dry etching using the resist 212 as a mask.
  • the underlying Si film 208 was also etched by about 20 ⁇ m to obtain the shape shown in FIG. 26 after removing the resist mask.
  • cleaning with an organic cleaning solution was performed to remove contaminants such as dry etching residues.
  • a silicon nitride film is formed on the side walls of the cap layer (211) and the gate electrodes (parts of 210, 209 and 208).
  • a first insulating sidewall film 2 13 was formed.
  • the first insulating side wall film 2 13 is formed by first depositing a silicon nitride film having a thickness of 10 to 20 nm by low pressure chemical vapor deposition as in Example 1, and then performing dry etching. It is formed by performing anisotropic etching by technology.
  • the cap layer (211) and The gate electrode was formed by completely patterning the Si film 208 using the first insulating sidewall film 213 as a mask. Further, the oxide film 207 was removed by washing with a mixed solution of ammonia and hydrogen peroxide and dilute hydrofluoric acid aqueous solution.
  • the cleaning means usually used in an LSI process such as a hydrofluoric acid aqueous solution treatment is used to elute metal. Can be used while avoiding such problems.
  • a thermal oxide film 2 14 was placed on the substrate at 850 ° C and a dry O 2 atmosphere for the purpose of modifying the gate oxide film in the gate portion. 5 nm was grown.
  • the modification treatment by the thermal oxidation method can be easily performed because the material exposed on the surface is limited to the silicon nitride film and silicon.
  • arsenic ions are implanted by ion implantation technology to form a first N-type impurity layer 216 in alignment with the first insulating side wall film 213. did.
  • the ion implantation energy is 15 KeV
  • the implantation concentration is 2 ⁇ 10 13 atoms / cm 2 .
  • a 50 to 100 nm thick silicon nitride film 113 is deposited by low pressure chemical vapor deposition, followed by anisotropic dry etching.
  • a second side wall coating 2 15 was obtained.
  • a second N-type impurity layer 217 was formed by implanting phosphorus ions by ion implantation in alignment with the second insulating side wall film 215. .
  • the ion implantation energy is 25 to 30 KeV, and the implantation concentration is 5 ⁇ 10 1 atomscm 2 . Therefore, the second N-type impurity layer 2 15 It is formed as a contact region deeper than the N-type impurity layer 2 13 of FIG.
  • an SiO 2 -based insulating film 218 serving as an interlayer insulating film between wirings is formed by a plasma CVD technique. did.
  • the Si 2 -based insulating film 2 18 has a thickness of about 3101111.
  • a resist 219 was patterned on the SiO 2 -based insulating film 218 by using a lithography technique.
  • This conductor layer can be made of a high-melting-point metal such as tungsten or a high-melting-point metal silicide, as in the above embodiment.
  • the conductor layer 220 is processed using a lithography and dry etching technique according to a desired wiring pattern to form a wiring layer 221.
  • the final Passhibeshiyo down film coated perform by Uni selection Etsuchingu that this passivation emission film bonding pad exposed c
  • bonding is performed on the exposed bonding pad to connect to an external lead, and finally, the semiconductor device is sealed with resin. Obtained. According to the second embodiment described above, it is possible to obtain a semiconductor device manufacturing method suitable for high speed and high integration by lowering the resistance of the gate electrode as well as improving the reliability.
  • the gate electrode structure is polycrystalline silicon / titanium nitride tungsten from the lower layer, but other gate electrode structures and gate contact structures due to factors such as gate resistance and wiring contact.
  • the contamination layer of the diffusion layer related to the processing of the metal electrode can be formed by the same procedure as in the present embodiment. It is possible to recover gate oxide film damage in the Toetu area. Therefore, a combination of the stacked electrode having the silicon film as the lowermost layer and the sidewall protection method described in the present embodiment is within the scope of the present invention.
  • one MOS FET was used as an example.
  • the formation of an isolation region in a semiconductor substrate is disclosed. Therefore, it is apparent that the present invention can be applied to the case of obtaining a semiconductor device having a plurality of MOS FETs as constituent elements, in general, a highly integrated semiconductor device called a semiconductor integrated circuit device. Specifically, it is useful when applied to the formation of MOS FET which constitutes a DRAM memory cell.
  • the present invention relates to a dynamic cylinder having a MOSFET as a constituent element. It is used for manufacturing semiconductor devices such as memory access memories.

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  • Chemical Kinetics & Catalysis (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Lors du façonnage d'une électrode de grille stratifiée contenant un matériau métallique, de mince revêtement de chant isolants sont disposés sur les sections de chant d'un film stratifié conducteur supérieur, tandis qu'une partie d'une couche de silicium polycristallin constituant l'électrode de grille de la couche la plus basse est laissée. Ultérieurement, la couche de polysilicium laissée est éliminée par attaque, nettoyée avec un produit chimique, et soumise à un traitement thermique visant à la reconstituer après la déterioration due à la gravure à sec. Par conséquent, la résistance de l'électrode de grille peut être notablement réduite sans provoquer l'augmentation des courants de fuite au niveau de la jonction ni la dégradation de la fiabilité d'un film d'oxide de grille en raison des contaminants métalliques.
PCT/JP1998/000599 1997-02-20 1998-02-13 Procede pour fabriquer un dispositif a semi-conducteurs WO1998037583A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9/35910 1997-02-20
JP3591097 1997-02-20

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926741A3 (fr) * 1997-12-23 1999-11-03 Texas Instruments Incorporated Structure de grille et sa méthode de fabrication
JP2003531472A (ja) * 1999-09-02 2003-10-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド タングステンゲート封入ｍｏｓトランジスタおよびメモリ・セルならびにその作成方法
US7846826B2 (en) 2004-10-15 2010-12-07 Elpida Memory Inc. Method of manufacturing a semiconductor device with multilayer sidewall

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335885A (ja) * 1994-06-08 1995-12-22 Samsung Electron Co Ltd 低抵抗ゲート電極を有する半導体素子の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07335885A (ja) * 1994-06-08 1995-12-22 Samsung Electron Co Ltd 低抵抗ゲート電極を有する半導体素子の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0926741A3 (fr) * 1997-12-23 1999-11-03 Texas Instruments Incorporated Structure de grille et sa méthode de fabrication
JP2003531472A (ja) * 1999-09-02 2003-10-21 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド タングステンゲート封入ｍｏｓトランジスタおよびメモリ・セルならびにその作成方法
US7846826B2 (en) 2004-10-15 2010-12-07 Elpida Memory Inc. Method of manufacturing a semiconductor device with multilayer sidewall

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