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WO1999000940A2 - Systeme de bus pour un reseau de communication numerique et procede pour commander un tel systeme - Google Patents

Systeme de bus pour un reseau de communication numerique et procede pour commander un tel systeme Download PDF

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Publication number
WO1999000940A2
WO1999000940A2 PCT/DE1998/001621 DE9801621W WO9900940A2 WO 1999000940 A2 WO1999000940 A2 WO 1999000940A2 DE 9801621 W DE9801621 W DE 9801621W WO 9900940 A2 WO9900940 A2 WO 9900940A2
Authority
WO
WIPO (PCT)
Prior art keywords
data
lines
transfer mode
transmission
bus system
Prior art date
Application number
PCT/DE1998/001621
Other languages
German (de)
English (en)
Other versions
WO1999000940A3 (fr
WO1999000940A8 (fr
Inventor
Ekkehard Pott
Wilfried Boets
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1999000940A2 publication Critical patent/WO1999000940A2/fr
Publication of WO1999000940A3 publication Critical patent/WO1999000940A3/fr
Publication of WO1999000940A8 publication Critical patent/WO1999000940A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0098—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
    • H04L2012/5679—Arbitration or scheduling

Definitions

  • the present invention relates to a bus system for a digital communication network according to the preamble of appended claim 1 and a method for transmitting signals in a digital bus system
  • the bus system comprises a bus made up of several groups of lines for transmitting digital signals, several interfaces for connecting access units to the bus and at least one control unit for controlling the signal transmission between the control unit and connected access units or between connected access units.
  • the synchronous transfer mode includes all methods of digital transmission of signals with the plesiochronous digital hierarchy and the synchronous digital hierarchy as well as all digital methods of line switching.
  • Characteristic of the synchronous transfer mode is a fixed time interval between the different channels arranged within a frame, which are formed by time slots, and also the synchronization of the frame by a frame sync word.
  • Each time slot or channel has a different fixed one time interval to the synchronization channel or frame header and this interval is also the address of the channel.
  • Each time slot usually contains a fixed number of bits, usually 8 bits.
  • Each frame and thus each time slot appears at a constant distance, for example 8000 times a second at a frame clock frequency of 8 MHz.
  • Most conventional digital communication networks and thus also their bus systems are operated on the basis of the synchronous transfer mode.
  • the asynchronous transfer mode is much more flexible than the synchronous transfer mode.
  • the asynchronous transfer mode takes the place of the time slots of the synchronous transfer mode.
  • At the beginning of such a cell there is a head which contains the address information for identifying the cell.
  • the corresponding cells can be assigned to certain connections using this header.
  • the cells no longer have to be transported at a constant distance from the synchronizing channels as in the synchronous transfer mode.
  • different bit rates can be achieved by sending cells out at different frequencies. All cells in the network are to be treated in the same way in terms of transmission technology and switching technology, regardless of whether they are sent frequently or rarely. This enables a single network of uniform technology for a wide variety of bit rates.
  • the basic functional principle of the asynchronous transfer mode is based on data transmission via virtual connections.
  • a virtual connection is set up, used for communication and cleared down again, but is not always switched through as a line, but is merely identified as a connection throughout.
  • the characteristic of a virtual connection between two subscribers The digital communication network based on the asynchronous transfer mode is a logical channel number which is assigned separately for each partial connection when the connection is established and which also carries each cell with it.
  • the logical channel number is assigned to an access unit connected to the communication network only for the duration of the connection, in general this number changes from connection to connection, since the next free logical channel is always used when establishing a connection.
  • the logical channel number is assigned in a bus system by a corresponding control unit.
  • Conventional digital communication networks or bus systems for digital communication networks can transmit signals or data either exclusively in the synchronous transfer mode or exclusively in the asynchronous transfer mode.
  • a considerably lower expenditure on control and switching technology is required than when transferring signals in the asynchronous transfer mode.
  • the transmission in asynchronous transfer mode enables the transmission of signals even with different bit rates in a very flexible manner.
  • there is neither a bus system nor a method for transmitting signals in a bus system which allow signals to be transmitted both in synchronous and in asynchronous transfer mode and thus combine the advantages of both transmission options.
  • Communication network comprises a bus from several groups of lines for the transmission of digital signals, several interfaces for connecting access units to the bus and at least one control unit for controlling the signal transmission between the control unit and the connected access units or between connected access units, each interface for both the connection of a data in the synchronous transfer mode (ST) access unit is designed as well as for the connection of data in the asynchronous transfer mode (AT) access unit, and a first group of lines for the transmission of data within pulse frames composed of time slots of a fixed Length is provided.
  • the pulse frames are each divided into a first container for transferring data in synchronous transfer mode and a second container for transferring data in asynchronous transfer mode.
  • Time slots for connected ST access units and the second container on request from connected AT access units assign time slots that are not assigned to the first container or are not required by it.
  • the control unit is further configured such that it has the first group of lines when transmitting data in two in synchronous transfer mode Halves divided, with the same time slot being assigned to the same access unit in both halves, so that both halves transmit the same data.
  • Each half can comprise a plurality of parity lines for transmitting parity bits, the control unit or the respective access unit receiving the data from the other half in each case when a parity error is detected in one half.
  • control unit is designed in such a way that it divides the first group of lines into two halves when transmitting data in the asynchronous transfer mode, the same time slot being assigned to the same access unit in both halves, so that both halves transmit the same data.
  • control unit can also be designed such that when data is transmitted in asynchronous transfer mode, it distributes the data to be transmitted over the entire first group of lines, the first group having a plurality of lines for transmitting error detection and Correction data includes and the control unit reduces the transmission of data in the asynchronous transfer mode when a serious error occurs to half the lines of the first group.
  • the first group of lines can have at least one line for transmitting a bus operating signal that is generated by a connected AT access unit and the end of the transmission of data by the latter
  • Access unit identifies.
  • a second group of lines for the transmission of request signals can be provided within pulse frames of a fixed length composed of time slots, each time frame being assigned to each interface provided in the bus system, in which time slots are assigned in each pulse frame, in which AT- connected to the corresponding interfaces Access units of the control unit can transmit request signals for the assignment of a second container.
  • a third group of lines for transmitting control signals for controlling connected access units and their interfaces is also advantageously provided.
  • the third group can comprise backflow lines, which are used for the transmission of data in the asynchronous transfer mode for the transmission of signals with which the transmission of data of different priority levels is controlled.
  • a fourth group of lines for transmitting signals is further provided, at least one of each of these lines for transmitting a pulse frame clock and a time slot clock from the
  • Control unit to the connected access units and at least one of these lines for transmitting a reference clock from the connected access units to the control unit.
  • a second control unit is provided, the structure of which corresponds to that of the first control unit and which takes over its tasks in the event of a malfunction of the first control unit.
  • Control unit for controlling the signal transmission between the control unit and the connected access units or between connected access units can be connected, each interface being transmitted both for the connection of data transmitted in the synchronous transfer mode (ST) and for the connection of data transmitted in the asynchronous transfer mode ( AT) access unit is designed, data are transmitted in a first group of lines within pulse frames composed of time slots of a fixed length, the pulse frames each in a first container for transmitting data in synchronous transfer mode and a second container for
  • the first container in each pulse frame has fixed time slots for connected ST
  • access units and the second container are assigned time slots which have not been assigned to the first container or are not required by it.
  • the first group of lines is divided into two halves when transmitting data in the synchronous transfer mode, the same time slot being assigned to the same access unit in both halves, so that the same data are transmitted in both halves.
  • Each half can have several
  • Parity lines for transmitting parity bits comprise, the data from the other half being received by a connected control unit or a respective access unit upon detection of a parity error in one half.
  • the first group of lines for transmitting data in the asynchronous transfer mode can be divided into two halves, the same time slot being assigned to the same access unit in both halves, so that the same data are transmitted from both halves.
  • the data to be transmitted can be distributed over the entire first group of lines, the first group comprising several lines for transmitting error detection and correction data and the transmission of data in the asynchronous transfer mode Occurrence of a serious error is reduced to half the lines of the first group.
  • a bus operating signal is transmitted which is generated by an AT access unit and which indicates the end of the transmission of data by this access unit.
  • request signals are also transmitted in a second group of lines within pulse frames of a fixed length composed of time slots, wherein each interface provided in the bus system is assigned specific time slots in each pulse frame, in which AT access units connected to the corresponding interfaces
  • Request signals for assigning a second container can be transmitted.
  • backflow signals can still be transmitted in the transmission of data in the asynchronous transfer mode, with which the transmission of data of different priority levels is controlled.
  • clock signals are transmitted in a fourth group of lines, with a pulse frame clock and an in at least one of each of these lines
  • the bus can have a second control interface for connecting a second control unit, the structure of which corresponds to that of the first control unit, a connected second control unit taking over its tasks in the event of a malfunction of the first control unit.
  • FIG. 2 shows a more detailed illustration of the bus system from FIG. 1,
  • FIG. 3 shows a schematic illustration of a pulse frame for the exclusive transmission of data in the synchronous transfer mode
  • FIG. 6 shows a schematic illustration of a pulse frame for the transmission of data in the synchronous and in the asynchronous transfer mode
  • 10 is a schematic representation of several pulse frames with a special pulse frame
  • FIG. 11 shows a schematic illustration of a pulse frame and a time slot for request data
  • Fig. 13 is a schematic representation of the invention
  • Fig. 14 is a schematic representation of an arrangement for
  • 16 is a schematic representation of the bus system according to the invention to explain the connection of additional access units during the
  • FIG. 17 shows a schematic illustration of the bus system according to the invention with backflow lines
  • FIG. 18 shows a more detailed illustration of the bus system shown in FIG. 17.
  • the bus system comprises a bus 1 consisting of a number of lines for transmitting digital signals, a plurality of connected access units 2, 3, 4, 5, 6 and 7 and two connected control units 8 and.
  • the access units 2 to 7 are plugged into corresponding interfaces on a bus base plate.
  • the control units 8 and 9 can also be plugged into corresponding control interfaces, or can also be permanently connected to the bus.
  • the access unit 2 is an access unit that transmits data in the asynchronous transfer mode, while the access units 3 and 4 transmit data in the synchronous transfer mode.
  • the interfaces for connecting the access units to the bus base plate are designed both for connecting data (ST) access units 3, 4 transmitted in synchronous transfer mode and for connecting data transmitted in AT mode (AT) access units.
  • the access unit 5 shown in FIG. 1 is an access unit which establishes the connection to a switching network for the asynchronous transfer mode, and the two access units 6 and 7 are used for exchanging time slots.
  • Bus 1 is in two
  • the two access units 2 to 5 are connected to both halves.
  • the two access units 6 and 7 are each connected to only one half of the bus 1.
  • Both control units 8 and 9 are also each connected to both halves of the bus 1.
  • the two control units 8 and 9 are constructed essentially the same and each have a bus access control element 10 and a clock generation unit 11.
  • the control unit 8 serves as an active control unit, while the control unit 9 is in the rest position. This means that the signal or data transmission is normally controlled by the control unit 8 and the control unit 9 the function of the
  • Control unit 8 only takes over if it shows malfunctions.
  • a connecting line 12 between the two Control units 8 and 9 are used for communication between these two control units, among other things
  • Clock synchronization signals and control signals are transmitted. Furthermore, the connecting line 12 is used to check the two control units 8 and 9 and if necessary. to switch off the faulty control unit.
  • the bus 1 comprises different groups of lines for the transmission of digital signals.
  • a first group 13 of lines serves for the transmission of data between connected access units or between connected access units and the control units.
  • the first group 13 of lines is divided into two halves 13a and 13b, connected ST access units and connected AT access units as well as the two control units 8 and 9 each being connected to both halves 13a and 13b.
  • a second group 14 of lines is used for the transmission of request signals.
  • the second group 14 of lines also consists of two halves 14a and 14b, each interface for connecting ST and AT access units 3 and 2 being connected to both halves 14a and 14b.
  • request signals are sent from connected AT access units 2 to the corresponding control unit 8 or 9, if necessary, in order to be able to transmit AT data.
  • the interfaces for the connection of access units 6 and 7 for the time slot exchange are not connected to the second group 14 of lines.
  • a third group 15 of lines is used to transmit control signals between the interfaces for the access units or connected access units and the control units 8 and 9.
  • a fourth group of lines which is not shown in FIG. 2, is used to transmit clock signals between connected access units and the control units.
  • the bus naturally includes power lines, ground lines and additional lines for other needs.
  • the third group 15 of lines also includes
  • the respective control unit receives a signal from the corresponding interface via one of the lines 22 to 25 that no access unit is connected there, the
  • the third group 15 further includes backflow lines which are used in the transmission of data in the asynchronous transfer mode for the transmission of signals with which the transmission of data of different priority levels is controlled. As shown in Fig. 2, backflow lines 16 are only between the control units 8 and 9 and the interfaces for the connection of AT and ST access units 2 to 3.
  • the third group 15 of lines further comprises lines 17 for transmitting management signals between the access units 2 to 7 and the control units 8 and 9.
  • the data lines shown in bold lines in FIGS. 1 and 2 each comprise a bundle of parallel lines for transmitting signals.
  • the two halves 13a and 13b of the first group 13 of data lines each comprise 40 lines, of which 32 lines each for the transmission of data and the remaining 8 lines each for the transmission of error detection, parity and / or
  • the two halves 14a and 14b of the second group of lines each comprise 4 data lines, 3 of which are each for the transmission of
  • Request signals and a data line for transmitting parity bits is used.
  • the data in the data lines 13a, 13b are transmitted on the basis of pulse frames with a duration of 125 ⁇ s.
  • the frames are each divided into a fixed number of time slots. In the event that the time slot clock frequency is 25.6 MHz, each pulse frame is thus divided into 3200 time slots, whereby a theoretical throughput of 0.82 gigabits / sec can be achieved for one half 13a or 13b of data group 13. If both halves 13a and 13b are used simultaneously for the transmission of data, a total throughput of up to 1.64 gigabits / sec. can be achieved.
  • the pulse frames are essentially divided into two containers, the first container for the transmission of
  • Data in synchronous transfer mode and the second container is used to transfer data in asynchronous transfer mode.
  • the The first container for the transmission of data in the synchronous transfer mode is divided with a predetermined division or determinable by the control units 8 or 9 into specific time slots in each pulse frame.
  • the part of each pulse frame that is not required for the transmission of data in the synchronous transfer mode or the time slots of the pulse frame that are not required for the transmission of data in the synchronous transfer mode are available for the second container for the transmission of data in the asynchronous transfer mode. Since larger cells or packets with a variable amount of data are transmitted in asynchronous transfer mode, the useful bandwidth of the bus can be used flexibly depending on the amount of data to be transmitted.
  • Data in the synchronous transfer mode is preferably carried out by the control unit 8 or 9.
  • the control unit is via connections to be set up or to be released, i.e. connected ST access units teaches and distributes the data to be transmitted in the synchronous transfer mode accordingly over the time slots of the corresponding pulse frame.
  • Time slots that are not or no longer occupied by data to be transmitted in the synchronous transfer mode can be used for the transmission of cells or packets of the asynchronous transfer mode.
  • the boundary between the two types of transfers can be seen as dynamic and virtual. Connections for the transmission of data in synchronous transfer mode are set up with priority. The remaining capacity of the bus is available to the connections for the asynchronous transfer mode.
  • a pulse frame is shown schematically in FIG. 3, in which only data is transmitted in the synchronous transfer mode.
  • the pulse frame 26 shown initially comprises a conventional head 27 with identification data,
  • the time slots 30 contain the data transmitted in the synchronous transfer mode. Each time slot transmits a fixed number of bits, for example 8 bits.
  • the pulse frame 26 comprises time slots 28 with control data for the synchronous transfer mode and time slots 29 with data for checking the bus.
  • the time slots 28 and 29 are preferably always arranged at the same positions of a pulse frame. At least one time slot for transmitting data and one time slot for receiving data are reserved for each interface of the bus, ie for each possible access unit position. This solution enables the implementation of a standard solution for all types of data traffic in synchronous transfer mode. The remaining part of each pulse frame is available for additional data traffic in the synchronous transfer mode and / or in the asynchronous transfer mode.
  • each time slot 30 with data transmitted in the synchronous transfer mode contains one byte, ie 8 bits of synchronous data, a signaling bit and a parity bit being additionally provided in each time slot.
  • the parity bit is used to protect the data bits and the signaling bit.
  • the signaling bit is used by the access units 6 and 7 for the time slot exchange, which are provided for through-signaling for analog access units.
  • a time slot 30 with data transmitted in the synchronous transfer mode thus consists of 8 data bits, a signaling bit and a parity bit.
  • the isochronous channels ie the time slots used for the transmission of signals in the synchronous transfer mode, are used to transport very time-critical data types, such as voice data and video data, and to meet real-time requirements. Furthermore, these time slots are used to exchange administrative information between the control units 8 and 9 and one of the connected access units, to transport administrative information from the control units 8 and 9 to all connected access units and a presence and functionality check of all connected access units. The functionality of the bus and its lines are also tested.
  • the assigned time slots are managed in all AT and ST access units. Around the mean wait for im asynchronous
  • Adhering to the transfer mode of data to be transmitted takes place as uniformly as possible allocation of the time slots for the synchronous transfer mode.
  • the connections 8 are set up and released by the control units 8 and 9.
  • the time slot allocation is permanently valid during the existence of the connection and applies to all pulse frames until the connection is cleared down.
  • the equal distribution of the time slots for the synchronous transfer mode also has the advantage that the administrative effort for setting up and releasing time slots is relatively low.
  • the assignment and release as well as the relevant time for the assignment and release of time slots must be communicated to all connected access units. This is done by the control units 8 and 9 using reserved channels to all connected access units simultaneously, i.e. in the broadcast process.
  • the new number of the occupied or activated time slot is thus available to all access units at the same time.
  • the new occupancy status is valid from the following pulse frame.
  • the maximum waiting time thus corresponds to the length of a pulse frame, namely 125 ⁇ s.
  • the bus system can thus be adapted to fluctuating traffic loads.
  • an acknowledgment mechanism can be provided with which the acceptance of the central assignment to the control units 8 or 9 is confirmed by all connected access units.
  • an acknowledgment mechanism can be provided with which the acceptance of the central assignment to the control units 8 or 9 is confirmed by all connected access units.
  • basic channels are automatically set up, by means of which the connected access units can be addressed.
  • the channel number is linked to the interface number and is used for internal communication between the control units and the connected access units.
  • FIG. 4 schematically shows a pulse frame 31 which is used exclusively for the transmission of data in the asynchronous transfer mode.
  • packets or cells 34 of different sizes can be seen in the pulse frame 31 of FIG. 4, which serve for the transmission of data in the asynchronous transfer mode.
  • the pulse frame 31 has cells 32 in which control data are transmitted in the asynchronous transfer mode.
  • the pulse frame 31 in FIG. 4 also comprises a head 27 with identification data, synchronization information etc., and time slots 29 with data for bus checking.
  • an area 33 is provided which must not be used for the transmission of data in the asynchronous transfer mode, in order to avoid the interruption of a packet 34 with the data transmitted in the asynchronous transfer mode by a pulse frame end.
  • the area 33 is preferably larger than 64 time slots.
  • the pulse frame 31 of FIG. 4 is an example of the fact that the first container, which is reserved for the transmission of data in the synchronous transfer mode, is empty and only data in the second container, ie only data in the asynchronous Transfer mode.
  • Packets 34 include error detection and correction bits in addition to the data bits.
  • the transmission of data is carried out asynchronously
  • Transfer mode uses 7 lines per half 13a and 13b for the transmission of the error detection and correction bits. One more line per half is used to transmit an operating signal indicating that the bus is operating. As with the transmission of data in the synchronous transfer mode, 32 lines are used in each half 13a or 13b of the data group 13 for the transmission of data, while the remaining 8 lines are used for the transmission of signaling bits, parity bits, error correction and correction bits or operating state bits become. This means that 32 bits can be transmitted in parallel in each half.
  • the 8 lines which are used for the transmission of data in the synchronous transfer mode for the transmission of the signaling and parity bits, are used for the transmission of data in the asynchronous transfer mode
  • the second container is used for the transfer of data in the asynchronous transfer mode.
  • the control of this transmission in the asynchronous transfer mode is carried out by the control units 8 and 9 and enables high transmission rates.
  • the issue of the transport permit for the transmission of data in the asynchronous transfer mode in a cell or a packet 34 is decentralized, that is to say in each connected AT access unit. Cells or packages 34 of different lengths can be transported in the second container.
  • the maximum length of a cell 34 is limited by the width of the monitoring device or the counter width for monitoring, the necessary header 27 (sender address, recipient address, etc.), the length of the user data and the Processing of the bus protocol.
  • the minimum length of a cell 34 is determined by the necessary header 27 and the insertion of one byte of user data. Both the minimum and the maximum length should occupy the bus in its width or in multiples thereof.
  • the cell 34 of maximum length comprises a routing head 35 which contains the sender address including the interface address of the AT access unit emitting this cell 34, the receiver address including the interface address of the AT access unit receiving this cell 34, identifiers for multicast addresses, groups of multicast access units , Operational information, administrative information, subcontainer sizes, etc.
  • the AT header 36 of cell 34 contains the AT layer protocol information. There are two different formats for this information, namely the UNI format for the transition between users and the network and sogn. NNI format for the transition between the network nodes and the connecting lines between the network nodes. The two formats differ only in the size of the VPI sub-area (sub-area with information relating to the identification of the virtual path) and the presence or absence of the GFC area.
  • the user data are transmitted in the information area 37.
  • the maximum size of the information area is 48 octets or 48 byte user data.
  • the size of the information area 37 can be reduced to 1 octet or 1 byte, as shown on the right in Fig. 5, and the AT header 36 can remain unused, making it possible to size the cell 34 of up to 9 octets. It is of course possible to have other maximum cell sizes than allow the maximum size of cell 34 of 60 bytes shown.
  • each cell there is an 8 bit checksum field 38 for checking the frame.
  • the maximum size of a cell 34 to be transmitted is limited by a programmable monitoring circuit, for example in the bus access control element 10 of the control units 8 or 9.
  • each of the connected access units receives knowledge of the size of the cell 34 currently being transmitted via the bus operations line in data group 13.
  • a frame 39 is shown in FIG. 6, in which data is transmitted both in the synchronous and in the asynchronous transfer mode.
  • the frame has a conventional head 27 and ST control data time slots 28 and AT control data cells 41.
  • Time slots 29 are also provided for bus checking.
  • the time slots 30 contain data that are transmitted in the synchronous transfer mode, while the cells 34 contain data that are transmitted in the asynchronous transfer mode.
  • the transmission of cells 34 is subordinate in priority to the transmission of time slots 30 in the bus structure. If a cell 34 with data to be transmitted in the asynchronous transfer mode is to be transported on the bus and meets one of the time slots 30 for data transmission in the synchronous transfer mode, the transport of the cell 34 is stopped until the time slots of the frame 39 no longer pass through in the synchronous mode Transfer mode data to be transferred are occupied. Ggffs. the interrupted transport of a cell 34 is interrupted, e.g. in Fig. 6 the transport of cell 34a through time slots 30, and after completion of the transfer of data in synchronous transfer mode continued.
  • the transport of cell 34a through the three time slots 30 is interrupted and after Transfer continued.
  • the transmission of the cell 34b is interrupted by a time slot 30 with the data transmitted in the synchronous transfer mode and is continued after this time slot.
  • each connected AT access unit In order to enable the transmission of data in the synchronous and in the asynchronous transfer mode, an additional signal, which is controlled by the control units 8 and 9, could be implemented in the bus.
  • each connected AT access unit In order to save this signal, each connected AT access unit must have knowledge of time slots in the pulse frame, which are assigned to data to be transmitted in the synchronous transfer mode. This means that all access units must receive information about the reservation and the change in the reservation of time slots for data in the synchronous transfer mode. Time slots for the transmission of cells 34 for data to be transmitted in the asynchronous transfer mode are assigned on request by the connected AT access units. Each AT access unit makes this request accordingly. The second group 14 with request lines is used for this.
  • the head 27 of the pulse frame 39 contains several pieces of information, e.g. the pulse frame number, frame synchronization information and if necessary. the frame clock frequency, a checksum of the head 27, etc. Furthermore, ST control data are transmitted in corresponding time slots 28 in each pulse frame, that is to say in the format of data transmitted in the synchronous transfer mode, between the control units 8 and 9 and the connected ST access units.
  • the number of time slots 28 for this internal protocol during normal operation is determined in accordance with the bandwidth requirements (e.g. 64kbit / s or 256kbit / s).
  • the position of the time slots 28 within the pulse frame 39 corresponds to the
  • the ST control data 28 are used for communication between the control units 8 or 9 and the connected ST access units.
  • 39 60 time slots are provided in each pulse frame as service channels between each connected ST access unit and the control units 8 and 9.
  • 20 time slots serve as service channels from the control units 8 and 9 to each access unit
  • 20 time slots serve as service channels from each access unit to the control units 8 and 9, the second 20 time slots being preceded by a further 20 time slots which contain defined data patterns which are controlled by the control unit 8 or 9.
  • These further 20 time slots are necessary in order to avoid that data of any previous time slot which is still valid in the bus can be misinterpreted as a service channel between the access unit and the control unit 8 or 9. Since the service channels are initialized in a clear manner from the access units to the control units 8 and 9, any removal of an access unit is recognized by the control unit 8 or 9, since the access unit no longer operates the service channel.
  • the service channels also include time slots 29 with bus check signals. In these time slots 29, test patterns are sent from the control units 8 and 9 to the connected access units or vice versa. This bus check data is transmitted on the bus either with incorrect parity to test the parity check or with correct parity and different data patterns to check data group 13 of the bus system.
  • AT control data are transmitted in control cells 41 between control units 8 and 9 and connected AT access units in the format of data transmitted in the asynchronous transfer mode.
  • the sender address and the recipient address of the AT control data correspond to the interface position of the connected AT access unit.
  • An exception to this applies to the service channels, such as the time slots 29 for the bus check, which are also transmitted for AT access units in the format of data transmitted in the synchronous transfer mode.
  • Another exception applies after switching on the bus system, since the
  • Control units 8 and 9 use the defined time slots 28 for the ST control data of the respective interface in order to establish basic communication with the connected AT access units. During operation, the control units 8 and 9 switch the communication to the asynchronous transfer mode.
  • FIG. 7 schematically shows an example of the format of the time slots 28 with ST control data and of the format of the time slots 30 with data transmitted in the synchronous transfer mode.
  • the time slots 30 for ST data consist of an upper half 30a and a lower half 30b.
  • Each half 30a and 30b comprises four bytes of data transmitted in the synchronous transfer mode as well as four parity bits and four signaling bits.
  • each half 30a and 30b thus comprises 40 bits, which are transmitted in parallel in the corresponding half 13a and 13b of the data group 13 of the bus 1.
  • the two halves 30a and 30b are redundant to one another, i.e. it will be the same data in both
  • the time slots 28 for the ST control data have the same format as the time slots 30 for the ST data.
  • the time slots 28 are accordingly divided into two halves 28a and 28b, the two halves being redundant to one another.
  • the upper 16 bits of the upper half 28a of an ST control data time slot 28 may be different from that Access unit 2 (n + i) can be used to transmit and receive data to the corresponding control unit 8 and 9, respectively, while the lower 16 bits of the upper half 28a of the ST control data time slot 28 are used by the access unit 2n + 1.
  • the upper bit 42 of the access unit 2 (n + l) is used to receive data from the corresponding control unit, while the next bit 43 of the access unit 2n + l is used to send control data to the corresponding control unit.
  • the third bit 44 is used by the access unit 2n + l to send control data to the corresponding control unit, while the fourth bit 45 by the access unit 2n + l is used to send control data to the corresponding access unit.
  • a time slot 28 thus serves two connected ST access units for sending and receiving control data. This option is more expensive than the option shown in Fig. 9, but its effectiveness is twice as high.
  • a first time slot 28a x of four connected ST access units is used for receiving control data from the corresponding control unit, while a second time slot 28a 2 of the four ST access units is used for transmission control data is used to the corresponding control unit.
  • the second byte 47 is used for a second ST access unit B for receiving control data from the corresponding one
  • Control unit the third byte 48 is used by a third ST access unit C for receiving control data and the fourth byte 49 is used by a fourth ST access unit D to receive control data.
  • the first byte 50 of the first ST access unit A is used to send control data to the Corresponding control unit
  • the second byte 51 is used by the second ST access unit B to send control data
  • the third byte 52 is used by the third ST access unit C to send control data
  • the fourth byte 53 is used by the fourth access unit D to send control data.
  • a time slot 28 serves four access units for sending control data to the corresponding control unit, while another time slot 28 serves for receiving control data.
  • This solution allows the implementation of a standard solution for all types of data to be transmitted in the synchronous transfer mode between control units 8 and 9 and connected ST access units as well as between connected ST access units. Optimal use of the bandwidth of bus 1 is possible here.
  • the 10 shows two normal pulse frames 39 for the transmission of data in synchronous and asynchronous transfer mode and a special frame 54.
  • the special frame comprises in its header 55 a byte 56 with special information which indicates that the associated frame 54 is a special frame which is specifically aimed at checking the bus and transmitting control data.
  • the special frame 54 includes control time slots 28 and time slots 29 with bus check data.
  • Special frames 54 need no control data 28 or 41 and no time slots 29 with bus check information to be transmitted in the normal pulse frame 39. This reduces the amount of data transferred.
  • the first container for the transmission of data is set up in synchronous transfer mode and ST time slots corresponding to the interface number can be used to address a basic communication path (e.g. to get the type of the connected access units, the assignment of additional time slots for sending and receiving, etc. ) and Download ST access units can be used.
  • ST time slots corresponding to the interface number can be used to address a basic communication path (e.g. to get the type of the connected access units, the assignment of additional time slots for sending and receiving, etc. ) and Download ST access units can be used.
  • the structure of the bus system allows the allocation of smaller parts of the bandwidth, ie steps of 64 kbit / s are possible. So one could
  • Time slot contains up to four 64 kbit / s channels. However, this would have the effect that a larger bus system address area and memory area would be necessary.
  • the allocation of time slots depends on the bandwidth requirements for the download and should be implemented in a flexible way to ensure sufficient bandwidth for the download. Packets or cells are used for downloading data in AT asynchronous transfer mode for AT access units.
  • a new access unit either an AT or an ST access unit
  • this access unit reports itself to the person via the presence line 22, 23, 24 or 25
  • Control unit 8 or 9 after it has carried out a power-on self-test. If the signal of the presence line is valid, this access unit is assigned a fixed time slot by the control unit 8 or 9, in which the access unit communicates its identity to the control unit. The assignment of the ST time slot to the interface position of the access unit and the control unit is thus known.
  • the connected AT access units are provided with cells or packets 34 for the transmission of data in the asynchronous transfer mode on request.
  • the bus comprises a group 14 of request lines, which is periodically made available to each connected access unit.
  • a time slot of a request pulse frame 40 is always within a specific interface of a cycle, within which the connected access unit can make its request for the transmission of a cell or a packet 34 in the asynchronous transfer mode.
  • FIG. 11 shows a request pulse frame 40, which can have a length of 125 ⁇ s, for example.
  • time slots 57 are periodically made available to the 20 different interfaces or connected access units of the bus system.
  • the bus system is of course not limited to 20 interfaces or access units, but can have more or fewer interfaces depending on the requirements.
  • a time slot 57 1 ( 57 2 .. or 57 20 is periodically made available to each interface.
  • the group 14 with request lines comprises two halves 14a and 14b of request lines, each with four lines the format shown in Fig. 11, namely two groups 58 and 60 of 3 bits each for
  • Request data which are protected by a parity bit 59 and 61, respectively.
  • the parity bits 59 and 61 of the request group 15 protect the signals transmitted in the backflow line 16 and the management line 17.
  • the request group 58 of the request time slots can be redundant to the request group 60, but the two request groups 58 and 60 can also represent different request levels, as a result of which the priority of the respective request can be identified. Up to seven priority levels can thus be implemented in the exemplary embodiment shown.
  • the maximum waiting time of an AT access unit for requesting a further cell 34, if it has just transmitted a cell 34, is 19 time slots in the exemplary embodiment explained. Possible variants of the exemplary embodiment explained are the adaptation of the repetition frequency
  • Requirement signal is necessary. These additions are useful if the bus must be used by cells 34 of minimal length. However, the bandwidth loss is significant.
  • the request for a cell 34 to be transmitted is also dependent on the fill level of the memory of the received AT access unit. This degree of filling is communicated by means of backflow signals in the backflow lines 16.
  • the length of a cell 34 to be transported or a cell 34 is communicated in the bus operations management of the data group 13 to all connected access units and the control units.
  • each access unit 2 is monitored via a point-to-point connection (presence line) 22.
  • Presence line 22 the point-to-point connection
  • Presence line 22 is monitored to determine whether access units have been inserted or removed into the base plate 62 of the bus system in the corresponding interfaces or whether an inserted access unit has failed. Such a presence line 22 exists for all interfaces of the bus system on the bus base plate 62. Another point-to-point connection, which is used for switching on or off connected access units, also exists for all interfaces of the bus base plate 62
  • Shutdown lines 18, 19, 20 and 21 can selectively put the interfaces of access units into or out of operation if the inserted access unit is defective.
  • a targeted response of connected access units is possible via the switch-off lines, for example in combination with service signals (two service signals carried as a bus), with which, for example, a reset, self-test, diagnosis, etc. of access units is possible.
  • FIG. 12 shows two control units 8 and 9, which are connected to a bus base plate 62.
  • the control units 8 and 9 can be firmly attached to the bus base plate, or can be detachably attached in appropriate interfaces.
  • Each control unit 8 and 9 comprises a bus access control element 10, to which the shutdown lines 18 and the presence lines 22 for each interface of the bus base plate 62 are connected. Between the two control units 8 and 9 there are connecting lines 12 for the exchange of control information, synchronization information and possibly mutual monitoring and switch-off signals.
  • the bus base plate 62 has at least one interface at which one
  • Access unit 2 is connected.
  • the access unit 2 comprises a bus access control element 64 and a driver 65.
  • the bus access control element 64 is connected to the presence line 22 and the driver 65 via an inverting input to the switch-off line 18.
  • the driver 65 also controls the two halves 13a and 13b the data group 13, the two halves 14a and 14b of the request group 14 and a reference clock line 66, all of which are connected to the bus base plate 62 via the interface of the access unit 2.
  • the bus access control element 64 controls a time slot clock line 67, a frame clock line 68 and a system clock line 69, which are likewise connected to the bus base plate 62.
  • the frame clock can have a frequency of 8 kHz, while the time slot clock can have a frequency of 25.6 MHz.
  • the shutdown line 18 is in the event of a serious error in an interface or Access unit that affects more than 1 bit in the data transmission, the corresponding access unit switched off, all clock signals can still be received by the access unit. This means that the faulty access unit is only switched off with regard to its data lines.
  • the distribution of the clock frequencies of the bus system is illustrated in FIG.
  • the two control units 8 and 9 each have a clock generation unit 11, of which a time slot clock line 67 and a frame clock line 68 are routed to the interfaces or the connected access units 2 and 3.
  • the clock generation units 11 feed a frame clock of for example 8 kHz and a time slot clock of for example 25.6 MHz to the connected access units 2 and 3 via these lines.
  • the two control units 8 and 9 can be supplied with a second frame clock via lines 70.
  • a line 71 is fed to the two control units 8 and 9, with which the two control units mutually determine their absence or presence.
  • a reference clock is also fed from the connected access units to the control units 8 or 9.
  • All clock lines can have a fast and a slow clock for different types of access units.
  • the slow clock is used by access units with a slow transmission speed of, for example, less than 2 Mbit / sec. used, while the fast clock of access units with a high transmission speed of, for example, more than 2 Mbit / sec. is used.
  • the presence lines 22 to 25 from each interface to the control units 8 and 9 are also used to switch the clock lines on and off.
  • the clock lines can be designed as point-to-point connections between the interfaces and the control units 8 and 9.
  • the bus system can be operated in two operating states.
  • both halves 13a and 13b of the data group 13 are used for the transmission of identical data.
  • One half 13a is thus redundant to the other half 13b.
  • Both halves transmit the same information.
  • the same time slot is assigned to an ST access unit or to both access units 6 and 7 for the time slot exchange on both halves 13a and 13b.
  • the access unit 6 is only connected to one half 13b, while the other access unit 7 for the time slot exchange is only connected to the first half 13a.
  • the transmitted information from the access units 6 and 7 for the time slot exchange is not necessarily synchronous on both halves 13a and 13b.
  • the data are transferred redundantly in both halves 13a and 13b of the data group 13.
  • the useful information transmitted is in each case taken over by the addressed access unit or the control unit from that half 13a or 13b which has been determined by default.
  • the ST data are protected against parity, and in the event of a parity error in the half 13a or 13b determined by default, the useful information is taken over from the other half 13b or 13a.
  • the incorrectly transmitted user information are not saved.
  • a data comparison of the contents of both bus halves 13a and 13b can be carried out.
  • the data group is considered, for example, in the present exemplary embodiment as a 64-bit bus, which is protected against errors and errors, for which an additional seven bits are required for each 32-bit half 13a or 13b.
  • the data group is considered, for example, in the present exemplary embodiment as a 64-bit bus, which is protected against errors and errors, for which an additional seven bits are required for each 32-bit half 13a or 13b.
  • single bit errors can be recognized and corrected within one cycle. Errors that affect two bits are only recognized. Serious errors, which concern more than two bits, are recognized by data comparison and lead to the shutdown of the affected half 13a or 13b, whereby the bandwidth available for transmission is halved.
  • Access units are informed by the control unit about the allocation of a special multicast time slot.
  • the multicast is supported by the leading head 35 of each cell 34, in which multicast groups can be addressed.
  • FIG. 14 schematically shows an error checking arrangement of an ST access unit which is connected to the two halves 13a and 13b of the data group 13.
  • the data arriving in the respective half 13a or 13b are received in a respective receiving element 74 and are each forwarded to a buffer 80, in which they are buffered.
  • the receiving element forwards the received parity bits to a respective parity checking element 76, which checks the parity bits of the received data.
  • the respective parity check element 76 is connected to the respective buffer 80, to which a write line 82 and a clock line 81 are also fed.
  • the outputs of the two intermediate memories 80 are combined to form a data input line 73.
  • the ST access unit for both halves 13a and 13b each has a buffer memory 77, to which a common data output line 72 is fed, as well as a clock line 78 and a read line 79.
  • the respective output of the buffer memory 77 is via a respective transmission element 75 corresponding half 13a or 13b of the data group 13 supplied.
  • the two output lines 83 and 84 of the parity check elements 76 are each fed to a parity counter 86 and a parity counter 87.
  • the two parity counters 86 and 87 form part of the bus access control element 85 of a control interface 88.
  • the parity counter 86 is connected to the output line 83, while the parity counter 87 is connected to the output line 84.
  • the parity counter 86 counts the parity errors 0, for example, while the parity counter 87 counts the parity errors 1, for example.
  • a parity error is added up in the parity counters 86 and 87, respectively, until it has one
  • Threshold reached When the predeterminable threshold value is reached, an interrupt signal is sent to the control unit 8 or 9.
  • the line 89 of the control interface 88 establishes an address and data connection line to the control unit 8 or 9 connected to the interface.
  • data comparators can also be provided which compare the data transmitted in both halves 13a and 13b in order to determine any errors.
  • the reference clock 90 represents the bus clock signal that corresponds to the time slot clock signal.
  • Arrow 57 indicates the length of a request channel in which the access units request signals for the request of the second container for the transfer of data in asynchronous transfer mode.
  • These time slots for the request signals of the various AT access units are identified by reference numeral 91, the request time slots of different access units being illustrated by different hatching.
  • the reference symbol 92 denotes an internal request signal which is sent from an AT access unit m to the
  • Access units or the control units is transmitted.
  • the reference symbol 93 clarifies the request signal 97 of the access unit m in the corresponding time slot in the request line.
  • the reference numeral 98 denotes this
  • the reference symbol 94 designates the data line, wherein time slots 30 for the transmission of data in synchronism
  • Reference number 95 shows the data line in the state in which the AT and ST data are actually transmitted in it.
  • the time slots 30 of the first container have priority over packets 100 and 101, in which data is in asynchronous
  • Transfer mode can be transferred in the second container.
  • the time slots 30 for the transmission of data in the synchronous transfer mode are only interrupted by the ST control data 28 arranged at predetermined locations in the respective pulse frame.
  • the cells or packets 100 and 101 for the AT data are inserted in the time slots in which no ST data slots 30 are transmitted.
  • the AT data packet 100 is divided into two halves 100a and 100b, for example by an ST data slot 30.
  • the AT data packet 101 is divided into two data packets 101a and 101b by a time slot 30.
  • the arrow 103 indicates the occupancy of the data lines by the long AT data packet 100 from the access unit m, while the arrow 104 indicates the occupancy of the data lines by the short AT data packet 101 from the access unit n.
  • the reference symbol 96 denotes an example of a bus operating signal with which the assignment of the data lines by AT data packets is identified.
  • the bus operating signal 96 in the exemplary embodiment explained heralds the end of an AT data packet two time slots before the actual end of the AT data packet.
  • the bus operating signal 96 cannot identify AT data packets that are only two data slots long, such as the AT data packet 101, and in the event of an AT data packet being interrupted by a time slot 30, the bus operating signal 96 is interrupted. Time slot 102 is data-free.
  • Halves 13a and 13b can be used.
  • An ST timeslot table in each interface or in each access unit contains the assignment of timeslots 30 to the corresponding interface position and is updated by the bus access control element in each access unit using the multicast possibility of the bus or via the head 27 of the pulse frames 39.
  • the maximum delay for ST data traffic to be transmitted on the bus is 125 ⁇ s.
  • the AT access units control the bus for the AT data packets to be transmitted in the second container independent, ie decentralized. This is possible because the knowledge about occupied ST time slots 30 and about requested time slots 34 for the asynchronous transfer mode is available in all access units. Depending on the different bus request parity levels, an AT access unit can independently control access to the bus. In order to enable the use of different packet or cell sizes 34, the additional bus operating signal is used, which indicates the size and the end of an AT data packet.
  • the maximum delay in the transmission of AT data packets becomes 35 ⁇ s. This value depends on the priorities set and the bus request capacity. In the present exemplary embodiment, four different priority levels have been set, the priority of cells which do not have the highest priority being increased if they have been waiting for a long time.
  • bus control comprises activating or deactivating the interfaces of the access units, monitoring the presence or absence of access units and filling up unused time slots in which no data is transmitted with teaching information in order to prevent the bus from floating.
  • Bus monitoring includes monitoring bus requirements, monitoring the length of the two containers, and controlling the bus park mechanism.
  • the control of the access units includes the control of the clock signals.
  • the control units 8 and 9 inform all connected access units, from where the time slot clock and the frame clock are to be taken.
  • the connected access units can only observe the presence or absence of the clock signals, but cannot control them. For this reason, it is possible to switch over from one clock source to a redundant clock source.
  • the information from the control units 8 and 9 to the access units, where the clock signals are to be taken from can either be sent by sending a command to all connected access units (broadcast) or to a group of connected access units (multicast) or by using a combination of the administration - and the shutdown lines of the bus.
  • control units 8 and 9 can send a reset command to the connected access units via a combination of the administration and the shutdown lines, which reset the affected access units.
  • the reset deactivates all access units or switches to a reception state. No signal other than the presence or absence signal to the affected access units can
  • Control units 8 and 9 are sent out more.
  • the access units can start their self-test.
  • control units 8 and 9 can use a combination of the administrative and the
  • Absence lines put the corresponding access units into a deactivation state or a reception state. In this case, no signal can be sent from the access units to the control units, apart from the presence or absence signal. In parallel, however, the access units can start their self-test.
  • Another requirement for the bus system according to the invention is that additional access units can be plugged into corresponding interfaces during the operation of the bus system.
  • the introduction or removal of an access unit must have no influence on the operation of the system. This requirement is met through the use of DC-DC converters (DC / DC converters) 110 and blocking logic 106 for the transceivers 107 in FIGS.
  • Access units 2 reached, as shown for example in Fig. 16.
  • a DC-DC converter 110 in each access unit is connected to a current monitor 109, which is coupled to the blocking logic 108.
  • the locking logic controls the transceiver 107 of the access unit 2, a leading pin 105 of the access unit 2 being connected to the locking logic 108 and the transceiver 107.
  • the leading pin 105 When the access unit 2 is inserted into the interface, the leading pin 105 will first contact the interface.
  • the leading pin 105 guarantees a defined voltage at the activation output of the Transceivers 107, which remains in the tri-state for transmission and reception.
  • the transceiver 107 remains in the tri-state, which is ensured by the blocking logic 108.
  • the presence line 22 can indicate that at least the access unit 2 is present and the self-test of the access unit 2 is running successfully.
  • the control unit 8 or 9 can then activate the interface of the access unit.
  • the control units 8 and 9 can also have pins 106 leading them, so that, for example, a second control unit 9 can be added with a first control unit 8 during operation of the bus system.
  • the data packets 34 are transmitted in the asynchronous transfer mode in FIG.
  • Data group 13 in the preferred embodiment with four priorities.
  • the highest priority is for the transport of AT data packets with a constant bit rate or peak bit rate, while the next priorities are set for the variable bit rate, the available bit rate and the undetermined bit rate.
  • These priorities only apply locally, i.e. within the respective access unit, only one priority being known to the bus itself.
  • the connected access units in through 115 are connected by a backflow line 16.
  • Arrows 121 represent the data transmission direction.
  • the data is thus transmitted from the access units 111, 112 and 113 to the access unit 114, which it forwards via its output line 120.
  • the access units 111, 112 and 113 sending out the data are supplied with data via their input lines 119.
  • Each access unit has an output buffer store 116 and two input buffer stores 117 for the data received via data group 13 from other access units.
  • the access units 111, 112, 113 and 114 have a small output buffer 116, while the access unit 115 has a large output buffer 118.
  • FIG. 18 shows the backflow system shown in FIG. 17 in more detail.
  • the access unit 115 comprises a large output buffer 118, which has an output memory 122 for data with constant bit rate and an output memory 123 for data with other bit rates, e.g. variable bit rate, available bit rate or indefinite bit rate.
  • the data coming from the access units 112 and 113 are fed via the data group 13 to the output memory 122 or the output memory 123 of the access unit 115 depending on their bit rate.
  • the output memory 122 is connected to the backflow line 116 which, when the output memory 123 is overfilled, sends a backflow signal to the input memory 124 of the other access units 112 and 113.
  • the input memory 124 of the access units 112 and 113 is used for the temporary storage of data with variable bit rate, available bit rate or indefinite bit rate.
  • the input memory 125 of the access units 112 and 113 serves for the temporary storage of data with a constant bit rate.
  • the two memories 124 of the two access units 112 and 113 are connected to an input line 119a for data with a non-constant bit rate, while the two input memories 125 are connected to an input line 119b for data with a constant bit rate.
  • the two input lines 119a and 119b together form the input line 119 of the access units.
  • a non-blocking system is backed up, in which only cells with a constant bit rate and with a variable bit rate read in such a way the total bit rate is less than 85% of the line bit rate on the output side. Furthermore, cells with an available bit rate and with an undetermined bit rate are no longer read from the input memory 124 into the respective input memory 125. Cells already in the input memory 125 with a variable bit rate, with an available bit rate or with an indefinite bit rate are also transmitted via the data line 13 when a back pressure signal is present, since all other modules are still receivable.
  • the other modules are still receptive, since the backflow signal is triggered when the predetermined threshold value is exceeded. Cells with a constant bit rate are therefore still transmitted with the highest priority directly to the receiving access unit 115 even when a jam signal is present.
  • the output memory 123 for non-constant bit rates of the access unit 115 has two or three threshold values, when they are exceeded backflow signals are sent back to all transmitting AT access units 112, 113. The backflow signal thus indicates the degree of filling of the output memory 123 of the access unit 115.
  • the access units 112 and 113 can also have corresponding output memories 122 and 123. This creates a non-blocking system.
  • a two-stage backflow signal could also be implemented, in which, in a second stage, data packets with a variable bit rate are also no longer accepted in the input memory 125.

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Abstract

L'invention concerne un système de bus pour un réseau de communication numérique, comportant un bus (1) qui comprend plusieurs groupes de lignes servant à transmettre des signaux numériques, plusieurs interfaces pour raccorder des unités d'accès au bus, et au moins une unité de commande (8) pour commander la transmission des signaux entre l'unité de commande (8) et des unités d'accès raccordées, ou entre des unités d'accès raccordées (8, 9). Chaque interface est conçue aussi bien pour le raccordement d'une unité d'accès ST (3) transmettant des données en mode synchrone que pour le raccordement d'une unité d'accès AT (2) transmettant des données en mode asynchrone. Il est prévu un premier groupe de lignes (13) pour la transmission de données à l'intérieur de trames pulsées de longueur fixe, composées de tranches de temps. Les trames pulsées sont divisées chacune en un premier conteneur pour la transmission de données en mode synchrone et un deuxième conteneur pour la transmission de données en mode asynchrone.
PCT/DE1998/001621 1997-06-16 1998-06-15 Systeme de bus pour un reseau de communication numerique et procede pour commander un tel systeme WO1999000940A2 (fr)

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DE19725422.5 1997-06-16
DE1997125422 DE19725422A1 (de) 1997-06-16 1997-06-16 Bussystem für ein digitales Kommunikationsnetz und Verfahren zur Steuerung eines derartigen Bussystems

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DE19725422A1 (de) 1998-12-17
WO1999000940A8 (fr) 1999-10-28

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