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WO1999033104A1 - Memoire a semi-conducteur, son procede de fabrication et masque d'implantation - Google Patents

Memoire a semi-conducteur, son procede de fabrication et masque d'implantation Download PDF

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Publication number
WO1999033104A1
WO1999033104A1 PCT/DE1998/002853 DE9802853W WO9933104A1 WO 1999033104 A1 WO1999033104 A1 WO 1999033104A1 DE 9802853 W DE9802853 W DE 9802853W WO 9933104 A1 WO9933104 A1 WO 9933104A1
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WO
WIPO (PCT)
Prior art keywords
doped region
implantation
doped
region
transistor
Prior art date
Application number
PCT/DE1998/002853
Other languages
German (de)
English (en)
Inventor
Albrecht Kieslich
Elke Eckstein
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1999033104A1 publication Critical patent/WO1999033104A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

Definitions

  • the invention relates to a semiconductor memory in a semiconductor substrate with memory cells, each comprising a capacitor and a MOS selection transistor and in which the capacitor is designed as a trench capacitor, and a manufacturing method.
  • the storage electrode is arranged in a trench in the semiconductor substrate, the common counter electrode is formed in a suitable manner by the semiconductor substrate.
  • the trench wall is lined with a capacitor dielectric, and there may be a thickened oxide collar near the substrate surface.
  • the associated selection transistor is arranged adjacent to the capacitor.
  • a first doped region of the selection transistor must be connected in a suitable manner to the storage electrode; This can be done, among other things, by a direct side wall contact, a so-called surface strap or a buried strap.
  • the second doped region of the selection transistor is connected to a bit line.
  • the doped regions have the opposite conductivity to the substrate in which they are arranged.
  • a p-channel selection transistor in an n-doped substrate is assumed below; the n-doped substrate can also be an epitaxial layer on a p-doped silicon substrate, for example.
  • all versions can be transferred to a p-type substrate with an n-channel transistor.
  • the storage electrode is formed by a region of the substrate and the cell plate by a polysilicon structure arranged in the trench. It is also possible to accommodate both electrodes in the trench.
  • the lowest possible contact and sheet resistance of the doped regions of transistors in the substrate is important. This is achieved by covering the doped area with a silicide. For example, an approximately 25 ⁇ m thick TiSi layer is applied to the exposed silicon areas - the S / D areas of transistors in the cell field and in the periphery - in a complex and cost-intensive process. The contact and sheet resistance of the p- and n-diffusion areas are then determined by the conductivity of the suicide, the doping of the silicon plays a subordinate role.
  • Channel transistors are equally implanted in the cell field and in the periphery using a mask (so-called p + mask, which covers n diffusion areas), common parameters of this boron implantation are a dose of approximately 10 15 cm ⁇ 2 and an energy of 10keV .
  • This implantation - and also an analog implantation of the n-channel transistors in the periphery - generally takes place after the trench capacitor and the gate have been completed.
  • a higher implantation ie higher dose leads to greater damage to the substrate in the form of lattice defects. It is formed
  • Dislocation loops or similar crystal defects This cannot be tolerated, in particular in the cell field in the vicinity of the first doped region and the trench, since the reliability of the memory, for example, due to an increased leakage current, which leads to a degradation of the retention time
  • the object of the present invention is therefore to provide a memory cell of this type which is easier to manufacture and which has the same or improved electrical reliability, and a simplified manufacturing method.
  • Claim 17 is a particularly suitable auxiliary means specified to solve the task.
  • the invention is based on avoiding a silicide and at the same time only heavily doping the S / D regions in the vicinity of which damage to the substrate is not critical.
  • S / D regions with a sufficiently low resistance are generated in the periphery and for the connection of the bit line in the cell field, but the damage-sensitive region in the cell field around the trench and a subsequent region of the first doped region of the selection transistor are less heavily doped, so that crystal defects are largely avoided here, or can be cured even with a low temperature budget.
  • a higher temperature budget is also available for further process management, so that lattice defects can be cured better.
  • the stronger doping of the second doped region and the peripheral transistors is achieved by first performing a first implantation of all p regions and then a further implantation with an additional mask, which covers damage-sensitive areas - in particular the vicinity of the trench - and the second doped Leaves area open.
  • the second doped region and the S / D regions of the peripheral transistors of the same conduction type are thus implanted more than the first doped region.
  • the parameters of the first and the further implantation are selected such that lattice disturbances in the damage-sensitive area are minimized on the one hand and contact and layer resistances in the other areas are minimized on the other hand.
  • the n-channel peripheral transistors are doped sufficiently high with a mask covering all p regions, so that a silicide assignment is not necessary.
  • the second endowed area and the S / D areas of the peripheral Ri transistors of the same conductivity type have a second dopant concentration which is in the range 10 20 to 10 21 cm “3 (surface concentration after electrical activation).
  • the first dopant concentration in the first doped region can be approximately 10 18 -10 20 cm “ 3 (preferably 10 18 cm "3 ).
  • the selection transistor is designed as an LDD transistor. Then the first doped region can only be doped with the LDD implantation as the first implantation, while using the additional mask the second doped region and the p-channel peripheral transistors are subjected to a further implantation. It is also possible, after the first implantation (for example LDD implantation), to implant the p-doped areas first using a known method (covering the n-diffusion areas), but with a lower dose, and then using the additional mask to implant the second ( third) implantation, so that only the second region and the p-channel peripheral transistors are doped.
  • the first implantation for example LDD implantation
  • the additional mask covers at least the n-diffusion areas and the vicinity of the trench with the adjoining part of the first doped area and preferably — already because the resolution limit has been reached — the entire first doped area.
  • the additional mask can be used as a replacement mask for the previous p + mask or as an additional mask, depending on the boundary conditions. In the latter case, the preceding implantation or implantations are carried out in such a way that a lower dopant concentration and less damage in the substrate is achieved.
  • the additional mask leaves the p-channel transistors open in the periphery, their properties can be optimized without restrictions by the cell area. Areas not critical to damage (periphery, bit line contacts) can be doped significantly higher. p-contact and layer resistances can be optimized separately from the induction of critical crystal damage.
  • the reduction in the S / D implantation on the cell node also reduces the under-diffusion of the S / D implantation under the gate polysilicon of the active word line.
  • This underdiffusion causes a further leak mechanism, which is referred to as "gate induced drain leakage" (GIDL) and is usually reduced by a thick spacer on the word line and a birds beak that is as pronounced as possible (oxidation of the gate oxide on the edge of the word line).
  • GIDL gate induced drain leakage
  • the invention leads to the further advantage that this leak mechanism is greatly reduced by the smaller implantation of the first doped region, since the position of the p / n junction below the gate can be set independently of the transistor performance of the peripheral transistors For example, it is possible to use a thinner spacer at the gate, which simplifies the further process steps (for example, generating the surface strap).
  • Dispensing with the usual silicide layer is made possible by the higher doping of the p-regions mentioned, which is in the range from 10 20 to 10 21 cm "3.
  • a boron implantation in the periphery with a dose of, for example, 2 x 10 15 cm -2 be performed.
  • the dose of the first implantation is of the order of 10 14 cm "2.
  • a higher temperature budget is achieved so that, for example, defects can be healed better and a void-free BPSG than one due to a higher flow temperature (e.g. 1000 C) Insulation layer can be produced on the traistors.
  • the invention can be used analogously when the n and p conductivity are interchanged, that is to say in the case of a memory cell with an n-channel selection transistor. E.g. the further implantation then takes place with the additional mask in the second doped region of the n-channel selection transistor and in the n-channel peripheral transistors.
  • 1 - 3 a top view (a) or a cross section (b and
  • FIG la, b In an n-doped semiconductor substrate 1 (with a p-doped substrate part 1 'in the periphery), a trench 2 is produced according to the known method, which trench insulated ten walls and accommodates a storage electrode 3 made of p-doped polysilicon.
  • the active region of the selection transistor is arranged adjacent to the trench; non-active regions of the substrate surface are provided with an insulation region 4 (for example shallow trench isolation).
  • the trench 2 lying behind the cutting line is shown in dashed lines.
  • the substrate may be heavily doped near the trench or trench bottom to form a functional cell plate.
  • an implantation with boron is carried out, in particular the usual boron implantation for producing LDD regions.
  • the dose is of the order of 10 12 to 10 14 cm “2 , the energy is approximately 8 to 20 keV.
  • This implantation can be carried out using a mask which covers the n diffusion areas (shown on the right in FIG. 1b).
  • a maskless implantation can also be carried out, in particular if the dose is at most 10 13 cm "2 ; in the n diffusion areas, the boron implantation is later compensated for by a higher n implantation.
  • a first doped region 6 and a second doped region 7 are produced in the cell field, corresponding doped regions P6, P7 of a p-channel transistor are produced in the periphery.
  • the dopant concentration of the p regions is approximately 10 18 cm "3
  • n diffusion regions N6, N7 are generated in the p-doped substrate part 1 '. Spacers are produced on the side walls of the gate, so that the gate 5 is completely encapsulated with insulation 8, 8 '.
  • a second p-implantation can now be carried out using the known p + mask - that is, covering the n-diffusion areas - although the dose is lower than in previous methods.
  • ren is selected (the p + mask corresponds to the mask shown in Fig. lb). It is thereby achieved that the dopant concentration is increased in particular in the first doped region 6, but no significant lattice disturbances occur yet.
  • an additional mask Z for example a resist mask, is applied by a known method, covering at least the n-diffusion areas N6, N7 and the damage-sensitive areas of the memory cell, i.e. the trench and the adjoining part of the first doped area and the directly adjacent area of the Covers substrate.
  • the second doped area and the p-areas in the periphery are not covered.
  • the additional mask Z covers a larger area and extends approximately to the middle of the word line.
  • the additional mask Z can consist, for example, of strips, the trench capacitors and the associated first doped regions being located below the strips, and the second doped regions being arranged in the gaps between the strips.
  • a p-implantation is now carried out with the mask Z (dose about 2 ⁇ 10 15 to 10 16 cm “2 , energy 10 keV), the S / D regions P6, P7 of the p-channel transistors in the This further implantation is preferably adjusted so that after the boron diffusion the pn junction is at a comparable depth to the known process control, the transistor parameters (punch behavior, saturation currents, threshold voltage, etc.) remain unchanged.
  • the usually subsequent silicide complex titanium
  • the additional mask is removed and the memory cell is finished using known methods.
  • the reduced implantation dose in the first doped area does not impair the electrical function, since the charge transport within the storage cell is ensured by the highly doped surface strap.
  • the second doped region 7 is connected to a bit line 10. This takes place, for example, via a W contact pillar, the bit line being able to consist of an Al alloy.
  • the p-channel transistor in the periphery is connected to interconnects P1, P12. The same applies to the n-channel transistor (Nil traces, N12).
  • FIG. 4 A top view of the cell array is shown, the bit line contacts (second doped region 7) being arranged in rows along a first direction. The remaining areas of the memory cells, in particular the trench capacitor and the first doped area of the selection transistor, are located between these rows.
  • the additional mask Z in the cell field consists of strips which run essentially in the first direction and leave the bit line contacts 7 and an adjacent part of the insulation 8, 8 'surrounding the gate.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

Dispositif de mémoire à semi-conducteur dans lequel les transistors sont reliés, dans le champ de cellules et dans la périphérie, sans siliciure, à des connexions. Une résistance suffisamment faible est obtenue en effectuant une implantation dans les domaines S/D au moyen d'un masque complémentaire (Z) qui recouvre les zones, sensibles aux dommages, des cellules dans l'environnement des noeuds de cellules, tout en conservant les autres zones dopées du type de conductivité correspondant. Les déformations de réseau dues à l'implantation dans la zone de l'électrode à mémoire sont évitées grâce au fait que la première zone dopée (6), connectée à l'électrode, du transistor de sélection correspondant est plus faiblement dopée que la deuxième zone dopée (7) du transistor de sélection qui est connecté à la ligne de bits.
PCT/DE1998/002853 1997-12-18 1998-09-24 Memoire a semi-conducteur, son procede de fabrication et masque d'implantation WO1999033104A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE29722440U DE29722440U1 (de) 1997-12-18 1997-12-18 Halbleiterspeicher und Implantationsmaske
DE29722440.9 1997-12-18

Publications (1)

Publication Number Publication Date
WO1999033104A1 true WO1999033104A1 (fr) 1999-07-01

Family

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Application Number Title Priority Date Filing Date
PCT/DE1998/002853 WO1999033104A1 (fr) 1997-12-18 1998-09-24 Memoire a semi-conducteur, son procede de fabrication et masque d'implantation

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DE (1) DE29722440U1 (fr)
WO (1) WO1999033104A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7326985B2 (en) 2001-04-24 2008-02-05 Infineon Technologies Ag Method for fabricating metallic bit-line contacts

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4034169A1 (de) * 1989-10-26 1991-05-02 Mitsubishi Electric Corp Dram mit einem speicherzellenfeld und herstellungsverfahren dafuer
JPH03250761A (ja) * 1990-02-28 1991-11-08 Sharp Corp 半導体メモリ素子の製造方法
US5395784A (en) * 1993-04-14 1995-03-07 Industrial Technology Research Institute Method of manufacturing low leakage and long retention time DRAM
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4034169A1 (de) * 1989-10-26 1991-05-02 Mitsubishi Electric Corp Dram mit einem speicherzellenfeld und herstellungsverfahren dafuer
JPH03250761A (ja) * 1990-02-28 1991-11-08 Sharp Corp 半導体メモリ素子の製造方法
US5395784A (en) * 1993-04-14 1995-03-07 Industrial Technology Research Institute Method of manufacturing low leakage and long retention time DRAM
US5439835A (en) * 1993-11-12 1995-08-08 Micron Semiconductor, Inc. Process for DRAM incorporating a high-energy, oblique P-type implant for both field isolation and punchthrough
US5534449A (en) * 1995-07-17 1996-07-09 Micron Technology, Inc. Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 16, no. 45 (E - 1162) 5 February 1992 (1992-02-05) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7326985B2 (en) 2001-04-24 2008-02-05 Infineon Technologies Ag Method for fabricating metallic bit-line contacts

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Publication number Publication date
DE29722440U1 (de) 1998-04-16

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