WO1999036964A1 - Source-down fet - Google Patents
Source-down fet Download PDFInfo
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- WO1999036964A1 WO1999036964A1 PCT/DE1998/003683 DE9803683W WO9936964A1 WO 1999036964 A1 WO1999036964 A1 WO 1999036964A1 DE 9803683 W DE9803683 W DE 9803683W WO 9936964 A1 WO9936964 A1 WO 9936964A1
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- WIPO (PCT)
- Prior art keywords
- semiconductor
- layer
- fet according
- highly conductive
- zone
- Prior art date
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- 239000004065 semiconductor Substances 0.000 claims abstract description 126
- 239000000758 substrate Substances 0.000 claims abstract description 68
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 26
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 9
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 9
- 238000001465 metallisation Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 3
- 230000035515 penetration Effects 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 description 47
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000000407 epitaxy Methods 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 206010010144 Completed suicide Diseases 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/664—Inverted VDMOS transistors, i.e. source-down VDMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
Definitions
- the present invention relates to an FET (field effect transistor) with a source-substrate connection (“source-down-FET”) and a trench gate, in which:
- a drain zone of the one conductivity type is provided on a surface of a semiconductor layer of the one conductivity type arranged on a semiconductor substrate of the one conductivity type,
- Trench gate essentially penetrates the semiconductor layer
- a source zone of one conductivity type is provided at the end of the trench on the other surface of the semiconductor layer, and
- a semiconductor zone of the other conductivity type is provided in the area next to the trench on the other surface of the semiconductor layer, the surface of which, together with the surface of the source zone, forms the other surface of the semiconductor layer.
- FETs with a source-substrate connection have considerable advantages in terms of their cooling, since this can be done via the semiconductor substrate made of silicon, which is at 0 volt. For example, it is possible to screw an FET with a source-substrate connection directly onto the body of a vehicle, which ensures excellent heat dissipation.
- US Pat. No. 5,023,196 A describes a MOSFET with a source-substrate connection and a trench gate, in which epitaxy occurs on a semiconductor substrate of one conductivity type a first semiconductor layer of the other conductivity type and a second semiconductor layer of the one conductivity type are applied, m a trench for the gate electrode is etched down to the semiconductor substrate.
- the trench is lined with an insulating layer and provided with a gate electrode.
- a source electrode is arranged on the surface of the semiconductor substrate opposite the trench, while a drain electrode is arranged in the region of the semiconductor layer of the one conductivity type over a highly doped region of the one conductivity type.
- wafer bonding in which two semiconductor wafers, one of which can also be referred to as a substrate, are connected to one another, has proven to be particularly expedient for the production of semiconductor components and integrated circuits. If an FET with a source-substrate connection is now desired, which is produced by wafer bonding, then the design of the connection layer between the two disks and in particular the short circuit between the source zone provided in the lower region of the trench and the semiconductor zone of the other conductivity type, the so-called “body” Zone ", problematic.
- this object is achieved according to the invention by a buried highly conductive layer between the other surface of the semiconductor layer and the semiconductor substrate.
- This highly conductive layer which can consist, for example, of silicide or titanium nitride, makes approximately or full ohmic contact both with the source zone and with the semiconductor layer of the other their conductivity type is resistant to high temperatures, so as not to be affected by the subsequent process steps for the production of the FET, and allows wafer bonding by placing a semiconductor substrate and a semiconductor layer on their bonding surfaces by means of the highly conductive layer which is on one of these bonding surfaces is applied to be connected.
- a layer consisting of polycrystalline silicon can also be used, the polycrystalline silicon being doped with dopant of one conductivity type.
- the semiconductor zone of the other conductivity type is preferably so highly doped that the pn junction runs in the polycrystalline highly conductive layer.
- the semiconductor substrate on which the semiconductor layer is applied by direct bonding, consists of highly conductive silicon or of several silicon layers.
- the wafer bonding area can run between the semiconductor substrate and the highly conductive layer or between the semiconductor layer and the highly conductive layer.
- the highly conductive layer is first applied to the semiconductor layer, so that the semiconductor layer provided with the highly conductive layer is wafer-bonded to the semiconductor substrate.
- the highly conductive layer is arranged on the semiconductor substrate, so that the semiconductor layer is wafer-bonded to the semiconductor substrate provided with the highly conductive layer.
- Typical dimensions for the respective layer thicknesses are 5 to 10 ⁇ m for the semiconductor layer, less than 1 ⁇ m for the drain zone and approximately 0.01 ⁇ m for the highly conductive layer the semiconductor substrate 50 to 200 ⁇ m, 2 to 5 ⁇ m for the semiconductor zone of the other conductivity type, 1 to 3 ⁇ m for the source zone and 1 to 5 ⁇ m, in particular 3 ⁇ m, for the drain metallization.
- the semiconductor zone of the other conductivity type is preferably heavily doped in the region adjacent to the highly conductive layer.
- a gate electrode located at the edge being grounded to increase the dielectric strength of the edge.
- low-poly silicon fillings of the gates in the region of an insulating layer arranged on the semiconductor layer can have hat-like lateral expansions which ensure a field profile which improves the dielectric strength.
- the semiconductor substrate can consist of monocrystalline silicon or else of polycrystalline silicon which is doped with dopant of the one conductivity type.
- Preferred methods for producing the source substrate connection and trench gate according to the invention are characterized in that either a semiconductor wafer provided with the highly conductive layer is wafer-bonded to the semiconductor substrate, or that the semiconductor substrate provided with the highly conductive layer is wafer-bonded to the semiconductor wafer. In both methods, the individual doping and etching steps are then carried out in the usual way after wafer bonding:
- a first semiconductor wafer of one conductivity type is provided with a zone of the other conductivity type by epitaxy or diffusion. Then m become these Disc of highly doped areas of the one conductivity type introduced, which are to form the source zone.
- the highly conductive layer is applied to it as a short-circuit layer between the source zone and the semiconductor zone of the other conductivity type (“body” region) and the wafer bonding is carried out with a second wafer as the substrate.
- the highly conductive layer does not have to be provided on the first semiconductor wafer. Rather, it can also be arranged on the second semiconductor wafer.
- the highly conductive layer It is essential for the highly conductive layer that it is able to produce approximately or full ohmic contact equally with highly conductive layers of the one and the other conductivity type, is resistant to high temperatures in order to be able to survive subsequent process steps, and direct wafer bonding between the two enables two semiconductor wafers, one of which forms the semiconductor layer and the other the semiconductor substrate.
- the first semiconductor wafer forming the semiconductor layer can be thinned and smoothed, as is expedient for trench etching and further preparation.
- Trench gate is then etched, the drain zones are introduced by diffusion or implantation, and finally a metallization of, for example, aluminum is applied.
- the second semiconductor wafer which forms the semiconductor substrate, can be thinned and metallized, it being possible, for example, to apply a cooling lug. Since the adjustment between the two semiconductor wafers with respect to one another before their bonding is of great importance, pyramid-shaped trenches can be produced, for example, in the first semiconductor wafer by anisotropic etching and partially or completely filled with polycrystalline silicon which is highly doped with dopant of the one conductivity type. The pyramid tips that appear after wafer bonding and thin grinding of the first semiconductor wafer can then be used as alignment marks in the process block with which the trenches are etched.
- silicide or titanium nitride are particularly preferred materials for the highly conductive layer.
- a polycrystalline silicon layer which is heavily doped with dopant of one conductivity type instead of silicide or titanium nitride.
- a polycrystalline silicon layer not only makes a low-resistance contact to the highly doped source zone of one conductivity type and to the semiconductor substrate, but also has a useful ohmic contact to the highly doped zone of the other conductivity type in the so-called "body" region of the FET.
- the doping of the highly doped zone of the other conductivity type should be so high that a pn junction m occurs in the polycrystalline silicon layer forming the highly conductive layer during the diffusion out during the production process.
- Highly doped pn junctions have an ohmic characteristic, particularly in polycrystalline silicon.
- FIG. 1 shows a section through a first exemplary embodiment of the inventive FET with source-substrate connection
- FIG. 2 shows a section through a second exemplary embodiment of the FET according to the invention with a source-substrate connection, it being indicated in particular where possible direct wafer bond g surfaces are located,
- FIG. 3 shows a diagram to explain a method for producing the FET according to the invention with a source-substrate connection
- FIG. 4 shows a section through a third exemplary embodiment of the FET according to the invention with source-substrate connection, deep-etched gate trenches being provided here in order to make the FET suitable for higher voltages,
- FIG. 5 shows a section through a fourth exemplary embodiment of the FET according to the invention with a source-substrate connection, a strongly short-circuited “body” zone being present here,
- FIG. 6 shows a section through a fifth exemplary embodiment of the FET according to the invention with a source-substrate connection, it being shown here how a plurality of FETs have a common source.
- FIG. 7 shows a section through a sixth exemplary embodiment of the FET according to the invention with a source-substrate connection, the gate fillings here being provided with hat-like structures,
- FIG. 8 is a diagram explaining how to fabricate a source-lead FET according to a seventh embodiment of the present invention.
- FIG. 9 shows a section through an eighth exemplary embodiment of the FET according to the invention with a source-substrate connection, an advantageous edge termination being illustrated here, and
- FIG. 10 shows a section through a ninth exemplary embodiment of the FET according to the invention with source-substrate connection, the position of a pn junction in a highly conductive layer made of polycrystalline silicon being illustrated here.
- Fig. 1 shows a highly conductive silicon substrate 1, which serves as the source S in the FET, which can be grounded.
- the silicon substrate 1 can optionally also consist of several layers which are produced by epitaxy or diffusion.
- a metallization 2 is applied, which can optionally be provided with a cooling lug.
- the silicon substrate is 1 n + conductive, that is to say of the first conductivity type.
- the conductivity types can also be reversed.
- a semiconductor layer 3 is applied to the surface of the silicon substrate 1 opposite the metallization 2 by wafer bonding.
- This semiconductor layer 3 is also referred to as the first semiconductor wafer, while the silicon substrate 1 forms a second semiconductor wafer.
- the semiconductor layer 3 has an n-type silicon region 4, the n + -leioning drain zones 5 of the surface opposite to the silicon substrate 1 are introduced.
- Opposite the silicon substrate 1 are a p-type semiconductor zone 6, which can be provided with a p + -leioning zone 7.
- trenches 8 are introduced by etching the silicon of the semiconductor layer 3 and filled with an insulating layer 9 made of silicon dioxide and n + -le ⁇ tendem polycrystalline silicon 10. This polycrystalline silicon 10 forms gate electrode G.
- n + -lective source zones 11 are provided, so that the p-type semiconductor zone 6 forms the "body" area of the FET.
- Dram zones 5 are connected to a metallization 12, which represents drain electrode D.
- a highly conductive layer 13 is applied as a short-circuit layer between the source zones 11 and the p + -leioning regions 7 and as a bond layer to the silicon substrate 1.
- This highly conductive layer preferably consists of a silicide or titanium nitride.
- the layer 13 thus makes approximately or full ohmic contact with the n + and p + or p-conducting zones, such as the source zones 11, the p + -lective region 7 and the silicon substrate 1. temperature-resistant, in order to be able to survive subsequent process steps after it has been applied, and enables wafer bonding between the first semiconductor wafer composed in particular of the silicon semiconductor layer 3 and the silicon substrate 1.
- poly- silicon or a material can be selected which m its properties similar to silicide, titanium nitride and n + -le ⁇ tendem polycrystalline silicon.
- FIG. 2 shows a second exemplary embodiment of the FET according to the invention with a source-substrate connection, although here the p + -lefting region 7 is omitted.
- Possible connection areas for the direct wafer bonding are the areas 14 and 15 of the highly conductive layer 13. If the area 14 is selected, the highly conductive layer 13 is applied to the first semiconductor wafer with the semiconductor layer 3, in order to then em direct wafer bonding with the silicon substrate 1 to carry out. If, on the other hand, the area 15 is selected, the highly conductive layer 13 is first applied to the silicon substrate 1 in order to then carry out the wafer bonding with the first semiconductor wafer or the semiconductor layer 3.
- FIG. 3 illustrates how a possible adjustment can be carried out in the FET according to the invention: before the wafer Bonding the first semiconductor wafer with, in particular, the silicon semiconductor layer 3, pyramidal trenches 16 m of the first semiconductor wafer are produced by anisotropic etching. These trenches 16 are then completely or partially filled with n + -le ⁇ tendem polycrystalline silicon 17. Pyramid tips 18, which appear after the wafer bonding of the first semiconductor wafer 3 to the semiconductor substrate 1 and a thin grinding of the first semiconductor wafer, then serve as alignment marks for the subsequent introduction of the trenches in the so-called "trench process block". It should be noted that m F g. 3 these trenches 8 with the insulating layer 9 and the fillings 10 have already been shown, although the corresponding structures are only created after the direct wafer bonding has been carried out (cf. the double arrow 19).
- the first semiconductor wafer made of n-conducting silicon is first provided with the p-conducting semiconductor zone 6 by means of epitaxy or diffusion.
- the n + -lecting source zones 11 are then introduced, and then the previously highly polished surface is provided with the highly conductive layer 13 serving as a short-circuit layer.
- the highly conductive layer 13 can also be applied to the silicon substrate 1.
- the semiconductor wafer in particular from the semiconductor layer 3, is thinned and smoothed, as is necessary for the trench etching and further preparation.
- the trenches 8 with the insulating layer 9 and the polycrystalline silicon 10 are then created.
- the dramatic zones 5 are produced and the metallization 12 is applied for the dramatic zones 5.
- FIG. 4 shows a third exemplary embodiment of the FET according to the invention, the gate trenches 8 being deeply etched here, which is particularly expedient for operation with higher voltages.
- layer thickness of the semiconductor substrate 1 approximately 200 ⁇ m
- layer thickness of the highly conductive layer 13 approximately 0.01 ⁇ m
- thickness of the source zone 11 below the trench 8 approximately 1 to 3 ⁇ m
- layer thickness of the semiconductor zone 6 of the other conductivity type approximately 2 to 5 ⁇ m
- layer thickness of the semiconductor layer 3 with the n-type region and the p-type semiconductor zone 6 approximately 5 to 10 ⁇ m
- thickness or penetration depth of the drain zone 5 less than 1 ⁇ m layer thickness of the metallization 12 about 3 ⁇ m.
- the distance between the individual trenches 8 can be approximately 5 ⁇ m.
- FIG. 5 shows a further, fourth exemplary embodiment of the FET according to the invention, which has a strongly short-circuited “body” zone, in that the semiconductor zone 6 is highly doped with an area 20 with p + m and is less doped in the actual channel area 21. Otherwise, this exemplary embodiment corresponds to the exemplary embodiment of FIG. 2.
- FIG. 6 shows an exemplary embodiment similar to FIG. 5, but in which several FETs are connected together with their gate electrodes, while increasing the dielectric strength the edge of a gate electrode is grounded.
- the FETs connected in parallel have a common source S here.
- FIG. 7 shows an exemplary embodiment similar to FIG. 2, in which the polycrystalline silicon 10 above the trench 8 has a hat-like structure 22, so that the polycrystalline silicon 10 extends by means of this structure 22 over the edge of the trench 8.
- the resulting field distribution improves the dielectric strength of the FET.
- silicide or titanium nitride for the highly conductive layer 13.
- exemplary embodiments are to be presented which preferably have n * -lectant polyconducting silicon for this highly conductive layer 13, which is now used as a layer 23 is used. It should be emphasized, however, that n + conductive polycrystalline silicon can also be used for the layer 13 in the exemplary embodiments in FIGS. 1 to 7, while the following exemplary embodiments in FIGS. 8 to 10 also contain silicide or titanium nitride for the highly conductive layer 23 can provide.
- FIG. 8 thus shows an exemplary embodiment similar to FIG. 1, but in which an n + -lecting polycrystalline silicon layer 23 is provided instead of the highly conductive layer 13 made of silicide or titanium nitride or a similar material, with which the direct wafer bonding with the silicon substrate 1 is carried out (cf. the double arrow 19).
- FIG. 9 shows an exemplary embodiment similar to FIG. 8, in which an addition to FIG. 6 similar edge termination is provided by a grounded gate electrode.
- the possible bond areas 14 and 15 are entered in accordance with the exemplary embodiment of FIG. 2.
- FIG. 10 shows an exemplary embodiment similar to FIG. 8, it being shown here that the p + -containing region 7 is preferably so highly doped that the pn junction 24 formed by diffusion during the manufacturing process is in the region of the polycrystalline Silicon of the highly conductive layer 23 runs. Highly doped pn junctions in polycrystalline silicon have an ohmic characteristic, which is advantageous in the present case.
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Abstract
Description
FET mit Source-SubstratanschlußFET with source-substrate connection
Die vorliegende Erfindung betrifft einen FET (Feldeffekttransistor) mit Source-Substratanschluß ("Source-Down-FET" ) und Graben-Gate, bei dem:The present invention relates to an FET (field effect transistor) with a source-substrate connection ("source-down-FET") and a trench gate, in which:
- eine Drainzone des einen Leitfähigkeitstyps an einer Oberfläche einer auf einem Halbleitersubstrat des einen Leitfähigkeitstyps angeordneten Halbleiterschicht des einen Leitfähigkeitstyps vorgesehen ist,a drain zone of the one conductivity type is provided on a surface of a semiconductor layer of the one conductivity type arranged on a semiconductor substrate of the one conductivity type,
- Graben-Gate im wesentlichen die Halbleiterschicht durchsetzt,Trench gate essentially penetrates the semiconductor layer,
- am Ende des Grabens an der anderen Oberfläche der Halbleiterschicht eine Sourcezone des einen Leitfähigkeitstyps vorgesehen ist, unda source zone of one conductivity type is provided at the end of the trench on the other surface of the semiconductor layer, and
- im Gebiet neben dem Graben an der anderen Oberfläche der Halbleiterschicht eine Halbleiterzone des anderen Leitfähigkeitstyps vorgesehen ist, deren Oberfläche zusammen mit der Oberfläche der Sourcezone die andere Oberfläche der Halbleiterschicht bildet.a semiconductor zone of the other conductivity type is provided in the area next to the trench on the other surface of the semiconductor layer, the surface of which, together with the surface of the source zone, forms the other surface of the semiconductor layer.
FETs mit Source-Substratanschluß haben, was ihre Kühlung anbelangt, beträchtliche Vorteile, da diese über das auf 0 Volt Spannung gelegte Halbleitersubstrat aus Silizium erfolgen kann. So ist es beispielsweise möglich, einen FET mit Source- Substratanschluß direkt auf die Karosserie eines Fahrzeuges aufzuschrauben, wodurch für eine hervorragende Wärmeabfuhr gesorgt ist.FETs with a source-substrate connection have considerable advantages in terms of their cooling, since this can be done via the semiconductor substrate made of silicon, which is at 0 volt. For example, it is possible to screw an FET with a source-substrate connection directly onto the body of a vehicle, which ensures excellent heat dissipation.
In der US 5 023 196 A ist ein MOSFET mit Source-Substratanschluß und Graben-Gate beschrieben, bei dem auf einem Halbleitersubstrat des einen Leitfähigkeitstyps durch Epitaxie eine erste Halbleiterschicht des anderen Leitfahigkeitstyps sowie eine zweite Halbleiterschicht des einen Leitfahigkeitstyps aufgetragen sind, m die ein Graben für die Gate-Elektrode bis zum Halbleitersubstrat geatzt wird. Der Graben ist mit einer Isolierschicht ausgekleidet und mit einer Gateelektrode versehen. Auf der dem Graben gegenüberliegenden Oberflache des Halbleitersubstrates ist eine Sourceelektrode angeordnet, wahrend im Bereich der Halbleiterschicht des einen Leitfahigkeitstyps über einem hochdotierten Gebiet des einen Leitfahigkeitstyps eine Drainelektrode angebracht ist.US Pat. No. 5,023,196 A describes a MOSFET with a source-substrate connection and a trench gate, in which epitaxy occurs on a semiconductor substrate of one conductivity type a first semiconductor layer of the other conductivity type and a second semiconductor layer of the one conductivity type are applied, m a trench for the gate electrode is etched down to the semiconductor substrate. The trench is lined with an insulating layer and provided with a gate electrode. A source electrode is arranged on the surface of the semiconductor substrate opposite the trench, while a drain electrode is arranged in the region of the semiconductor layer of the one conductivity type over a highly doped region of the one conductivity type.
Gerade m letzter Zeit hat sich das sogenannte "Waferbonden", bei dem zwei Halbleiterscheiben, von denen eine auch als Substrat bezeichnet werden kann, miteinander verbunden werden, als besonders zweckmäßig für die Herstellung von Halb- leiterbauelementen und integrierten Schaltungen erwiesen. Wird nun ein FET mit Source-Substratanschluß gewünscht, der durch Waferbonden hergestellt ist, so ist die Gestaltung der Verbindungsschicht zwischen den beiden Scheiben und insbesondere der Kurzschluß zwischen der im unteren Bereich des Grabens vorgesehenen Sourcezone und der Halbleiterzone des anderen Leitfahigkeitstyps, der sogenannten "body-Zone", problematisch.Recently, so-called "wafer bonding", in which two semiconductor wafers, one of which can also be referred to as a substrate, are connected to one another, has proven to be particularly expedient for the production of semiconductor components and integrated circuits. If an FET with a source-substrate connection is now desired, which is produced by wafer bonding, then the design of the connection layer between the two disks and in particular the short circuit between the source zone provided in the lower region of the trench and the semiconductor zone of the other conductivity type, the so-called "body" Zone ", problematic.
Es ist daher Aufgabe der vorliegenden Erfindung, einen FET mit Source-Substratanschluß und Graben-Gate zu schaffen, der durch Waferbonden herstellbar ist.It is therefore an object of the present invention to provide an FET with a source-substrate connection and a trench gate that can be produced by wafer bonding.
Diese Aufgabe wird bei einem FET der eingangs genannten Art erfmdungsgemaß gelost durch eine vergrabene hochleitende Schicht zwischen der anderen Oberflache der Halbleiterschicht und dem Halbleitersubstrat. Diese hochleitende Schicht, die beispielsweise aus Silizid oder Titannitrid bestehen kann, stellt einen annähernd oder vollen ohmschen Kontakt sowohl mit der Sourcezone als auch mit der Halbleiterschicht des an- deren Leitfähigkeitstyps her, ist gegenüber hohen Temperaturen beständig, um durch die nachfolgenden Prozeßschritte zur Fertigung des FETs nicht beeinträchtigt zu werden, und erlaubt ohne weiteres ein Waferbonden, indem ein Halbleitersubstrat und eine Halbleiterschicht an ihren Bondflächen mittels der hochleitenden Schicht, die auf eine dieser Bondflächen aufgetragen ist, miteinander verbunden werden.In the case of an FET of the type mentioned at the outset, this object is achieved according to the invention by a buried highly conductive layer between the other surface of the semiconductor layer and the semiconductor substrate. This highly conductive layer, which can consist, for example, of silicide or titanium nitride, makes approximately or full ohmic contact both with the source zone and with the semiconductor layer of the other their conductivity type is resistant to high temperatures, so as not to be affected by the subsequent process steps for the production of the FET, and allows wafer bonding by placing a semiconductor substrate and a semiconductor layer on their bonding surfaces by means of the highly conductive layer which is on one of these bonding surfaces is applied to be connected.
Anstelle eines Suizides oder von Titannitrid kann auch eine aus polykristallinem Silizium bestehende Schicht verwendet werden, wobei das polykristalline Silizium mit Dotierstoff des einen Leitfähigkeitstyps dotiert ist. Dabei wird die Halbleiterzone des anderen Leitfähigkeitstyps vorzugsweise so hoch dotiert, daß der pn-Übergang in der polykristallinen hochleitenden Schicht verläuft.Instead of a suicide or titanium nitride, a layer consisting of polycrystalline silicon can also be used, the polycrystalline silicon being doped with dopant of one conductivity type. The semiconductor zone of the other conductivity type is preferably so highly doped that the pn junction runs in the polycrystalline highly conductive layer.
Das Halbleitersubstrat, auf dem die Halbleiterschicht durch Direktbonden angebracht wird, besteht aus hochleitendem Silizium oder aus mehreren Silizium-Schichten.The semiconductor substrate, on which the semiconductor layer is applied by direct bonding, consists of highly conductive silicon or of several silicon layers.
Wie bereits oben angedeutet wurde, kann die Wafer-Bondflache zwischen dem Halbleitersubstrat und der hochleitenden Schicht oder zwischen der Halbleiterschicht und der hochleitenden Schicht verlaufen. Im ersten Fall ist die hochleitende Schicht zunächst auf die Halbleiterschicht aufgetragen, so daß die mit der hochleitenden Schicht versehene Halbleiterschicht mit dem Halbleitersubstrat wafergebondet wird. Im letzteren Fall ist die hochleitende Schicht auf dem Halbleitersubstrat angeordnet, so daß die Halbleiterschicht auf das mit der hochleitenden Schicht versehene Halbleitersubstrat wafergebondet wird.As already indicated above, the wafer bonding area can run between the semiconductor substrate and the highly conductive layer or between the semiconductor layer and the highly conductive layer. In the first case, the highly conductive layer is first applied to the semiconductor layer, so that the semiconductor layer provided with the highly conductive layer is wafer-bonded to the semiconductor substrate. In the latter case, the highly conductive layer is arranged on the semiconductor substrate, so that the semiconductor layer is wafer-bonded to the semiconductor substrate provided with the highly conductive layer.
Typische Abmessungen für die jeweiligen Schichtdicken betragen für die Halbleiterschicht 5 bis 10 μm, für die Drainzone unter 1 μm, für die hochleitende Schicht etwa 0, 01 μm, für das Halbleitersubstrat 50 bis 200 μm, für die Halbleiterzone des anderen Leitfahigkeitstyps 2 bis 5 μm, für die Sourcezone 1 bis 3 μm und für die Drain-Metallisierung 1 bis 5 μm, insbesondere 3 μm.Typical dimensions for the respective layer thicknesses are 5 to 10 μm for the semiconductor layer, less than 1 μm for the drain zone and approximately 0.01 μm for the highly conductive layer the semiconductor substrate 50 to 200 μm, 2 to 5 μm for the semiconductor zone of the other conductivity type, 1 to 3 μm for the source zone and 1 to 5 μm, in particular 3 μm, for the drain metallization.
Die Halbleiterzone des anderen Leitfahigkeitstyps ist vorzugsweise in dem an die hochleitende Schicht angrenzenden Gebiet hochdotiert.The semiconductor zone of the other conductivity type is preferably heavily doped in the region adjacent to the highly conductive layer.
Weiterhin können mehrere Gates parallel geschaltet werden, wobei zur Erhöhung der Spannungsfestigkeit des Randes eine am Rand gelegene Gateelektrode geerdet ist. Ebenfalls zur Steigerung der Spannungsfestigkeit können polykπstallme Silizi- u -Fullungen der Gates im Bereich einer auf der Halbleiterschicht angeordneten Isolierschicht hutartige seitliche Ausdehnungen haben, die für einen Feldverlauf sorgen, der die Spannungsfestigkeit verbessert.Furthermore, several gates can be connected in parallel, with a gate electrode located at the edge being grounded to increase the dielectric strength of the edge. Likewise to increase the dielectric strength, low-poly silicon fillings of the gates in the region of an insulating layer arranged on the semiconductor layer can have hat-like lateral expansions which ensure a field profile which improves the dielectric strength.
Das Halbleitersubstrat kann aus monokπstallinem Silizium oder auch aus polykristallmem Silizium bestehen, das mit Dotierstoff des einen Leitfahigkeitstyps dotiert ist.The semiconductor substrate can consist of monocrystalline silicon or else of polycrystalline silicon which is doped with dopant of the one conductivity type.
Bevorzugte Verfahren zum Herstellen des erfmdungsgemaßen fest mit Source-Substratanschluß und Graben-Gate zeichnen sich dadurch aus, daß entweder eine mit der hochleitenden Schicht versehene Halbleiterscheibe mit dem Halbleitersubstrat wafergebondet wird, oder daß das mit der hochleitenden Schicht versehene Halbleitersubstrat mit der Halbleiterscheibe wafergebondet wird. Bei beiden Verfahren werden sodann nach dem Wafer-Bonden m üblicher Weise die einzelnen Dotier- und Atzschritte vorgenommen:Preferred methods for producing the source substrate connection and trench gate according to the invention are characterized in that either a semiconductor wafer provided with the highly conductive layer is wafer-bonded to the semiconductor substrate, or that the semiconductor substrate provided with the highly conductive layer is wafer-bonded to the semiconductor wafer. In both methods, the individual doping and etching steps are then carried out in the usual way after wafer bonding:
Zunächst wird eine erste Halbleiterscheibe des einen Leitfahigkeitstyps durch Epitaxie oder Diffusion mit einer Zone des anderen Leitfahigkeitstyps versehen. Sodann werden m diese Scheibe hochdotierte Gebiete des einen Leitfahigkeitstyps eingebracht, die die Sourcezone bilden sollen. Nach Flachpo- lieren der der Sourcezone gegenüberliegenden Oberflache dieser ersten Halbleiterscheibe wird auf diese die hochleitende Schicht als Kurzschlußschicht zwischen der Sourcezone und der Halbleiterzone des anderen Leitfahigkeitstyps ("body"-Be- reich) aufgebracht und das Waferbonden mit einer zweiten Scheibe als Substrat durchgeführt.First, a first semiconductor wafer of one conductivity type is provided with a zone of the other conductivity type by epitaxy or diffusion. Then m become these Disc of highly doped areas of the one conductivity type introduced, which are to form the source zone. After the surface of this first semiconductor wafer, which is opposite the source zone, has been polished flat, the highly conductive layer is applied to it as a short-circuit layer between the source zone and the semiconductor zone of the other conductivity type (“body” region) and the wafer bonding is carried out with a second wafer as the substrate.
Wie bereits oben angemerkt wurde, muß die hochleitende Schicht nicht auf der ersten Halbleiterscheibe vorgesehen werden. Sie kann vielmehr auch auf der zweiten Halbleiterscheibe angeordnet sein.As already noted above, the highly conductive layer does not have to be provided on the first semiconductor wafer. Rather, it can also be arranged on the second semiconductor wafer.
Für die hochleitende Schicht ist wesentlich, daß diese einen annähernd oder vollen ohmschen Kontakt gleichermaßen zu hoch- leitenden Schichten des einen und des anderen Leitfahigkeitstyps zu erzeugen vermag, hochtemperaturbestandig ist, um nachfolgende Prozeßschritte überleben zu können, und ein Di- rekt-Waferbonden zwischen den beiden Halbleiterscheiben, von denen eine die Halbleiterschicht und die andere das Halbleitersubstrat bilden, ermöglicht.It is essential for the highly conductive layer that it is able to produce approximately or full ohmic contact equally with highly conductive layers of the one and the other conductivity type, is resistant to high temperatures in order to be able to survive subsequent process steps, and direct wafer bonding between the two enables two semiconductor wafers, one of which forms the semiconductor layer and the other the semiconductor substrate.
Nach dem Bonden der beiden Halbleiterscheiben kann die die Halbleiterschicht bildende erste Halbleiterscheibe verdünnt und geglättet werden, wie dies für die Grabenatzung und weitere Praparation zweckmäßig ist. Sodann wird Grabengate geatzt, die Drainzonen werden durch Diffusion oder Implantation eingebracht, und schließlich wird eine Metallisierung aus beispielsweise Aluminium aufgetragen.After the two semiconductor wafers have been bonded, the first semiconductor wafer forming the semiconductor layer can be thinned and smoothed, as is expedient for trench etching and further preparation. Trench gate is then etched, the drain zones are introduced by diffusion or implantation, and finally a metallization of, for example, aluminum is applied.
Als letzter Prozeßblock kann die zweite Halbleiterscheibe, die das Halbleitersubstrat bildet, verdünnt und metallisiert werden, wobei beispielsweise eine Kuhlfahne aufgebracht werden kann . Da die Justierung zwischen den beiden Halbleiterscheiben zueinander vor deren Bonden von großer Bedeutung ist, können durch anisotropes Atzen beispielsweise m der ersten Halbleiterscheibe pyramidenförmig Graben hergestellt und mit poly- kristallmem Silizium teilweise oder ganz gefüllt werden, das mit Dotierstoff des einen Leitfahigkeitstyps hochdotiert ist. Die Pyramidenspitzen, die nach dem Waferbonden und Dunn- schleifen der ersten Halbleiterscheibe erscheinen, können dann als Justiermarken m dem Prozeßblock eingesetzt werden, m welchem die Graben geatzt werden.As the last process block, the second semiconductor wafer, which forms the semiconductor substrate, can be thinned and metallized, it being possible, for example, to apply a cooling lug. Since the adjustment between the two semiconductor wafers with respect to one another before their bonding is of great importance, pyramid-shaped trenches can be produced, for example, in the first semiconductor wafer by anisotropic etching and partially or completely filled with polycrystalline silicon which is highly doped with dopant of the one conductivity type. The pyramid tips that appear after wafer bonding and thin grinding of the first semiconductor wafer can then be used as alignment marks in the process block with which the trenches are etched.
Es wurde bereits erwähnt, daß Silizid oder Titannitrid besonders bevorzugte Materialien für die hochleitende Schicht sind.It has already been mentioned that silicide or titanium nitride are particularly preferred materials for the highly conductive layer.
Es ist aber auch möglich, anstelle von Silizid oder Titanni- tπd eine polykristallme Siliziumschicht, die mit Dotierstoff des einen Leitfahigkeitstyps hochdotiert ist, zu verwenden. Eine solche polykristallme Siliziumschicht stellt nicht nur einen niederohmigen Kontakt zu der hochdotierten Sourcezone des einen Leitfahigkeitstyps und zu dem Halbleitersubstrat her, sondern weist auch einen brauchbaren ohm- schen Kontakt zu der hochdotierten Zone des anderen Leitfahigkeitstyps im sogenannten "body"-Bereιch des FETs auf. Die Dotierung der hochdotierten Zone des anderen Leitfahigkeitstyps sollte dabei so hoch sein, daß bei der Ausdiffusion wahrend des Herstellungsverfahrens ein pn-Ubergang m der die hochleitende Schicht bildenden polykristallinen Siliziumschicht entsteht. Hochdotierte pn-Ubergange weisen namlich im polykristallinen Silizium eine ohmsche Charakteristik auf.However, it is also possible to use a polycrystalline silicon layer which is heavily doped with dopant of one conductivity type instead of silicide or titanium nitride. Such a polycrystalline silicon layer not only makes a low-resistance contact to the highly doped source zone of one conductivity type and to the semiconductor substrate, but also has a useful ohmic contact to the highly doped zone of the other conductivity type in the so-called "body" region of the FET. The doping of the highly doped zone of the other conductivity type should be so high that a pn junction m occurs in the polycrystalline silicon layer forming the highly conductive layer during the diffusion out during the production process. Highly doped pn junctions have an ohmic characteristic, particularly in polycrystalline silicon.
Die Verwendung von hochdotiertem polykπstallinem Silizium des einen Leitfahigkeitstyps für die hochleitende Schicht ist besonders vorteilhaft, da sie einfach und mit blichen Herstellungsmethoden realisiert werden kann.The use of highly doped Polykπstallinem silicon of the one conductivity type for the highly conductive layer is Particularly advantageous, since it can be implemented easily and using customary manufacturing methods.
Nachfolgend wird die Erfindung anhand der Zeichnungen naher erläutert. Es zeigen:The invention is explained in more detail below with reference to the drawings. Show it:
Fig. 1 einen Schnitt durch ein erstes Ausfuhrungs- beispiel des erfmdungsgemaßen FETs mit Source-Substratanschluß,1 shows a section through a first exemplary embodiment of the inventive FET with source-substrate connection,
Fig. 2 einen Schnitt durch ein zweites Ausfuhrungs- beispiel des erfmdungsgemaßen FETs mit Source-Substratanschluß, wobei insbesondere angegeben ist, wo mögliche Direkt-Waferbond g- Oberflachen gelegen sind,2 shows a section through a second exemplary embodiment of the FET according to the invention with a source-substrate connection, it being indicated in particular where possible direct wafer bond g surfaces are located,
Fig. 3 eine Darstellung zur Erläuterung eines Verfahrens zum Herstellen des erfmdungsgemaßen FETs mit Source-Substratanschluß,3 shows a diagram to explain a method for producing the FET according to the invention with a source-substrate connection,
Fig. 4 einen Schnitt durch ein drittes Ausfuhrungs- beispiel des erfmdungsgemaßen FETs mit Source-Substratanschluß, wobei hier tiefgeatzte Gate-Graben vorgesehen sind, um den FET für höhere Spannungen geeignet zu machen,4 shows a section through a third exemplary embodiment of the FET according to the invention with source-substrate connection, deep-etched gate trenches being provided here in order to make the FET suitable for higher voltages,
Fig. 5 einen Schnitt durch ein viertes Ausfuhrungs- beispiel des erfmdungsgemaßen FETs mit Source-Substratanschluß, wobei hier eine stark kurzgeschlossene "body"-Zone vorliegt,5 shows a section through a fourth exemplary embodiment of the FET according to the invention with a source-substrate connection, a strongly short-circuited “body” zone being present here,
Fig. 6 einen Schnitt durch ein fünftes Ausfuhrungs- beispiel des erfmdungsgemaßen FETs mit Source-Substratanschluß, wobei hier gezeigt ist, wie mehrere FETs bei gemeinsamer Source pa- O 99/369646 shows a section through a fifth exemplary embodiment of the FET according to the invention with a source-substrate connection, it being shown here how a plurality of FETs have a common source. O 99/36964
8 rallelgeschaltet werden können und die Randstruktur zu gestalten ist,8 can be connected in parallel and the edge structure is to be designed,
Fig. 7 einen Schnitt durch ein sechstes Ausführungsbeispiel des erfindungsgemäßen FETs mit Source-Substratanschluß, wobei hier die Gatefüllungen mit hutartigen Strukturen versehen sind,7 shows a section through a sixth exemplary embodiment of the FET according to the invention with a source-substrate connection, the gate fillings here being provided with hat-like structures,
Fig. 8 eine Darstellung, die erläutert, wie ein FET mit Source-Substratanschluß gemäß einem siebenten Ausführungsbeispiel der vorliegenden Erfindung herzustellen ist,8 is a diagram explaining how to fabricate a source-lead FET according to a seventh embodiment of the present invention;
Fig. 9 einen Schnitt durch ein achtes Ausführungsbeispiel des erfindungsgemäßen FETs mit Source-Substratanschluß, wobei hier ein vorteilhafter Randabschluß veranschaulicht ist, und9 shows a section through an eighth exemplary embodiment of the FET according to the invention with a source-substrate connection, an advantageous edge termination being illustrated here, and
Fig. 10 einen Schnitt durch ein neuntes Ausführungsbeispiel des erfindungsgemäßen FETs mit Source-Substratanschluß, wobei hier die Lage eines pn-Überganges in einer hochleitenden Schicht aus polykristallinem Silizium veranschaulicht ist.10 shows a section through a ninth exemplary embodiment of the FET according to the invention with source-substrate connection, the position of a pn junction in a highly conductive layer made of polycrystalline silicon being illustrated here.
In den Figuren werden einander entsprechende Bauteile mit den gleichen Bezugszeichen versehen.In the figures, components which correspond to one another are provided with the same reference symbols.
Fig. 1 zeigt ein hochleitendes Siliziumsubstrat 1, das bei dem FET als Source S dient, welche geerdet werden kann. Das Siliziumsubstrat 1 kann gegebenenfalls auch aus mehreren Schichten bestehen, die durch Epitaxie oder Diffusion erzeugt sind. Auf der der Fig. 1 unteren Oberflache des Siliziumsubstra- tes 1 ist eine Metallisierung 2 aufgebracht, welche gegebenenfalls mit einer Kuhlfahne versehen werden kann.Fig. 1 shows a highly conductive silicon substrate 1, which serves as the source S in the FET, which can be grounded. The silicon substrate 1 can optionally also consist of several layers which are produced by epitaxy or diffusion. On the lower surface of FIG. 1 of the silicon substrate 1, a metallization 2 is applied, which can optionally be provided with a cooling lug.
Im vorliegenden Ausfuhrungsbeispiel und auch den folgenden Ausfuhrungsbeispielen ist das Siliziumsubstrat 1 n+-leιtend, also vom ersten Leitfahigkeitstyps. Selbstverständlich können jedoch auch die Leitfahigkeitstypen jeweils umgekehrt sein.In the present exemplary embodiment and also in the following exemplary embodiments, the silicon substrate is 1 n + conductive, that is to say of the first conductivity type. Of course, the conductivity types can also be reversed.
Auf der der Metallisierung 2 gegenüberliegenden Oberflache des Siliziumsubstrates 1 ist eine Halbleiterschicht 3 durch Wafer-Bonden aufgebracht. Diese Halbleiterschicht 3 wird auch als erste Halbleiterscheibe bezeichnet, wahrend das Siliziumsubstrat 1 eine zweite Halbleiterscheibe bildet. Die Halbleiterschicht 3 weist ein n-leitendes Siliziumgebiet 4 auf, das n+-leιtende Drainzonen 5 der zu dem Siliziumsubstrat 1 entgegengesetzten Oberflache eingebracht sind. Dem Siliziumsubstrat 1 gegenüber liegen eine p-leitende Halbleiterzone 6, die mit einer p+-leιtenden Zone 7 versehen sein kann.A semiconductor layer 3 is applied to the surface of the silicon substrate 1 opposite the metallization 2 by wafer bonding. This semiconductor layer 3 is also referred to as the first semiconductor wafer, while the silicon substrate 1 forms a second semiconductor wafer. The semiconductor layer 3 has an n-type silicon region 4, the n + -leioning drain zones 5 of the surface opposite to the silicon substrate 1 are introduced. Opposite the silicon substrate 1 are a p-type semiconductor zone 6, which can be provided with a p + -leioning zone 7.
Von der Oberseite der Halbleiterschicht 3 aus sind Graben 8 durch Atzen m das Silizium der Halbleiterschicht 3 eingebracht und mit einer Isolierschicht 9 aus Siliziumdioxid sowie n+-leιtendem polykristallmem Silizium 10 gefüllt. Dieses polykristallme Silizium 10 bildet Gateelektrode G.From the top of the semiconductor layer 3, trenches 8 are introduced by etching the silicon of the semiconductor layer 3 and filled with an insulating layer 9 made of silicon dioxide and n + -leιtendem polycrystalline silicon 10. This polycrystalline silicon 10 forms gate electrode G.
Im Bereich unterhalb der Graben 8 sind n+-leιtende Sourcezo- nen 11 vorgesehen, so daß die p-leitende Halbleiterzone 6 den "body"-Bereιch des FETs bildet.In the area below the trench 8, n + -lective source zones 11 are provided, so that the p-type semiconductor zone 6 forms the "body" area of the FET.
Die Dramzonen 5 sind mit einer Metallisierung 12 verbunden, die die Drainelektrode D darstellt.Dram zones 5 are connected to a metallization 12, which represents drain electrode D.
Auf die planare Oberflache der Sourcezonen 11 und des p+-leι- tenden Gebietes 7 bzw. der p-leitenden Halbleiterzone 6 ist eine hochleitende Schicht 13 als Kurzschlußschicht zwischen den Sourcezonen 11 und den p+-leιtenden Gebieten 7 sowie als Bondschicht zu dem Siliziumsubstrat 1 aufgebracht. Diese hochleitende Schicht besteht bevorzugter Weise aus einem Silizid oder aus Titannitrid. Die Schicht 13 stellt so einen annähernd oder vollen ohmschen Kontakt zu den n+- und p+- bzw. p-leitenden Zonen, wie den Sourcezonen 11, dem p+-leι- tenden Gebiet 7 und dem Siliziumsubstrat 1 her, ist hochtem- peraturbestandig, um nach ihrem Auftragen nachfolgende Prozeßschritte überleben zu können, und ermöglicht das Waferbonden zwischen der ersten Halbleiterscheibe aus insbesondere der Silizium-Halbleiterschicht 3 und dem Siliziumsubstrat 1.On the planar surface of the source zones 11 and of the p + -lecting region 7 or of the p-type semiconductor zone 6 a highly conductive layer 13 is applied as a short-circuit layer between the source zones 11 and the p + -leioning regions 7 and as a bond layer to the silicon substrate 1. This highly conductive layer preferably consists of a silicide or titanium nitride. The layer 13 thus makes approximately or full ohmic contact with the n + and p + or p-conducting zones, such as the source zones 11, the p + -lective region 7 and the silicon substrate 1. temperature-resistant, in order to be able to survive subsequent process steps after it has been applied, and enables wafer bonding between the first semiconductor wafer composed in particular of the silicon semiconductor layer 3 and the silicon substrate 1.
Für die hochleitende Schicht 13 kann auch n+-leιtendes poly- kristallmes Silizium oder ein Material gewählt werden, das m seinen Eigenschaften ähnlich zu Silizid, Titannitrid und n+-leιtendem polykristallinem Silizium ist.For the highly conductive layer 13 and n + -leιtendes kristallmes poly- silicon or a material can be selected which m its properties similar to silicide, titanium nitride and n + -leιtendem polycrystalline silicon.
Fig. 2 zeigt em zweites Ausfuhrungsbeispiel des erfmdungs- gemaßen FETs mit Source-Substratanschluß, wobei hier allerdings das p+-leιtende Gebiet 7 weggelassen ist.FIG. 2 shows a second exemplary embodiment of the FET according to the invention with a source-substrate connection, although here the p + -lefting region 7 is omitted.
Mögliche Verbmdungsflachen für das Direkt-Waferbonden sind die Flachen 14 und 15 der hochleitenden Schicht 13. Wird die Flache 14 gewählt, so wird die hochleitende Schicht 13 auf die erste Halbleiterscheibe mit der Halbleiterschicht 3 aufgetragen, um sodann em Direkt-Waferbonden mit dem Siliziumsubstrat 1 durchzufuhren. Wird dagegen die Flache 15 gewählt, so wird zunächst die hochleitende Schicht 13 auf das Siliziumsubstrat 1 aufgetragen, um anschließend das Waferbonden mit der ersten Halbleiterscheibe bzw. der Halbleiterschicht 3 vorzunehmen.Possible connection areas for the direct wafer bonding are the areas 14 and 15 of the highly conductive layer 13. If the area 14 is selected, the highly conductive layer 13 is applied to the first semiconductor wafer with the semiconductor layer 3, in order to then em direct wafer bonding with the silicon substrate 1 to carry out. If, on the other hand, the area 15 is selected, the highly conductive layer 13 is first applied to the silicon substrate 1 in order to then carry out the wafer bonding with the first semiconductor wafer or the semiconductor layer 3.
Fig. 3 veranschaulicht, wie eine mögliche Justierung bei dem erfmdungsgemaßen FET vorgenommen werden kann: vor dem Wafer- bonden der ersten Halbleiterscheibe mit insbesondere der Si- lizium-Halbleiterschicht 3 werden durch anisotropes Atzen pyramidenförmige Graben 16 m der ersten Halbleiterscheibe erzeugt. Diese Graben 16 werden sodann mit n+-leιtendem poly- kristallmem Silizium 17 ganz oder teilweise aufgefüllt. Pyramidenspitzen 18, die nach dem Waferbonden der ersten Halbleiterscheibe 3 mit dem Halbleitersubstrat 1 und einem Dunn- schleifen der ersten Halbleiterscheibe erscheinen, dienen dann als Justiermarken für das nachfolgende Einbringen der Graben im sogenannten "Trench-Prozeßblock" . Es sei angemerkt, daß m F g. 3 diese Graben 8 mit der Isolierschicht 9 und den Füllungen 10 bereits dargestellt sind, obwohl die entsprechenden Strukturen erst nach Durchfuhren des Direkt-Waferbon- dens (vgl. den Doppelpfeil 19) erstellt werden.3 illustrates how a possible adjustment can be carried out in the FET according to the invention: before the wafer Bonding the first semiconductor wafer with, in particular, the silicon semiconductor layer 3, pyramidal trenches 16 m of the first semiconductor wafer are produced by anisotropic etching. These trenches 16 are then completely or partially filled with n + -leιtendem polycrystalline silicon 17. Pyramid tips 18, which appear after the wafer bonding of the first semiconductor wafer 3 to the semiconductor substrate 1 and a thin grinding of the first semiconductor wafer, then serve as alignment marks for the subsequent introduction of the trenches in the so-called "trench process block". It should be noted that m F g. 3 these trenches 8 with the insulating layer 9 and the fillings 10 have already been shown, although the corresponding structures are only created after the direct wafer bonding has been carried out (cf. the double arrow 19).
Bei der Herstellung des FETs wird zunächst die erste Halbleiterscheibe aus n-leitendem Silizium mittels Epitaxie oder Diffusion mit der p-leitenden Halbleiterzone 6 versehen. Sodann werden die n+-leιtenden Sourcezonen 11 eingebracht, und anschließend wird die zuvor hochpolierte Oberflache mit der als Kurzschlußschicht dienenden hochleitenden Schicht 13 versehen.During the production of the FET, the first semiconductor wafer made of n-conducting silicon is first provided with the p-conducting semiconductor zone 6 by means of epitaxy or diffusion. The n + -lecting source zones 11 are then introduced, and then the previously highly polished surface is provided with the highly conductive layer 13 serving as a short-circuit layer.
Anschließend folgt das Waferbonden, wobei nochmals anzumerken ist, daß die hochleitende Schicht 13 auch auf dem Siliziumsubstrat 1 angebracht sein kann. Nach dem Waferbonden wird die Halbleiterscheibe aus insbesondere der Halbleiterschicht 3 verdünnt und geglättet, wie dies für die Grabenatzung und weitere Praparation erforderlich ist. Sodann werden die Graben 8 mit der Isolierschicht 9 und dem polykristall em Silizium 10 erstellt. Schließlich werden noch die Dramzonen 5 hergestellt und die Metallisierung 12 wird für die Dramzonen 5 aufgebracht. O 99/36964This is followed by wafer bonding, it being noted once again that the highly conductive layer 13 can also be applied to the silicon substrate 1. After the wafer bonding, the semiconductor wafer, in particular from the semiconductor layer 3, is thinned and smoothed, as is necessary for the trench etching and further preparation. The trenches 8 with the insulating layer 9 and the polycrystalline silicon 10 are then created. Finally, the dramatic zones 5 are produced and the metallization 12 is applied for the dramatic zones 5. O 99/36964
1212th
Fig. 4 zeigt em drittes Ausfuhrungsbeispiel des erfmdungs- gemaßen FETs, wobei hier die Gate-Graben 8 tiefgeatzt sind, was besonders für einen Betrieb mit höheren Spannungen zweckmäßig ist.4 shows a third exemplary embodiment of the FET according to the invention, the gate trenches 8 being deeply etched here, which is particularly expedient for operation with higher voltages.
Als zweckmäßige Abmessungen können für dieses Ausfuhrungsbeispiel wie auch für die übrigen Ausfuhrungsbeispiele die folgenden Werte angegeben werden: Schichtdicke des Halbleiter- substrates 1 etwa 200 μm, Schichtdicke der hochleitenden Schicht 13 etwa 0, 01 μ , Dicke der Sourcezone 11 unterhalb des Grabens 8 etwa 1 bis 3 μm, Schichtdicke der Halbleiterzone 6 des anderen Leitfahigkeitstyps etwa 2 bis 5 μm, Schichtdicke der Halbleiterschicht 3 mit dem n-leitenden Gebiet und der p-leitenden Halbleiterzone 6 etwa 5 bis 10 μm, Dicke bzw. Eindringtiefe der Drainzone 5 weniger als 1 μm, Schichtdicke der Metallisierung 12 etwa 3 μm.The following values can be specified as expedient dimensions for this exemplary embodiment as well as for the other exemplary embodiments: layer thickness of the semiconductor substrate 1 approximately 200 μm, layer thickness of the highly conductive layer 13 approximately 0.01 μm, thickness of the source zone 11 below the trench 8 approximately 1 to 3 μm, layer thickness of the semiconductor zone 6 of the other conductivity type approximately 2 to 5 μm, layer thickness of the semiconductor layer 3 with the n-type region and the p-type semiconductor zone 6 approximately 5 to 10 μm, thickness or penetration depth of the drain zone 5 less than 1 μm, layer thickness of the metallization 12 about 3 μm.
Der Abstand zwischen den einzelnen Graben 8 kann etwa 5 μm betragen.The distance between the individual trenches 8 can be approximately 5 μm.
Die obigen Werte stellen lediglich Richtgroßen dar und sollen die vorliegende Erfindung m keiner Weise einschranken. Vielmehr können diese Werte jeweils nach oben und unten m beiden Richtungen über- bzw. unterschritten werden.The above values are only indicative and are not intended to limit the present invention in any way. Rather, these values can be exceeded or fallen below in both directions.
Fig. 5 zeigt em weiteres, viertes Ausfuhrungsbeispiel des erf dungsgemaßen FETs, das eine stark kurzgeschlossene "body"-Zone hat, indem hier die Halbleiterzone 6 mit p+ m einem Gebiet 20 hochdotiert und im eigentlichen Kanalgebiet 21 niedriger dotiert ist. Im übrigen entspricht dieses Ausfuhrungsbeispiel dem Ausfuhrungsbeispiel der Fig. 2.5 shows a further, fourth exemplary embodiment of the FET according to the invention, which has a strongly short-circuited “body” zone, in that the semiconductor zone 6 is highly doped with an area 20 with p + m and is less doped in the actual channel area 21. Otherwise, this exemplary embodiment corresponds to the exemplary embodiment of FIG. 2.
Fig. 6 zeigt em zu Fig. 5 ahnliches Ausfuhrungsbeispiel, bei dem aber mehrere FETs mit ihren Gateelektroden zusammengeschaltet sind, wahrend zur Erhöhung der Spannungsfestigkeit des Randes eine Gateelektrode an Masse gelegt ist. Die parallel geschalteten FETs haben hier eine gemeinsame Source S.FIG. 6 shows an exemplary embodiment similar to FIG. 5, but in which several FETs are connected together with their gate electrodes, while increasing the dielectric strength the edge of a gate electrode is grounded. The FETs connected in parallel have a common source S here.
Fig. 7 zeigt e zu Fig. 2 ähnliches Ausfuhrungsbeispiel, bei dem das polykristallme Silizium 10 oberhalb der Graben 8 eine hutartige Struktur 22 hat, so daß sich das polykristallme Silizium 10 mittels dieser Struktur 22 über den Rand der Graben 8 erstreckt. Durch die dadurch erreichte Feldlmienver- teilung wird die Spannungsfestigkeit des FETs verbessert.FIG. 7 shows an exemplary embodiment similar to FIG. 2, in which the polycrystalline silicon 10 above the trench 8 has a hat-like structure 22, so that the polycrystalline silicon 10 extends by means of this structure 22 over the edge of the trench 8. The resulting field distribution improves the dielectric strength of the FET.
Wahrend bei den Ausfuhrungsbeispielen der Fig. 1 bis 7 bevorzugt Silizid oder Titannitrid für die hochleitende Schicht 13 verwendet wird, sollen im folgenden noch Ausfuhrungsbeispiele vorgestellt werden, die bevorzugt n*-leιtendes polykπstalli- nes Silizium für diese hochleitende Schicht 13, die nunmehr als Schicht 23 bezeichnet ist, verwenden. Es sei aber betont, daß auch in den Ausfuhrungsbeispielen der Fig. 1 bis 7 n+- leitendes polykristallmes Silizium für die Schicht 13 eingesetzt werden kann, wahrend selbstverständlich auch die folgenden Ausfuhrungsbeispiele der Fig. 8 bis 10 Silizid bzw. Titannitrid für die hochleitende Schicht 23 vorsehen können.1 to 7, preference is given to using silicide or titanium nitride for the highly conductive layer 13. In the following, exemplary embodiments are to be presented which preferably have n * -lectant polyconducting silicon for this highly conductive layer 13, which is now used as a layer 23 is used. It should be emphasized, however, that n + conductive polycrystalline silicon can also be used for the layer 13 in the exemplary embodiments in FIGS. 1 to 7, while the following exemplary embodiments in FIGS. 8 to 10 also contain silicide or titanium nitride for the highly conductive layer 23 can provide.
Fig. 8 zeigt also em zu Fig. 1 ähnliches Ausfuhrungsbeispiel, bei dem aber anstelle der hochleitenden Schicht 13 aus Silizid oder Titannitrid oder einem ahnlichen Material eine n+-leιtende polykristallme Siliziumschicht 23 vorgesehen ist, mit welcher das Direkt-Waferbonden mit dem Siliziumsubstrat 1 vorgenommen wird (vgl. den Doppelpfeil 19).8 thus shows an exemplary embodiment similar to FIG. 1, but in which an n + -lecting polycrystalline silicon layer 23 is provided instead of the highly conductive layer 13 made of silicide or titanium nitride or a similar material, with which the direct wafer bonding with the silicon substrate 1 is carried out (cf. the double arrow 19).
Fig. 9 zeigt ein zu Fig. 8 ahnliches Ausfuhrungsbeispiel, bei dem zusätzlich em zu F g. 6 ahnlicher Randabschluß durch eine geerdete Gateelektrode vorgesehen ist. Außerdem sind die möglichen Bondflachen 14 und 15 entsprechend zu dem Ausfuhrungsbeispiel von Fig. 2 eingetragen. Schließlich zeigt Fig. 10 ein zu Fig. 8 ähnliches Ausführungsbeispiel, wobei hier gezeigt ist, daß das p+-leitende Gebiet 7 vorzugsweise so hoch dotiert ist, daß der durch Ausdiffusion während des Herstellverfahrens gebildete pn-Über- gang 24 im Bereich des polykristallinen Siliziums der hochleitenden Schicht 23 verläuft. Hochdotierte pn-Übergänge in polykristallinem Silizium weisen nämlich eine ohmsche Charakteristik auf, was im vorliegenden Fall vorteilhaft ist. FIG. 9 shows an exemplary embodiment similar to FIG. 8, in which an addition to FIG. 6 similar edge termination is provided by a grounded gate electrode. In addition, the possible bond areas 14 and 15 are entered in accordance with the exemplary embodiment of FIG. 2. Finally, FIG. 10 shows an exemplary embodiment similar to FIG. 8, it being shown here that the p + -containing region 7 is preferably so highly doped that the pn junction 24 formed by diffusion during the manufacturing process is in the region of the polycrystalline Silicon of the highly conductive layer 23 runs. Highly doped pn junctions in polycrystalline silicon have an ohmic characteristic, which is advantageous in the present case.
Claims
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP53662499A JP2001515663A (en) | 1998-01-15 | 1998-12-15 | FET with source substrate contact and trench gate |
| EP98966210A EP0966764A1 (en) | 1998-01-15 | 1998-12-15 | Source-down fet |
| KR10-1999-7008381A KR100443976B1 (en) | 1998-01-15 | 1998-12-15 | Source-down fet |
| US09/395,302 US6124612A (en) | 1998-01-15 | 1999-09-13 | FET with source-substrate connection and method for producing the FET |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19801313.2 | 1998-01-15 | ||
| DE19801313A DE19801313C2 (en) | 1998-01-15 | 1998-01-15 | FET with source-substrate connection |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US09/395,302 Continuation US6124612A (en) | 1998-01-15 | 1999-09-13 | FET with source-substrate connection and method for producing the FET |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1999036964A1 true WO1999036964A1 (en) | 1999-07-22 |
Family
ID=7854702
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE1998/003683 WO1999036964A1 (en) | 1998-01-15 | 1998-12-15 | Source-down fet |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP0966764A1 (en) |
| JP (1) | JP2001515663A (en) |
| KR (1) | KR100443976B1 (en) |
| DE (1) | DE19801313C2 (en) |
| TW (1) | TW430994B (en) |
| WO (1) | WO1999036964A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1122796A3 (en) * | 2000-02-04 | 2002-03-20 | Infineon Technologies AG | Vertical semiconductor device with a source-down-design and corresponding fabrication process |
| JP2002083962A (en) * | 1999-10-21 | 2002-03-22 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10042226B4 (en) * | 2000-08-28 | 2014-12-24 | Infineon Technologies Ag | Source-down power MOSFET and method of making the same |
| US6455905B1 (en) * | 2001-04-05 | 2002-09-24 | Ericsson Inc. | Single chip push-pull power transistor device |
| DE10239310B4 (en) * | 2002-08-27 | 2005-11-03 | Infineon Technologies Ag | Method for producing an electrically conductive connection between a first and a second buried semiconductor layer |
| JP2005150686A (en) * | 2003-10-22 | 2005-06-09 | Sharp Corp | Semiconductor device and manufacturing method thereof |
| US7947569B2 (en) | 2008-06-30 | 2011-05-24 | Infineon Technologies Austria Ag | Method for producing a semiconductor including a foreign material layer |
| US7943449B2 (en) | 2008-09-30 | 2011-05-17 | Infineon Technologies Austria Ag | Semiconductor component structure with vertical dielectric layers |
| US8519473B2 (en) * | 2010-07-14 | 2013-08-27 | Infineon Technologies Ag | Vertical transistor component |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62159468A (en) * | 1986-01-08 | 1987-07-15 | Tdk Corp | semiconductor equipment |
| US5023196A (en) * | 1990-01-29 | 1991-06-11 | Motorola Inc. | Method for forming a MOSFET with substrate source contact |
| DE19606105A1 (en) * | 1995-02-21 | 1996-08-22 | Fuji Electric Co Ltd | Back-source power MOSFET for power integrated circuit or discrete module |
| EP0833392A2 (en) * | 1996-09-19 | 1998-04-01 | Siemens Aktiengesellschaft | Field effect controllable vertical semiconductor device |
-
1998
- 1998-01-15 DE DE19801313A patent/DE19801313C2/en not_active Expired - Fee Related
- 1998-12-15 JP JP53662499A patent/JP2001515663A/en not_active Ceased
- 1998-12-15 EP EP98966210A patent/EP0966764A1/en not_active Withdrawn
- 1998-12-15 WO PCT/DE1998/003683 patent/WO1999036964A1/en not_active Application Discontinuation
- 1998-12-15 KR KR10-1999-7008381A patent/KR100443976B1/en not_active Expired - Fee Related
- 1998-12-23 TW TW087121524A patent/TW430994B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62159468A (en) * | 1986-01-08 | 1987-07-15 | Tdk Corp | semiconductor equipment |
| US5023196A (en) * | 1990-01-29 | 1991-06-11 | Motorola Inc. | Method for forming a MOSFET with substrate source contact |
| DE19606105A1 (en) * | 1995-02-21 | 1996-08-22 | Fuji Electric Co Ltd | Back-source power MOSFET for power integrated circuit or discrete module |
| EP0833392A2 (en) * | 1996-09-19 | 1998-04-01 | Siemens Aktiengesellschaft | Field effect controllable vertical semiconductor device |
Non-Patent Citations (1)
| Title |
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| PATENT ABSTRACTS OF JAPAN vol. 011, no. 396 (E - 568) 24 December 1987 (1987-12-24) * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002083962A (en) * | 1999-10-21 | 2002-03-22 | Fuji Electric Co Ltd | Semiconductor device and method of manufacturing the same |
| EP1122796A3 (en) * | 2000-02-04 | 2002-03-20 | Infineon Technologies AG | Vertical semiconductor device with a source-down-design and corresponding fabrication process |
| US6576953B2 (en) | 2000-02-04 | 2003-06-10 | Infineon Technologies Ag | Vertical semiconductor component with source-down design and corresponding fabrication method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000076284A (en) | 2000-12-26 |
| DE19801313C2 (en) | 2001-01-18 |
| KR100443976B1 (en) | 2004-08-09 |
| TW430994B (en) | 2001-04-21 |
| JP2001515663A (en) | 2001-09-18 |
| DE19801313A1 (en) | 1999-07-22 |
| EP0966764A1 (en) | 1999-12-29 |
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