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WO1999036964A1 - Transistor a effet de champ comportant une connexion source-substrat - Google Patents

Transistor a effet de champ comportant une connexion source-substrat Download PDF

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Publication number
WO1999036964A1
WO1999036964A1 PCT/DE1998/003683 DE9803683W WO9936964A1 WO 1999036964 A1 WO1999036964 A1 WO 1999036964A1 DE 9803683 W DE9803683 W DE 9803683W WO 9936964 A1 WO9936964 A1 WO 9936964A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
layer
fet according
highly conductive
zone
Prior art date
Application number
PCT/DE1998/003683
Other languages
German (de)
English (en)
Inventor
Jenö Tihanyi
Wolfgang Werner
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to JP53662499A priority Critical patent/JP2001515663A/ja
Priority to EP98966210A priority patent/EP0966764A1/fr
Priority to KR10-1999-7008381A priority patent/KR100443976B1/ko
Publication of WO1999036964A1 publication Critical patent/WO1999036964A1/fr
Priority to US09/395,302 priority patent/US6124612A/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/664—Inverted VDMOS transistors, i.e. source-down VDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

Definitions

  • the present invention relates to an FET (field effect transistor) with a source-substrate connection (“source-down-FET”) and a trench gate, in which:
  • a drain zone of the one conductivity type is provided on a surface of a semiconductor layer of the one conductivity type arranged on a semiconductor substrate of the one conductivity type,
  • Trench gate essentially penetrates the semiconductor layer
  • a source zone of one conductivity type is provided at the end of the trench on the other surface of the semiconductor layer, and
  • a semiconductor zone of the other conductivity type is provided in the area next to the trench on the other surface of the semiconductor layer, the surface of which, together with the surface of the source zone, forms the other surface of the semiconductor layer.
  • FETs with a source-substrate connection have considerable advantages in terms of their cooling, since this can be done via the semiconductor substrate made of silicon, which is at 0 volt. For example, it is possible to screw an FET with a source-substrate connection directly onto the body of a vehicle, which ensures excellent heat dissipation.
  • US Pat. No. 5,023,196 A describes a MOSFET with a source-substrate connection and a trench gate, in which epitaxy occurs on a semiconductor substrate of one conductivity type a first semiconductor layer of the other conductivity type and a second semiconductor layer of the one conductivity type are applied, m a trench for the gate electrode is etched down to the semiconductor substrate.
  • the trench is lined with an insulating layer and provided with a gate electrode.
  • a source electrode is arranged on the surface of the semiconductor substrate opposite the trench, while a drain electrode is arranged in the region of the semiconductor layer of the one conductivity type over a highly doped region of the one conductivity type.
  • wafer bonding in which two semiconductor wafers, one of which can also be referred to as a substrate, are connected to one another, has proven to be particularly expedient for the production of semiconductor components and integrated circuits. If an FET with a source-substrate connection is now desired, which is produced by wafer bonding, then the design of the connection layer between the two disks and in particular the short circuit between the source zone provided in the lower region of the trench and the semiconductor zone of the other conductivity type, the so-called “body” Zone ", problematic.
  • this object is achieved according to the invention by a buried highly conductive layer between the other surface of the semiconductor layer and the semiconductor substrate.
  • This highly conductive layer which can consist, for example, of silicide or titanium nitride, makes approximately or full ohmic contact both with the source zone and with the semiconductor layer of the other their conductivity type is resistant to high temperatures, so as not to be affected by the subsequent process steps for the production of the FET, and allows wafer bonding by placing a semiconductor substrate and a semiconductor layer on their bonding surfaces by means of the highly conductive layer which is on one of these bonding surfaces is applied to be connected.
  • a layer consisting of polycrystalline silicon can also be used, the polycrystalline silicon being doped with dopant of one conductivity type.
  • the semiconductor zone of the other conductivity type is preferably so highly doped that the pn junction runs in the polycrystalline highly conductive layer.
  • the semiconductor substrate on which the semiconductor layer is applied by direct bonding, consists of highly conductive silicon or of several silicon layers.
  • the wafer bonding area can run between the semiconductor substrate and the highly conductive layer or between the semiconductor layer and the highly conductive layer.
  • the highly conductive layer is first applied to the semiconductor layer, so that the semiconductor layer provided with the highly conductive layer is wafer-bonded to the semiconductor substrate.
  • the highly conductive layer is arranged on the semiconductor substrate, so that the semiconductor layer is wafer-bonded to the semiconductor substrate provided with the highly conductive layer.
  • Typical dimensions for the respective layer thicknesses are 5 to 10 ⁇ m for the semiconductor layer, less than 1 ⁇ m for the drain zone and approximately 0.01 ⁇ m for the highly conductive layer the semiconductor substrate 50 to 200 ⁇ m, 2 to 5 ⁇ m for the semiconductor zone of the other conductivity type, 1 to 3 ⁇ m for the source zone and 1 to 5 ⁇ m, in particular 3 ⁇ m, for the drain metallization.
  • the semiconductor zone of the other conductivity type is preferably heavily doped in the region adjacent to the highly conductive layer.
  • a gate electrode located at the edge being grounded to increase the dielectric strength of the edge.
  • low-poly silicon fillings of the gates in the region of an insulating layer arranged on the semiconductor layer can have hat-like lateral expansions which ensure a field profile which improves the dielectric strength.
  • the semiconductor substrate can consist of monocrystalline silicon or else of polycrystalline silicon which is doped with dopant of the one conductivity type.
  • Preferred methods for producing the source substrate connection and trench gate according to the invention are characterized in that either a semiconductor wafer provided with the highly conductive layer is wafer-bonded to the semiconductor substrate, or that the semiconductor substrate provided with the highly conductive layer is wafer-bonded to the semiconductor wafer. In both methods, the individual doping and etching steps are then carried out in the usual way after wafer bonding:
  • a first semiconductor wafer of one conductivity type is provided with a zone of the other conductivity type by epitaxy or diffusion. Then m become these Disc of highly doped areas of the one conductivity type introduced, which are to form the source zone.
  • the highly conductive layer is applied to it as a short-circuit layer between the source zone and the semiconductor zone of the other conductivity type (“body” region) and the wafer bonding is carried out with a second wafer as the substrate.
  • the highly conductive layer does not have to be provided on the first semiconductor wafer. Rather, it can also be arranged on the second semiconductor wafer.
  • the highly conductive layer It is essential for the highly conductive layer that it is able to produce approximately or full ohmic contact equally with highly conductive layers of the one and the other conductivity type, is resistant to high temperatures in order to be able to survive subsequent process steps, and direct wafer bonding between the two enables two semiconductor wafers, one of which forms the semiconductor layer and the other the semiconductor substrate.
  • the first semiconductor wafer forming the semiconductor layer can be thinned and smoothed, as is expedient for trench etching and further preparation.
  • Trench gate is then etched, the drain zones are introduced by diffusion or implantation, and finally a metallization of, for example, aluminum is applied.
  • the second semiconductor wafer which forms the semiconductor substrate, can be thinned and metallized, it being possible, for example, to apply a cooling lug. Since the adjustment between the two semiconductor wafers with respect to one another before their bonding is of great importance, pyramid-shaped trenches can be produced, for example, in the first semiconductor wafer by anisotropic etching and partially or completely filled with polycrystalline silicon which is highly doped with dopant of the one conductivity type. The pyramid tips that appear after wafer bonding and thin grinding of the first semiconductor wafer can then be used as alignment marks in the process block with which the trenches are etched.
  • silicide or titanium nitride are particularly preferred materials for the highly conductive layer.
  • a polycrystalline silicon layer which is heavily doped with dopant of one conductivity type instead of silicide or titanium nitride.
  • a polycrystalline silicon layer not only makes a low-resistance contact to the highly doped source zone of one conductivity type and to the semiconductor substrate, but also has a useful ohmic contact to the highly doped zone of the other conductivity type in the so-called "body" region of the FET.
  • the doping of the highly doped zone of the other conductivity type should be so high that a pn junction m occurs in the polycrystalline silicon layer forming the highly conductive layer during the diffusion out during the production process.
  • Highly doped pn junctions have an ohmic characteristic, particularly in polycrystalline silicon.
  • FIG. 1 shows a section through a first exemplary embodiment of the inventive FET with source-substrate connection
  • FIG. 2 shows a section through a second exemplary embodiment of the FET according to the invention with a source-substrate connection, it being indicated in particular where possible direct wafer bond g surfaces are located,
  • FIG. 3 shows a diagram to explain a method for producing the FET according to the invention with a source-substrate connection
  • FIG. 4 shows a section through a third exemplary embodiment of the FET according to the invention with source-substrate connection, deep-etched gate trenches being provided here in order to make the FET suitable for higher voltages,
  • FIG. 5 shows a section through a fourth exemplary embodiment of the FET according to the invention with a source-substrate connection, a strongly short-circuited “body” zone being present here,
  • FIG. 6 shows a section through a fifth exemplary embodiment of the FET according to the invention with a source-substrate connection, it being shown here how a plurality of FETs have a common source.
  • FIG. 7 shows a section through a sixth exemplary embodiment of the FET according to the invention with a source-substrate connection, the gate fillings here being provided with hat-like structures,
  • FIG. 8 is a diagram explaining how to fabricate a source-lead FET according to a seventh embodiment of the present invention.
  • FIG. 9 shows a section through an eighth exemplary embodiment of the FET according to the invention with a source-substrate connection, an advantageous edge termination being illustrated here, and
  • FIG. 10 shows a section through a ninth exemplary embodiment of the FET according to the invention with source-substrate connection, the position of a pn junction in a highly conductive layer made of polycrystalline silicon being illustrated here.
  • Fig. 1 shows a highly conductive silicon substrate 1, which serves as the source S in the FET, which can be grounded.
  • the silicon substrate 1 can optionally also consist of several layers which are produced by epitaxy or diffusion.
  • a metallization 2 is applied, which can optionally be provided with a cooling lug.
  • the silicon substrate is 1 n + conductive, that is to say of the first conductivity type.
  • the conductivity types can also be reversed.
  • a semiconductor layer 3 is applied to the surface of the silicon substrate 1 opposite the metallization 2 by wafer bonding.
  • This semiconductor layer 3 is also referred to as the first semiconductor wafer, while the silicon substrate 1 forms a second semiconductor wafer.
  • the semiconductor layer 3 has an n-type silicon region 4, the n + -leioning drain zones 5 of the surface opposite to the silicon substrate 1 are introduced.
  • Opposite the silicon substrate 1 are a p-type semiconductor zone 6, which can be provided with a p + -leioning zone 7.
  • trenches 8 are introduced by etching the silicon of the semiconductor layer 3 and filled with an insulating layer 9 made of silicon dioxide and n + -le ⁇ tendem polycrystalline silicon 10. This polycrystalline silicon 10 forms gate electrode G.
  • n + -lective source zones 11 are provided, so that the p-type semiconductor zone 6 forms the "body" area of the FET.
  • Dram zones 5 are connected to a metallization 12, which represents drain electrode D.
  • a highly conductive layer 13 is applied as a short-circuit layer between the source zones 11 and the p + -leioning regions 7 and as a bond layer to the silicon substrate 1.
  • This highly conductive layer preferably consists of a silicide or titanium nitride.
  • the layer 13 thus makes approximately or full ohmic contact with the n + and p + or p-conducting zones, such as the source zones 11, the p + -lective region 7 and the silicon substrate 1. temperature-resistant, in order to be able to survive subsequent process steps after it has been applied, and enables wafer bonding between the first semiconductor wafer composed in particular of the silicon semiconductor layer 3 and the silicon substrate 1.
  • poly- silicon or a material can be selected which m its properties similar to silicide, titanium nitride and n + -le ⁇ tendem polycrystalline silicon.
  • FIG. 2 shows a second exemplary embodiment of the FET according to the invention with a source-substrate connection, although here the p + -lefting region 7 is omitted.
  • Possible connection areas for the direct wafer bonding are the areas 14 and 15 of the highly conductive layer 13. If the area 14 is selected, the highly conductive layer 13 is applied to the first semiconductor wafer with the semiconductor layer 3, in order to then em direct wafer bonding with the silicon substrate 1 to carry out. If, on the other hand, the area 15 is selected, the highly conductive layer 13 is first applied to the silicon substrate 1 in order to then carry out the wafer bonding with the first semiconductor wafer or the semiconductor layer 3.
  • FIG. 3 illustrates how a possible adjustment can be carried out in the FET according to the invention: before the wafer Bonding the first semiconductor wafer with, in particular, the silicon semiconductor layer 3, pyramidal trenches 16 m of the first semiconductor wafer are produced by anisotropic etching. These trenches 16 are then completely or partially filled with n + -le ⁇ tendem polycrystalline silicon 17. Pyramid tips 18, which appear after the wafer bonding of the first semiconductor wafer 3 to the semiconductor substrate 1 and a thin grinding of the first semiconductor wafer, then serve as alignment marks for the subsequent introduction of the trenches in the so-called "trench process block". It should be noted that m F g. 3 these trenches 8 with the insulating layer 9 and the fillings 10 have already been shown, although the corresponding structures are only created after the direct wafer bonding has been carried out (cf. the double arrow 19).
  • the first semiconductor wafer made of n-conducting silicon is first provided with the p-conducting semiconductor zone 6 by means of epitaxy or diffusion.
  • the n + -lecting source zones 11 are then introduced, and then the previously highly polished surface is provided with the highly conductive layer 13 serving as a short-circuit layer.
  • the highly conductive layer 13 can also be applied to the silicon substrate 1.
  • the semiconductor wafer in particular from the semiconductor layer 3, is thinned and smoothed, as is necessary for the trench etching and further preparation.
  • the trenches 8 with the insulating layer 9 and the polycrystalline silicon 10 are then created.
  • the dramatic zones 5 are produced and the metallization 12 is applied for the dramatic zones 5.
  • FIG. 4 shows a third exemplary embodiment of the FET according to the invention, the gate trenches 8 being deeply etched here, which is particularly expedient for operation with higher voltages.
  • layer thickness of the semiconductor substrate 1 approximately 200 ⁇ m
  • layer thickness of the highly conductive layer 13 approximately 0.01 ⁇ m
  • thickness of the source zone 11 below the trench 8 approximately 1 to 3 ⁇ m
  • layer thickness of the semiconductor zone 6 of the other conductivity type approximately 2 to 5 ⁇ m
  • layer thickness of the semiconductor layer 3 with the n-type region and the p-type semiconductor zone 6 approximately 5 to 10 ⁇ m
  • thickness or penetration depth of the drain zone 5 less than 1 ⁇ m layer thickness of the metallization 12 about 3 ⁇ m.
  • the distance between the individual trenches 8 can be approximately 5 ⁇ m.
  • FIG. 5 shows a further, fourth exemplary embodiment of the FET according to the invention, which has a strongly short-circuited “body” zone, in that the semiconductor zone 6 is highly doped with an area 20 with p + m and is less doped in the actual channel area 21. Otherwise, this exemplary embodiment corresponds to the exemplary embodiment of FIG. 2.
  • FIG. 6 shows an exemplary embodiment similar to FIG. 5, but in which several FETs are connected together with their gate electrodes, while increasing the dielectric strength the edge of a gate electrode is grounded.
  • the FETs connected in parallel have a common source S here.
  • FIG. 7 shows an exemplary embodiment similar to FIG. 2, in which the polycrystalline silicon 10 above the trench 8 has a hat-like structure 22, so that the polycrystalline silicon 10 extends by means of this structure 22 over the edge of the trench 8.
  • the resulting field distribution improves the dielectric strength of the FET.
  • silicide or titanium nitride for the highly conductive layer 13.
  • exemplary embodiments are to be presented which preferably have n * -lectant polyconducting silicon for this highly conductive layer 13, which is now used as a layer 23 is used. It should be emphasized, however, that n + conductive polycrystalline silicon can also be used for the layer 13 in the exemplary embodiments in FIGS. 1 to 7, while the following exemplary embodiments in FIGS. 8 to 10 also contain silicide or titanium nitride for the highly conductive layer 23 can provide.
  • FIG. 8 thus shows an exemplary embodiment similar to FIG. 1, but in which an n + -lecting polycrystalline silicon layer 23 is provided instead of the highly conductive layer 13 made of silicide or titanium nitride or a similar material, with which the direct wafer bonding with the silicon substrate 1 is carried out (cf. the double arrow 19).
  • FIG. 9 shows an exemplary embodiment similar to FIG. 8, in which an addition to FIG. 6 similar edge termination is provided by a grounded gate electrode.
  • the possible bond areas 14 and 15 are entered in accordance with the exemplary embodiment of FIG. 2.
  • FIG. 10 shows an exemplary embodiment similar to FIG. 8, it being shown here that the p + -containing region 7 is preferably so highly doped that the pn junction 24 formed by diffusion during the manufacturing process is in the region of the polycrystalline Silicon of the highly conductive layer 23 runs. Highly doped pn junctions in polycrystalline silicon have an ohmic characteristic, which is advantageous in the present case.

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  • Electrodes Of Semiconductors (AREA)
  • Element Separation (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

La présente invention concerne un transistor à effet de champ comportant une connexion source-substrat et une grille à tranchée (8), dans lequel une zone de drain (5) d'un premier type de conductivité est disposée sur une surface d'une couche de semi-conducteur (3) du premier type de conductivité disposée sur un substrat de semi-conducteur (1) du premier type de conductivité. La grille à tranchée (8) traverse pratiquement la couche de semi-conducteur (3), une zone de source (11) se trouvant à l'extrémité de la tranchée (8), sur l'autre surface de semi-conducteur (3), et une zone de semi-conducteur (6, 7) d'un second type de conductivité se trouvant dans la région adjacente à la tranchée (8), sur l'autre surface de la couche de semi-conducteur (3). La surface de ladite zone de semi-conducteur forme, avec la surface de la zone de source (11), l'autre surface de la couche de semi-conducteur (3).
PCT/DE1998/003683 1998-01-15 1998-12-15 Transistor a effet de champ comportant une connexion source-substrat WO1999036964A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP53662499A JP2001515663A (ja) 1998-01-15 1998-12-15 ソースサブストレートコンタクトとトレンチゲートを備えたｆｅｔ
EP98966210A EP0966764A1 (fr) 1998-01-15 1998-12-15 Transistor a effet de champ comportant une connexion source-substrat
KR10-1999-7008381A KR100443976B1 (ko) 1998-01-15 1998-12-15 소스-다운 ｆｅｔ
US09/395,302 US6124612A (en) 1998-01-15 1999-09-13 FET with source-substrate connection and method for producing the FET

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19801313.2 1998-01-15
DE19801313A DE19801313C2 (de) 1998-01-15 1998-01-15 FET mit Source-Substratanschluß

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/395,302 Continuation US6124612A (en) 1998-01-15 1999-09-13 FET with source-substrate connection and method for producing the FET

Publications (1)

Publication Number Publication Date
WO1999036964A1 true WO1999036964A1 (fr) 1999-07-22

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PCT/DE1998/003683 WO1999036964A1 (fr) 1998-01-15 1998-12-15 Transistor a effet de champ comportant une connexion source-substrat

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EP (1) EP0966764A1 (fr)
JP (1) JP2001515663A (fr)
KR (1) KR100443976B1 (fr)
DE (1) DE19801313C2 (fr)
TW (1) TW430994B (fr)
WO (1) WO1999036964A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1122796A3 (fr) * 2000-02-04 2002-03-20 Infineon Technologies AG Dispositif semi-conducteur vertical comportant une connexion source-substrat et procédé de fabrication correspondant
JP2002083962A (ja) * 1999-10-21 2002-03-22 Fuji Electric Co Ltd 半導体素子およびその製造方法

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Publication number Priority date Publication date Assignee Title
DE10042226B4 (de) * 2000-08-28 2014-12-24 Infineon Technologies Ag Source-Down-Leistungs-MOSFET und Verfahren zu dessen Herstellung
US6455905B1 (en) * 2001-04-05 2002-09-24 Ericsson Inc. Single chip push-pull power transistor device
DE10239310B4 (de) * 2002-08-27 2005-11-03 Infineon Technologies Ag Verfahren zur Herstellung einer elektrisch leitenden Verbindung zwischen einer ersten und einer zweiten vergrabenen Halbleiterschicht
JP2005150686A (ja) * 2003-10-22 2005-06-09 Sharp Corp 半導体装置およびその製造方法
US7947569B2 (en) 2008-06-30 2011-05-24 Infineon Technologies Austria Ag Method for producing a semiconductor including a foreign material layer
US7943449B2 (en) 2008-09-30 2011-05-17 Infineon Technologies Austria Ag Semiconductor component structure with vertical dielectric layers
US8519473B2 (en) * 2010-07-14 2013-08-27 Infineon Technologies Ag Vertical transistor component

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JPS62159468A (ja) * 1986-01-08 1987-07-15 Tdk Corp 半導体装置
US5023196A (en) * 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
DE19606105A1 (de) * 1995-02-21 1996-08-22 Fuji Electric Co Ltd Back-Source-MOSFET
EP0833392A2 (fr) * 1996-09-19 1998-04-01 Siemens Aktiengesellschaft Dispositif semi-conducteur vertical commandé par effet de champ

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62159468A (ja) * 1986-01-08 1987-07-15 Tdk Corp 半導体装置
US5023196A (en) * 1990-01-29 1991-06-11 Motorola Inc. Method for forming a MOSFET with substrate source contact
DE19606105A1 (de) * 1995-02-21 1996-08-22 Fuji Electric Co Ltd Back-Source-MOSFET
EP0833392A2 (fr) * 1996-09-19 1998-04-01 Siemens Aktiengesellschaft Dispositif semi-conducteur vertical commandé par effet de champ

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Title
PATENT ABSTRACTS OF JAPAN vol. 011, no. 396 (E - 568) 24 December 1987 (1987-12-24) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002083962A (ja) * 1999-10-21 2002-03-22 Fuji Electric Co Ltd 半導体素子およびその製造方法
EP1122796A3 (fr) * 2000-02-04 2002-03-20 Infineon Technologies AG Dispositif semi-conducteur vertical comportant une connexion source-substrat et procédé de fabrication correspondant
US6576953B2 (en) 2000-02-04 2003-06-10 Infineon Technologies Ag Vertical semiconductor component with source-down design and corresponding fabrication method

Also Published As

Publication number Publication date
KR20000076284A (ko) 2000-12-26
DE19801313C2 (de) 2001-01-18
KR100443976B1 (ko) 2004-08-09
TW430994B (en) 2001-04-21
JP2001515663A (ja) 2001-09-18
DE19801313A1 (de) 1999-07-22
EP0966764A1 (fr) 1999-12-29

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