WO2002007360A1

WO2002007360A1 - Receiver and method for carrying out an optical information transmission

Info

Publication number: WO2002007360A1
Application number: PCT/DE2001/002672
Authority: WO
Inventors: Reinhold Noe
Original assignee: Siemens Aktiengesellschaft
Priority date: 2000-07-17
Filing date: 2001-07-17
Publication date: 2002-01-24
Also published as: DE10035086A1

Abstract

The invention relates to a receiver for transmitting optical partial signals (OS1, OS2) using a polarization multiplex, comprising a separator/detector (SD), which provides electrical detected signals (ED1, ED2), and comprising decision elements (DDM1, DDM2) in which these electrical detected signals (ED1, ED2) are regenerated. The inventive receiver also comprises switches (SS1, SS2), which maintain these electrical detected signals (ED1, ED2) and relay the same as switched signals (ESD1, ESD2), and which are closed when a regenerated signal (DD11, DD12, bzw. DD21, DD22) corresponding to a transmit-side modulation signal (SDD11, SDD12, SDD21, SDD22) is logically zero. A controller (RG; RG1, RG2) is provided, which sets a mean value (EDS1, EDS2) of this switched signal (ESD1, ESD2) by means of a polarization transformer, which is contained in the separator/detector (SD), such that this electrical detected signal (ED1, ED2) as well corresponds as closely as possible to a logical zero.

Description

description

Receiver and method for optical information transmission

The invention relates to an arrangement and an associated method for optical information reception with polarization multiplex according to the preamble of independent claims 1 and 5.

Polarization multiplexing is used to increase the capacity of an optical transmission system.

In the conference proceedings of the European Conference on Optical Communications 1993, Montreux, Switzerland, pp. 401-404, contribution eP9.3, F. Heismann et al. , "Automatic Polarization Demultiplexer for

Polarization-Multiplexed Transmission Systems "describes an optical polarization multiplex transmission system. A major disadvantage in this embodiment of an optical transmission system is the regulation of a polarization transformer on the receiver side in such a way that the two polarization multiplex channels are divided between the two outputs of a downstream polarization beam splitter a correlation signal of the recovered clock with the received signal is formed and this is maximized by adjusting the polarization transformer The procedure according to the prior art has several disadvantages:

First of all, if a pure, AC-coupled pseudo-random sequence is specified, the correlation product disappears on average over time, which makes control difficult or impossible.

To distinguish the two polarization multiplex channels, different bit rates also had to be selected, which is not permitted in practice. Finally, a correlation product was axed for regulation. Because of the high demands on crosstalk in polarization multiplex systems, it would be more expedient to minimize a signal. For example, in the presence of polarization-dependent attenuation in the transmission system, the orthogonality of the transmitted polarizations is generally lost, so that maximizing a correlation product in such cases causes disturbing crosstalk.

The object of the invention is therefore to provide an arrangement and an associated method for optical information transmission by means of polarization multiplex, which avoid the disadvantages of the prior art as far as possible.

This object is achieved by an arrangement specified in claim 1 and by a method as specified in claim 5.

Advantageous further developments are specified in the subclaims.

The solution to the problem lies in measuring the crosstalk caused by the unwanted signal while receiving zeros of the desired signal of a receiver channel. For this purpose, the received signal is fed to a controller via a switch. This switch is opened while received ones of the desired signal, and closed when received zeros. The control signal obtained only disappears if a signal at the regenerator input does not simultaneously contain a portion of the signal to be regenerated by the other regenerator. The polarization controller is controlled by a control device so that the control signal disappears. In this case, each regenerator receives and regenerates only one polarization multiplex channel, which corresponds to the desired separation of the signals on the receiver side. The invention is explained in more detail using exemplary embodiments.

Show it

1 shows the basic structure of a transmission system with polarization multiplex, FIG. 2 shows a receiver according to the invention, FIG. 3 shows a separator / detector, FIG. 4 shows a vector diagram of linear polarization states, FIG. 5 shows an embodiment of part of the separator / detector, FIG. 6 shows a switch with logic module and low-pass filter, FIG. 7 shows a time diagram of signals occurring according to the invention.

Figure 1 shows the basic structure of a transmission system with polarization multiplex. On the transmission side, there are two optical transmitters TX1, TX2 which emit a first and a second optical partial signal OS1, 0S2 with mutually orthogonal polarizations. These are combined in a transmitter-side polarization beam splitter PBSS and can then be transmitted via an optical fiber LWL to a receiver RX with an input EI. Since the optical fiber generally the polarization does not preserve the difficulty of separating the two partial signals OS1, OS2 again. Instead of the polarization beam splitter PBSS on the transmission side, a simple optical directional coupler can also be used, which, however, leads to a loss of power and less well-defined

Orthogonality of the partial signals OS1, OS2 leads. The first and second optical transmitters TX1 and TX2 are modulated with first and second transmission-side modulation signals SDDll and possibly SDD12 or SDD21 and possibly SDD22. Each modulation signal on the transmission side can have two portions SDD11, SDD12 or SDD21, SDD22 interleaved in time division multiplex. According to FIG. 2, the receiver RX here consists of a separator / detector SD and downstream receiver electronics.

The separator / detector SD for polarization multiplex is shown in FIG. 3. The received optical partial signals are fed from the input EI to an endless polarization transformer PT which receives a first control signal ST1 and a second control signal ST2. Both the first control signal ST1 and the second control signal ST2 can consist of one or more signals. A polarizing element EPBS on the receiver side is attached to the output of the polarization transformer PT. This can be designed as a polarization beam splitter, which provides first and second signal components OUT1, OUT2 at its outputs. Ideally, the signal components OUT1, OUT2 should be the orthogonally polarized partial signals OS1 and OS2; however, these are only with a suitable setting of the polarization transformer PT and a compensator of polarization mode dispersion PMDC, which may be connected upstream. The signal components OUT1, OUT2 are detected in photodetectors PD11, PD21, which generate electrically detected signals EDI, ED2.

A compensator of polarization mode dispersion PMDC, called PMD compensator, as described, for example, in German patent applications 19841755.1 and 19830990.2 can also be provided in front of the polarization transformer PT. PMD compensator PMDC, polarization transformer PT and receiver-side polarizing element EPBS designed as a polarization beam splitter can be integrated on a substrate SUB consisting, for example, of lithium niobate. A PMD compensator coupler KPMDC can be present between the PMD compensator PMDC and the polarization transformer PT for decoupling part of the signals transported between these modules. Instead of the integrated structure, the PMD compensator PMDC could also be omitted, for example, and polarization transformer PT and receiver side as polar polarization element EPBS formed as a beam splitter as described in the conference proceedings of the European Conference on Optical Communications 1993, Montreux, Switzerland, pp. 401-404, article WeP9.3. Embodiments according to the subjects described in German patent applications 19858148.3, 19919576.5 are also possible.

The electrically detected signals ED1, ED2 are sent to decision-makers DDM1, DDM2. For operation at a data rate of e.g. 40Gb / s or higher, the decision makers DDM1, DDM2 are preferably designed as de ultiplexer decision makers, which have a decision maker function, but at the same time, e.g. Multiplex down to half the data rate. Such circuits are from the International J. of High Speed Electronics and Systems, Volume 9, 1998, No. 2, H.-M. Rein, "Si and SiGe bipolar ICs for 10 to 40 Gb / s optical-fiber TDM links", is known. It is expedient to take the clock signals CL1, CL2 required for the operation of the decision-makers DDM1, DDM2 from a common source it is also possible to take the clock signals CL1 and CL2 from different sources.

The decision-makers DDM1, DDM2, if they 1: 2-

Demu1tiplexfunktion have regenerated digital signals DDll, DD12 or DD21, DD22 available at their outputs. These are supplied to logic modules NOR1 and NOR2, which in the present exemplary embodiment are designed as NOR gates. A first logic signal SNOR1 or a second logic signal SNOR2 at their outputs are equal to one if both of the regenerated digital signals DD11, DD12 or DD21, DD22, DD22 resulting from 1: 2 demultiplexing are equal to zero. This is the case if an electrical detected signal ED1 or ED2 contains two consecutive logical zeros which originate from the modulation signals SDD11, SDD12 or SDD21, SDD22 on the transmission side. Non-zero signal values of an electrically detected signal ED1 or ED2 indicate crosstalk NS through the signals that actually should appear only in the other channel in the other electrically detected signal ED2 or ED1 and originate from the modulation signals SDD21, SDD22 or SDDll, SDD12 on the transmission side.

If the first logic signal SNOR1 or the second logic signal SNOR2 is equal to one, a first switch SSI or a second switch SS2 is closed, so that the first electrically detected signal ED1 or the second electrically detected signal ED2 is switched in a first Signal ESDI or a second switched signal ESD2 appears. The DC components of the switched signals ESDI, ESD2, which are possibly determined by low-pass filters Lll, L22, serve as the first control signal EDS1 and the second control signal EDS2. According to the invention, the first control signal EDS1 and the second control signal EDS2 correspond only to the crosstalk NS of the respectively undesired channel, that is to say signals which should only appear in the second electrically detected signal ED2 or in the first electrically detected signal ED1. Control signals EDS1, EDS2 are fed to a controller RG, which can consist of two controllers RG1 or RG2, which generate the control signals ST1 and possibly ST2.

So that the control works as described, a runtime adjustment must be guaranteed. In particular, the running times of the decision-makers DDM1 or DDM2 have to be delayed e.g. the electrically detected signals ED1 or ED2 are balanced up to the inputs of the switches SSI or SS2. In FIG. 2, this is done by delay lines L01 or L02, the first delayed signal ESI or the second delayed signal ES2 corresponding to the first electrically detected signal ED1 or the second electrically detected signal ED2. After passing through the switches SSI, SS2, there are switched signals ESDI, ESD2.

FIG. 7 shows the measurement of crosstalk NS according to the invention, which during transmitted zeros is caused by the desired channel is generated. This is crosstalk by the second partial signal OS2, while the first partial signal OS1 is to be received. Crosstalk NS, represented by hatched areas, increases the zero values of the first delayed signal ESI when the second partial signal OS2 corresponds to a logic one. Crosstalk during sent logical ones is not shown for the sake of clarity. The signals described above are shown first delayed signal ESI, DD11, DD12, first logic signal SN0R1, first switched signal ESDI during typical bit patterns as functions of time t. A symbol duration T is also shown. "0 ^W and" 1 "denote the levels of logical zeros and ones. The vertical axis is in each case an amplitude axis, for example for voltage or current. Deviating from the strictly rectangular-shaped signals of FIG. 7, the invention also functions when rounded edges Bandwidth limits occur.

FIG. 7 also applies analogously to the measurement of crosstalk in the second partial signal OS2 by the first partial signal OS1.

If the decision makers DDM1 and DDM2 generate inverted signals, logic modules NOR1 and NOR2 must each be AND gates. According to the invention, the switches SSI and SS2 are in turn only closed when there are two consecutive logical zeros in the electrically detected signal ED1 and ED2.

FIG. 6 shows a possible embodiment of the first switch SSI, which can also be used analogously for the second switch SS2. The decision signals DD11 and DD12 of a decision maker, who also executes demultiplexing at the same time, are fed to the bases of a first switching transistor TT1 and a second switching transistor TT2. Only if both decision signals DDll, DD12 are logic zeros, is a third transistor TT3, the base of which is set at a reference level P01 corresponding to the mean of the zeros and ones of DDll, DD12 and whose emitter is connected to the Emitter of the other two switching transistors TT1, TT2 is conductively connected, conductive and conducts a constant current IK to a differential amplifier DF, which thereby becomes functional and the first delayed signal ESI as its input signal in its differential form in its output signal, namely the difference between the collector currents reinforced by DF. This output signal is the first switched signal ESDI. A capacitance C in conjunction with load resistors Rl, R2, which are selected with the same resistance values, simultaneously realizes the first low-pass filter Lll, so that the differential output voltage of the differential amplifier DF is the desired first control signal EDS1. The positive supply voltage is U +.

If the circuit technology permits the construction of decision-makers directly at the symbol rate used, the decision-makers DDM1 or DDM2 are preferably designed as simple decision-makers without demultiplexing function, each with only one output signal DD11 or DD21. The logic modules NOR1 and NOR2, which were previously designed as NOR gates, become simple inverters or can be omitted entirely if the only remaining output signal DD11 or DD21 from such a decision maker DDM1 or DDM2 is in inverted form. The second transistor TT2 is then omitted in FIG.

In the case of a separator / detector SD according to FIG. 3 with a polarization beam splitter PBS, in principle it is sufficient to use only one, for example the first control signal EDS1, as the control signal; the second logic module NOR2, the second delay element L02, the second switch SS2, the second low-pass filter L22 and the second controller RG2 are then superfluous. Nevertheless, the use of both control signals EDS1, EDS2 is also preferable here; for this purpose they can be summed in a summer SU. The controllers RG1, RG2 are combined to form a common controller RG. The ones he created Control signals ST1, ST2 are sent to the separator / detector SD, where they control the polarization transformer PT.

The controllers RG1, RG2, RG minimize the control signal or signals EDS1, EDS2. This requires DC voltage coupling of the electrically detected signals ED1, ED2 to behind the switches SSI, SS2 and finally the provision of the control signals EDS1, EDS2. The result is a signal EDS1, EDS2 indicating the crosstalk NS in the respective channel. The polarization transformer PT is therefore advantageously set such that regenerated signals DD11, DD21, DD12, DD22 are available at the outputs of optimal quality and lowest bit error rates. These signals correspond to the modulation signals SDD11, SDD12, SDD21, SDD22, which are indicated by a "S" in front of them.

Additional quality signal winners and controllers RP1, RP2, which can also be combined to form a common assembly RP and which generate at least one control signal SP1, SP2, can be used as in the proc. 9th European Conference on Integrated Optics (ECIO'99), April 14-16, 1999, Turin, Italy, postdeadline-paper-Band, pp. 17-19, D. Sandel et al. , "Integrated-optical polarization or dispersion compensation for 6-ps, 40-Gb / s pulses", described can be used to control the PMD compensator PMDC.

In principle, the polarization transformer PT is constructed in exactly the same way as the PMD compensator PMDC, which is described in more detail in the literature just mentioned and simply represents the cascade of several mode converters as polarization transformers. The control signals of the controller RG are fed to the polarization transformer PT, while the control signals of the controller RP are fed to the PMD compensator PMDC.

By non-ideal multiplex in the transmitting polarization beam splitter PBSS on the transmitting side, or by polarization-independent dependent attenuation or amplification in the optical waveguide LWL can lead to reduced orthogonality of the received optical partial signals OS1, OS2. According to FIG. 4 and FIG. 5, in such cases it is expedient to use a polarization transformer PT1 or PT2 with a PMD compensator PMDCl or PMDC2 connected upstream and a downstream polarization beam splitter or polarizer PBS1 or PBS2 after passing through a power divider TE. In the case of linear polarizations, the polarization adjustments achieved according to the invention by the exemplary embodiment in FIG. 5 are outlined in FIG. 4; in FIG. 5, components KPMDC and PMDC are initially replaced by through connections, and PDPMDC, DANA and RPMDC are also omitted. The received partial signals OS1, OS2 are not polarized orthogonally to one another. However, the signal OUT1, which is transmitted by PBS1, is orthogonal to partial signal OS2, and OU 2, which is transmitted by PBS2, is orthogonal to partial signal OSl. The fact that partial signal OSl is not polarized identically with OUTl and partial signal OS2 is not polarized identically with OUT2 leads to a certain signal loss, which is however easier to bear than a strong crosstalk, which would result if partial signal OSl were identical to OUTl and Partial signal OS2 made identical to OUT2.

Further exemplary embodiments of the invention relate to the combination with methods and devices for compensating polarization mode dispersion (PMD). Minimal optical effort results if the control signals for PMDC in FIGS. 3 and 5 are derived from the two electrically detected signals ED1 and ED2. The disadvantage here is that the settings of PT, PTl, PT2 can also have an effect on the PMD compensation.

This can be avoided if an optical signal is branched off and detected before the polarizing elements PBS, PBS1, PBS2 are reached. From this, PMD distortions are then analyzed and minimized by setting PMDC, PMDCl, PMDC2. For this purpose, FIGS 5 each a coupler KPMDC, a photodetector PDPMDC connected to it, a distortion analyzer DANA, a controller RPMDC and a PMD compensator PMDC are provided. The components RP, RP1, RP2 in FIG. 2 are omitted and the components PMDCl, PMDC2 in FIG. 5 are replaced by through connections. This type of PMD compensation is in principle already known, for example from European patent application EP 0 909 045 A2 and from IEEE J. Lightwave Technology, 17 (1999) 9, pp. 1602-1616; however, what is new is their application to polarization multiplex signals.

The invention is suitable for the non-return-to-zero signal format (NRZ) as well as for the return-to-zero signal format (RZ) without restrictions.

List of reference symbols OSi (i = 1, 2) partial signals SDDij (j = 1, 2) transmission-side modulation signals TX1, TX2 optical transmitters PBSS transmission-side polarization beam splitter LWL fiber optic cable RX receiver EI input of the receiver SD separator / detector SPi control signals for PMD compensator (s)

RPi, RP controller for PMD compensator (s) STi control signals for polarization transformer (s)

RGi, RG controller for polarization transformer (s) EDi electrical detection signals

CLi clock signals

DDMi decision maker

DDij regenerated signals

LOi delay elements ESi delayed signals

SSi switch

ESDi switched signals

Lii low pass filter

EDSi control signals NORi logic modules

SNORi logic signals

PDil photodiodes

PBSi polarization beam splitters, polarizers

PT, PTi polarization transformers, mode converters

TE power divider

SUB, SUBi substrates

PMDC, PMDCi PMD compensators

OUTi outputs x, y coordinates for horizontal / vertical polarization

SU totalizer

Claims

claims

1. Method for transmitting optical partial signals (OS1, OS2) modulated by transmission-side modulation signals (SDD11, SDD21) by means of polarization multiplex, which are carried out in a separator / detector (SD) with polarization transformer (PT), a downstream polarizing element (PBS) and photodetectors ( PDll, PD21) are converted into electrical detected signals (EDl, ED2) and regenerated in decision-makers (DDMl, DDM2) to regenerated signals (DDll, DD21), characterized in that one of these electrically detected signals (EDl or ED2) derived delayed signal (ESI or ES2) is forwarded by a switch (SSI or SS2) as a switched signal (ESDI or ESD2) and as a control signal (EDS1 or EDS2) to a controller (RG; RGI or RG2), that this switch (SSI or SS2) is closed when a regenerated signal (DDll, DD12, or DD21, DD22) corresponding to a transmission-side modulation signal (SDDll, SDD12, or SDD21, SDD22) logi sch zero is that this controller (RG; RGI or RG2) sets this polarization transformer (PT; PT1 or PT2) so that this electrically detected signal (ED1 or ED2) corresponds as exactly as possible to a logic zero.

2. The method according to claim 1, characterized in that if this decider (DDM1 or DDM2) is simultaneously a demultiplexer, the multiple, time-nested transmission-side modulation signals (SDDll, SDD12 or SDD21, SDD22) corresponding regenerated signals (DDll, DD12 or DD21, DD22), this switch (SSI or SS2) is closed when all these regenerated signals (DD11, DD12 or DD21, DD22) correspond to logic zeros.

3rd Method according to claim 1 or 2, characterized in that that the crosstalk (NS) indicating direct component of this switched signal (ESDI or ESD2) determined by a low-pass filter (Lll or L22) is used as a control signal (EDS1 or EDS2).

4. The method according to any one of claims 1 to 3, characterized in that a delay comparison between the delayed signal (ESI or ES2) and an at least one received zero-indicating logic signal (SNORI or SNOR2) is carried out.

5. Receiver for the transmission of modulation signals (OSD, OSD) modulated by transmission-side modulation signals (SDD11, SDD21) by means of polarization multiplex, with a separator / detector (SD) which has a polarization transformer (PT), a downstream polarizing element (PBS) and Has photodetectors (PD11, PD21), which convert the optical partial signals (OS1, OS2) into electrically detected signals (ED1, ED2), with decision-makers (DDM1, DDM2), in which these electrically detected signals (ED1, ED2) into regenerated signals (DD11, DD21), characterized in that a switch (SSI or SS2) is provided, which receives a delayed signal (ESI or ES2) derived from one of these electrically detected signals (ED1 or ED2) and forwards it as a switched signal (ESDI or ESD2), which is closed when there is a lot of activity corresponding to a modulation signal (SDD11, SDD12, or SDD21, SDD22) on the transmission side generated signal (DD11, DD12, or DD21, DD22) is logic zero that a controller (RG; RGI or RG2) is provided, which receives a mean value of this switched signal (ESDI or ESD2) as control signal (EDS1 or EDS2) and sets this polarization transformer (PT; PTl or PT2) so that this electrically detected signal ( ED1 or ED2) corresponds as exactly as possible to a logical zero.

6. Receiver according to claim 5, characterized in that this decider (DDM1 or DDM2) is simultaneously a de-multiplexer which has several, time-nested transmission-side modulation signals (SDDll, SDD12 or SDD21, SDD22) corresponding regenerated signals (DDll, DD12 or DD21, DD22) provides that this switch (SSI or SS2) is closed when all these regenerated signals (DD11, DD12 or DD21, DD22) correspond to logic zeros.

7. Receiver according to claim 5 or 6, characterized in that a control signal (EDS1 or EDS2) is present, which contains the crosstalk (NS) indicative DC component of this switched signal (ESDI or ESD2), that possibly a low-pass filter (Lll or L22) is present, which determines this DC component.

8. Receiver according to one of claims 5 to 7, characterized in that a delay element (L01 or L02) for a delay comparison between the delayed signal (ESI or ES2) and an at least one received zero-indicating logic signal (SNOR1 or SNOR2) is provided.