[go: up one dir, main page]

WO2003007364A3 - Verfahren zur herstellung einer verpackung für halbleiterchips - Google Patents

Verfahren zur herstellung einer verpackung für halbleiterchips Download PDF

Info

Publication number
WO2003007364A3
WO2003007364A3 PCT/EP2002/007439 EP0207439W WO03007364A3 WO 2003007364 A3 WO2003007364 A3 WO 2003007364A3 EP 0207439 W EP0207439 W EP 0207439W WO 03007364 A3 WO03007364 A3 WO 03007364A3
Authority
WO
WIPO (PCT)
Prior art keywords
packing
producing
semiconductor chips
semiconductor chip
mechanical connection
Prior art date
Application number
PCT/EP2002/007439
Other languages
English (en)
French (fr)
Other versions
WO2003007364A2 (de
Inventor
Andreas Bischof
Knut Kahlisch
Henning Mieth
Original Assignee
Infineon Technologies Ag
Andreas Bischof
Knut Kahlisch
Henning Mieth
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag, Andreas Bischof, Knut Kahlisch, Henning Mieth filed Critical Infineon Technologies Ag
Priority to KR1020047000203A priority Critical patent/KR100575354B1/ko
Priority to US10/483,212 priority patent/US7326593B2/en
Publication of WO2003007364A2 publication Critical patent/WO2003007364A2/de
Publication of WO2003007364A3 publication Critical patent/WO2003007364A3/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

Das erfindungsgemässe Verfahren basiert auf der Überlegung, dass beim Fertigstellen der Verpackung eine mechanische Verbindung (4) zwischen dem Halbleiterchip (2) und dem Trägersubstrat (1) wieder gelöst wird. Die zur Herstellung der elektrischen Kontakte zwischen dem Halbleiterchip und dem Trägersubstrat notwendige mechanische Verbindung erfolgt somit nur temporär. Dadurch wird in der Verpackung eine kritische Grenzfläche entfernt was eine deutliche Reduzierung der thermomechanischen Spannungen zur Folge hat.
PCT/EP2002/007439 2001-07-10 2002-07-04 Verfahren zur herstellung einer verpackung für halbleiterchips WO2003007364A2 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020047000203A KR100575354B1 (ko) 2001-07-10 2002-07-04 반도체 칩용 패키지의 제조 방법
US10/483,212 US7326593B2 (en) 2001-07-10 2002-07-04 Method of producing a package for semiconductor chips

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10133361A DE10133361C2 (de) 2001-07-10 2001-07-10 Verfahren zur Herstellung einer Verpackung für Halbleiterchips
DE10133361.7 2001-07-10

Publications (2)

Publication Number Publication Date
WO2003007364A2 WO2003007364A2 (de) 2003-01-23
WO2003007364A3 true WO2003007364A3 (de) 2003-07-24

Family

ID=7691194

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2002/007439 WO2003007364A2 (de) 2001-07-10 2002-07-04 Verfahren zur herstellung einer verpackung für halbleiterchips

Country Status (5)

Country Link
US (1) US7326593B2 (de)
KR (1) KR100575354B1 (de)
DE (1) DE10133361C2 (de)
TW (1) TW565898B (de)
WO (1) WO2003007364A2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10238581B4 (de) * 2002-08-22 2008-11-27 Qimonda Ag Halbleiterbauelement
DE102005015036B4 (de) * 2004-07-19 2008-08-28 Qimonda Ag Verfahren zur Montage eines Chips auf einer Unterlage
CN100416811C (zh) * 2005-10-24 2008-09-03 南茂科技股份有限公司 光电芯片封装构造、制造方法及其芯片承载件
DE102006023168B4 (de) * 2006-05-17 2011-02-03 Infineon Technologies Ag Herstellungsverfahren für eine elektronische Schaltung

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5169056A (en) * 1992-02-21 1992-12-08 Eastman Kodak Company Connecting of semiconductor chips to circuit substrates
JPH10214849A (ja) * 1997-01-31 1998-08-11 Hitachi Chem Co Ltd 半導体パッケ−ジ用チップ支持基板
US6114753A (en) * 1996-05-30 2000-09-05 Hitachi, Ltd. Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US6118183A (en) * 1996-12-19 2000-09-12 Texas Instruments Incorporated Semiconductor device, manufacturing method thereof, and insulating substrate for same
DE19921113A1 (de) * 1999-05-07 2000-11-30 Siemens Ag Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5030308A (en) * 1986-07-14 1991-07-09 National Starch And Chemical Investment Holding Corporation Method of bonding a semiconductor chip to a substrate
US4906314A (en) * 1988-12-30 1990-03-06 Micron Technology, Inc. Process for simultaneously applying precut swatches of precured polyimide film to each semiconductor die on a wafer
KR970008355B1 (ko) * 1992-09-29 1997-05-23 가부시키가이샤 도시바 수지밀봉형 반도체장치
US5504374A (en) * 1994-02-14 1996-04-02 Lsi Logic Corporation Microcircuit package assembly utilizing large size die and low temperature curing organic die attach material
TW422874B (en) * 1996-10-08 2001-02-21 Hitachi Chemical Co Ltd Semiconductor device, semiconductor chip mounting substrate, methods of manufacturing the device and substrate, adhesive, and adhesive double coated film
JP2956617B2 (ja) * 1996-10-31 1999-10-04 日本電気株式会社 樹脂封止型半導体装置
WO1998025302A1 (fr) * 1996-12-04 1998-06-11 Shinko Electric Industries Co., Ltd. Dispositif a semi-conducteurs obture a la resine, fabrication dudit dispositif
JPH10303352A (ja) * 1997-04-22 1998-11-13 Toshiba Corp 半導体装置および半導体装置の製造方法
US5972735A (en) * 1998-07-14 1999-10-26 National Starch And Chemical Investment Holding Corporation Method of preparing an electronic package by co-curing adhesive and encapsulant
KR100308884B1 (ko) * 1998-12-22 2001-11-22 박종섭 씨모스 이미지 센서를 위한 아날로그-디지털 변환 장치
JP3384357B2 (ja) * 1999-04-13 2003-03-10 日立電線株式会社 液晶ポリマーテープの接着方法、およびリードフレームへの半導体チップの搭載方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5169056A (en) * 1992-02-21 1992-12-08 Eastman Kodak Company Connecting of semiconductor chips to circuit substrates
US6114753A (en) * 1996-05-30 2000-09-05 Hitachi, Ltd. Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US6118183A (en) * 1996-12-19 2000-09-12 Texas Instruments Incorporated Semiconductor device, manufacturing method thereof, and insulating substrate for same
JPH10214849A (ja) * 1997-01-31 1998-08-11 Hitachi Chem Co Ltd 半導体パッケ−ジ用チップ支持基板
DE19921113A1 (de) * 1999-05-07 2000-11-30 Siemens Ag Verfahren zur COB-Montage von elektronischen Chips auf einer Schaltungsplatine

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 13 30 November 1998 (1998-11-30) *

Also Published As

Publication number Publication date
TW565898B (en) 2003-12-11
KR20040013122A (ko) 2004-02-11
WO2003007364A2 (de) 2003-01-23
US20060211166A1 (en) 2006-09-21
KR100575354B1 (ko) 2006-05-03
DE10133361C2 (de) 2003-05-28
DE10133361A1 (de) 2003-01-30
US7326593B2 (en) 2008-02-05

Similar Documents

Publication Publication Date Title
SG98431A1 (en) Low profile integrated circuit packages
HUP0303965A3 (en) Multichip module fabricated on a semiconductor or dielectric wafer and method for manufacturing same
WO2002067292A3 (en) Semiconductor package and method of preparing same
WO2003021672A3 (en) An electronic package having a thermal stretching layer
MY116426A (en) Chip scale ball grid array for integrated circuit packaging
MY119341A (en) Chip scale ball grid array for integrated circuit package
WO2003054927A3 (en) Structure and process for packaging rf mems and other devices
WO2002061827A1 (fr) DISPOSITIF à SEMI-CONDUCTEUR ET SON PROCEDE DE FABRICATION
SG85141A1 (en) Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device
WO2003019617A3 (de) Verfahren zur herstellung von elektronischen bauelementen
TWI256719B (en) Semiconductor device package module and manufacturing method thereof
WO2002051217A3 (en) Packaged integrated circuits and methods of producing thereof
WO2003041158A3 (en) Semiconductor package device and method of formation and testing
EP1154471A4 (de) Halbleifes chip und seine herstellung
WO2004059728A3 (en) Method of fabricating an integrated circuit and semiconductor chip
AU2001278736A1 (en) Method of producing semiconductor integrated circuit device and method of producing multi-chip module
WO2003019643A1 (en) Semiconductor device having high-permittivity insulation film and production method therefor
ATE252225T1 (de) Verfahren zum erzeugen eines mikro- elektromechanischen elements
WO2003007364A3 (de) Verfahren zur herstellung einer verpackung für halbleiterchips
EP1291906A4 (de) Halbleiterbauelement und verfahren zu seiner herstellung
SG107567A1 (en) Method and apparatus for forming a flip chip semiconductor package and method for producing a substrate for the flip chip semiconductor package
TW346666B (en) Process for producing dielectric layer in an integrated circuit
TW200611349A (en) Semiconductor package and fabrication method thereof
AU2003263368A1 (en) Selective connection in ic packaging
WO2003024711A3 (de) Verfahren zur herstellung eines keramischen substrats und keramisches substrat

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): KR SG US

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 1020047000203

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 10483212

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 10483212

Country of ref document: US