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WO2003038905A2 - Dispositif lateral silicium sur oxyde a film mince - Google Patents

Dispositif lateral silicium sur oxyde a film mince Download PDF

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Publication number
WO2003038905A2
WO2003038905A2 PCT/IB2002/004412 IB0204412W WO03038905A2 WO 2003038905 A2 WO2003038905 A2 WO 2003038905A2 IB 0204412 W IB0204412 W IB 0204412W WO 03038905 A2 WO03038905 A2 WO 03038905A2
Authority
WO
WIPO (PCT)
Prior art keywords
thickness
layer
silicon
dielectric layer
dielectric
Prior art date
Application number
PCT/IB2002/004412
Other languages
English (en)
Other versions
WO2003038905A3 (fr
Inventor
Rene P. Zingg
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to AU2002339582A priority Critical patent/AU2002339582A1/en
Publication of WO2003038905A2 publication Critical patent/WO2003038905A2/fr
Publication of WO2003038905A3 publication Critical patent/WO2003038905A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/65—Lateral DMOS [LDMOS] FETs
    • H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/112—Field plates comprising multiple field plate segments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform

Definitions

  • the invention relates to a thin film lateral SOI (silicon on oxide) device.
  • SOI lateral power devices show degraded high-side performance due to carrier depletion from the handle wafer (pinching of the drift region). This degradation has been minimized by going to step- and stair-SOCOS device as shown in WO 00/31776, which in fact maximizes the silicon film thickness and available doping therein.
  • the step- and stair-SOCOS devices have, however, a potential trough for electrons in the drift region which has different heights in the SOI film due to variation in silicon film thickness and oxide thickness. This again results in a partial alignment of the vertical electric field with the current direction, increasing impact ionization rate and, thereby, limiting acceptable longitudinal electric fields. Among other disadvantages, this makes it necessary to have the transition step close to the source region where vertical fields are small and makes the device longer for a given voltage rating.
  • the device 2 comprises a buried oxide layer (BOx) 4 on a substrate (not shown) and a silicon layer 6 on the buried oxide layer 4, the silicon layer comprising, from left to right in Fig.l, a first thickness region 8, a second thickness region 10 having a thickness smaller than the first thickness region 8 and a third thickness region 12 having a thickness smaller than the second thickness region 10.
  • a first transition 14 is located between the first thickness region 8 and the second thickness region 10 and a second transition 16 is located between the second thickness region 10 and the third thickness region 12.
  • a second oxide layer (dielectric) is provided on top of the silicon layer 6, the second oxide layer having a gate oxide layer 18, a field oxide layer 20 having a thickness larger than the thickness of the gate oxide layer 18 and a drift oxide layer 22 having a thickness larger than the thickness of the field oxide layer 20.
  • An oxide layer transition 24 is located between the field oxide layer 20 and the drift oxide layer 22.
  • a gate 26 is located above the gate oxide layer 18 and extends as a field plate 28 above a channel region 38 the field oxide layer 20 and the drift oxide layer 22.
  • a drain 30 is laterally spaced from the third thickness region 12 of the silicon layer 6.
  • a source 32 is laterally separated from the gate 26.
  • the gate 26 comprises a polysilicon layer and is covered by a further oxide layer 34.
  • a further metal field plate 36 is provided which extends from the source region 32 across the further oxide layer 34 to almost an end of the field oxide layer 20.
  • the device comprises a substrate, a buried oxide layer on the substrate, a layer of silicon on the buried oxide layer (SOI, silicon on insulator), a layer of dielectric 18 (preferably grown oxide), a gate or field- plate 28 on top of this dielectric, a further dielectric layer 34, a metal layer 36, and a passivation layer (not shown).
  • SOI silicon on the buried oxide layer
  • dielectric 18 preferably grown oxide
  • the SOI layer is sequentially reduced in thickness towards the drain 30 and the oxide sequentially increased in thickness.
  • the metal layer 36 is also used to further remove the field plate 36 from the SOI layer and thereby reduce the vertical fields.
  • Line A in Figure 1 indicates the minimum potential for electrons and shows the change of height of this minimum in the SOI layer due to changes in semiconductor- and dielectric thickness.
  • the US-A 5,362,979 shows a SOI transistor with improved source-high performance especially for bridge type circuits.
  • the laterally extending silicon layer of the drift region has a region of thinner thickness over a portion of the length of the drift region.
  • the field plate is formed with a separation from the gate and extends over the thin portion of the drift region.
  • the gate and field plate are short-circuited by a metal interconnect.
  • the thin film lateral SOI device of the invention comprises, a substrate and a buried oxide layer (BOx) as a dielectric layer on the substrate; a silicon layer on the buried oxide layer, the silicon layer comprising a first thickness silicon region, a second thickness silicon region having a thickness smaller than the first thickness silicon region and a third thickness silicon region having a thickness smaller than the second thickness silicon region; a dielectric layer (TOx) on top of the silicon layer, comprising a gate dielectric layer on top of the first thickness silicon region, a field dielectric layer on top of the a second thickness silicon region, the field dielectric layer having thickness larger than the thickness of the a gate dielectric layer, and a drift dielectric layer on top of the third thickness silicon region the drift dielectric layer having thickness larger than the thickness of the a drift di
  • a thin film SOI device wherein the dielectric layers are oxide layers preferably produced by a LOCOS process.
  • a thin film SOI device wherein the gate terminates at the transition between the field dielectric layer and the drift dielectric region.
  • a thin film SOI device comprising a further dielectric layer covering at least the gate and the drift dielectric layer.
  • a thin film SOI device comprising a further field plate extending across the further dielectric layer (46).
  • the additional field plate supplements the field plate extension of the gate such that the field plate arrangement is adapted to control the complete drift region in the silicon layer or protect the drift region against external influences.
  • a thin film SOI device is provided wherein the further field plate extends to almost an end of the drift dielectric layer.
  • a thin film SOI device wherein the further field plate is connected to the source, whereby the further field plate is on the same potential level as the field plate extension of the gate which is advantageous in controlling the device.
  • a thin film SOI device wherein the gate consists of polysilicon, which is advantageous in integrating the step of manufacturing the gate during the manufacturing process of the device as is well known in the art.
  • a thin film SOI device wherein the further field plate consists of a metal resulting in a well defined shape of the further field plate during manufacturing of the device.
  • a thin film SOI device is provided, wherein the further field plate consists of a first metal layer and a second metal layer, the second metal layer being isolated from the first metal layer.
  • the first metal layer may be connected to the gate and the second metal layer can be connected to the source or the gate or to any separate potential which might be desired to control the drift region.
  • a thin film SOI device is provided, wherein the second metal layer is isolated from the first metal layer by a dielectric layer.
  • a thin film lateral SOI device comprises a substrate, a buried oxide layer on the substrate, a layer of silicon on the buried oxide layer (SOI, silicon on insulator), a layer of dielectric (preferably grown oxide), a gate or field-plate on top of this dielectric.
  • SOI silicon on the buried oxide layer
  • dielectric preferably grown oxide
  • One or multiple metal layers, isolated from the underground by a dielectric film with local contact holes and a passivation layer complete the device.
  • the SOI layer is sequentially reduced in thickness towards the drain, and the oxide sequentially increased in thickness.
  • the metal layer is also used to further remove field-plate from the SOI layer and thereby reduce the vertical fields.
  • SOI film thickness and dielectric under the field-plates are matched according to an equation in order to minimize displacements of the minimum potential of electrons along the device. This reduces carrier multiplication by impact ionization, thereby allowing higher lateral electric fields and permitting shorter devices for a given voltage rating. Reduction in drift region, increase in possible doping, increase in SOI film thickness, and reduction in area individually or in combination contribute to reducing the specific on- resistance, especially in high-side operation.
  • the above described device is a step and stair SOI device or a step and stair
  • SOCOS silicon-oxide-channel-oxide-silicon
  • LDMOS low-density dielectric
  • the invention is applicable to all thin film SOI devices having step transitions in the top oxide layer or level transitions caused by the ends of electrodes or field plates.
  • variations in and the thickness of the additional top oxide may be engineered to level out the potential trough for the electrons.
  • the thinning of the silicon layer on the buried oxide can be moved further to the collector reducing pinch-off effects in high side operation and therefore improve current drive of the device.
  • Figure 1 is a schematic section of a step and stair thin film lateral SOI device of the state of art
  • Figure 2 is a schematic section of a thin film lateral SOI device according to an embodiment of the invention.
  • Figure 3 is a schematic section of a thin film lateral SOI device according to another embodiment of the invention.
  • FIG. 2 An embodiment of the thin film lateral SOI device 40 of the invention is shown in Figure 2 in which the same reference numerals are used for the same parts as in Figure 1.
  • the thin film lateral SOI device of the invention also has a buried oxide layer 4 on a substrate (not shown) and a silicon layer 6 on the buried oxide layer 4.
  • the silicon layer 6 again having the first thickness region 8, the second thickness region 10 and the third thickness region 12.
  • the oxide layer on top of the silicon layer 6 comprises a gate oxide layer 18, a field oxide layer 20 and a drift oxide layer 22 which are provided on the thickness regions 8, 10, 12 respectively of the silicon layer 6.
  • the thin film lateral SOI device 40 of the invention as shown in Figure 2 consists of a gate 42 located above a channel region 38 and extending as a field plate 44 above the gate-oxide layer 18 and the field oxide layer 20.
  • the gate field plate ends at this transition 24, thereby allowing a thickness-matched further dielectric layer 46 to be inserted between field-plate 48 and SOI film 12.
  • This means that the polysilicon gate 42 is ending at the transition 24 from field oxide (FOx) of the first silicon layer thickness region 8 to the drift oxide (DOx) of the second silicon layer thickness region 10.
  • a further field plate 48 extends from the source 32 across the further oxide layer 46 to almost an end of the drift oxide layer 22 and covers the further oxide layer 46.
  • the further oxide layer 46 and the further field plate 48 are extending smoothly across the gate extension and the field oxide as there is no step in this area as in the device of the state of art. The fact that the step of the device of the state of art is missing, further improves the desired functionality of the device.
  • the further field plate 48 may be embodied by an extension of the source 32 and may consist of a metal layer.
  • the potential minimum of the electrons in the silicon layer in the device of Figure 1 is expressed by a relationship between top-oxide thickness (TOx), buried oxide thickness (BOx), and silicon-film thickness (t S o ⁇ ) as follows:
  • FIG. 1 is selected according to the following relationship between top-oxide thickness (TOx), buried oxide thickness (BOx), and silicon-film thickness (tSOI) as follows:
  • TOxl is the total thickness of all dielectric layers under the field plate to the left of the transition (24)
  • TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition (24)
  • BOx is the thickness of the buried oxide layer tson is the thickness of the silicon on insulator layer to the left of the transition (24) tsoi 2 s the thickness of the silicon on insulator layer to the right of the transition (24) e si is the dielectric constant of silicon e ox is the dielectric constant of the dielectric.
  • Tuning the thickness of the buried oxide and the silicon layer according the equating (3) results in a reduction of the depth of the potential trough.
  • FIG. 3 Another embodiment of the thin film lateral SOI device 50 of the invention is shown in Figure 3 in which the same reference numerals are used for the same parts as in Figures 1 and 2.
  • the further field plate is embodied by a first metal layer 52 and a second metal layer 54, the second metal layer being isolated from the first metal layer 52, by an oxide layer 56.
  • the second metal layer 54 may be connected to the source, to the gate or to a separate potential.
  • BOx is the thickness of the buried oxide layer 4
  • TOxl is the total thickness of all dielectric layers below the field plate to the left of the transition 24
  • TOx2 is the thickness of all dielectric layers under the field plate to the right of the transition 24, i.e. the thickness of the drift dielectric layer 22 plus the thickness of the further dielectric layer 46
  • TOx3 is the thickness of all dielectric layers under the further field plate 54, i.e. the thickness of the third dielectric layer thickness region plus the thickness of the further dielectric layer 46 plus the thickness of the dielectric layer 56 tson the thickness of the first silicon layer thickness region 10 tson the thickness of the second silicon layer thickness region 12 tson is the thickness of the third silicon layer thickness region 14 to the right of the second silicon layer thickness region 12

Landscapes

  • Thin Film Transistor (AREA)

Abstract

Un dispositif latéral silicium sur oxyde (SSO) à film mince comprend un substrat et une couche d'oxyde noyée (4) (BOx) faisant office de couche diélectrique sur le substrat; une couche de silicium (6) située sur la couche d'oxyde noyée, la couche de silicium comprenant une première région (8) ayant une première épaisseur et une deuxième région (10) ayant une deuxième épaisseur, l'épaisseur de la première région (8) étant supérieure à celle de la deuxième région et une troisième région (12) ayant une troisième épaisseur qui est inférieure à l'épaisseur de la deuxième région (10); une couche diélectrique (TOx) située au-dessus de la couche de silicium (6), comprenant une couche (18) de diélectrique de grille située au-dessus de la première région (8) ayant une première épaisseur, une couche (20) de diélectrique de champ située au-dessus de la deuxième région (10) ayant une deuxième épaisseur, la couche (20) de diélectrique de champ présentant une épaisseur supérieure à celle de la couche (18) de diélectrique de grille et une couche (22) de diélectrique de migration située au-dessus de la troisième région ayant une troisième épaisseur, la couche (22) de diélectrique de migration présentant une épaisseur supérieure à celle de la couche (20) de diélectrique de champ; une grille (42) située au-dessus de la couche (18) de diélectrique de grille, au-dessus d'une région de canal (38); une plaque (44) de champ s'étendant au niveau de la couche (20) de diélectrique de champ; un drain (30) latéralement espacé de la troisième région (12) ayant une troisième épaisseur, de la couche de silicium (6); et une source (32) latéralement séparée de la grille.
PCT/IB2002/004412 2001-11-01 2002-10-22 Dispositif lateral silicium sur oxyde a film mince WO2003038905A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2002339582A AU2002339582A1 (en) 2001-11-01 2002-10-22 Lateral soi field-effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP01204203 2001-11-01
EP01204203.2 2001-11-01

Publications (2)

Publication Number Publication Date
WO2003038905A2 true WO2003038905A2 (fr) 2003-05-08
WO2003038905A3 WO2003038905A3 (fr) 2003-10-23

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AU (1) AU2002339582A1 (fr)
TW (1) TW200406924A (fr)
WO (1) WO2003038905A2 (fr)

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WO2005114743A3 (fr) * 2004-05-11 2006-05-04 Cree Inc Transistors a large bande interdite comprenant de multiples plaques de champ
WO2007069188A3 (fr) * 2005-12-14 2007-12-13 Nxp Bv Transistor mos et procédé de fabrication d'un transistor mos
GB2451122A (en) * 2007-07-20 2009-01-21 X Fab Uk Ltd Low threshold voltage transistor with non-uniform thickness gate dielectric
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
US7550783B2 (en) 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US7692263B2 (en) 2006-11-21 2010-04-06 Cree, Inc. High voltage GaN transistors
US7709269B2 (en) 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US8283699B2 (en) 2006-11-13 2012-10-09 Cree, Inc. GaN based HEMTs with buried field plates
CN103633136A (zh) * 2012-08-20 2014-03-12 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法
US8823057B2 (en) 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9773877B2 (en) 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures
US11791385B2 (en) 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates

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TWI584473B (zh) * 2016-08-10 2017-05-21 亞洲大學 高壓半橋電位移轉器及其製造方法

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US6346451B1 (en) * 1997-12-24 2002-02-12 Philips Electronics North America Corporation Laterial thin-film silicon-on-insulator (SOI) device having a gate electrode and a field plate electrode
JP2001513270A (ja) * 1997-12-24 2001-08-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 改良されたオン状態特性を有する高電圧薄膜トランジスタ及びその製造方法
DE19800647C1 (de) * 1998-01-09 1999-05-27 Siemens Ag SOI-Hochspannungsschalter
US6232636B1 (en) * 1998-11-25 2001-05-15 Philips Electronics North America Corporation Lateral thin-film silicon-on-insulator (SOI) device having multiple doping profile slopes in the drift region

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US7928475B2 (en) 2003-09-09 2011-04-19 Cree, Inc. Wide bandgap transistor devices with field plates
US9397173B2 (en) 2003-09-09 2016-07-19 Cree, Inc. Wide bandgap transistor devices with field plates
US8120064B2 (en) 2003-09-09 2012-02-21 Cree, Inc. Wide bandgap transistor devices with field plates
US7501669B2 (en) 2003-09-09 2009-03-10 Cree, Inc. Wide bandgap transistor devices with field plates
JP2013153189A (ja) * 2004-05-11 2013-08-08 Cree Inc 複数のフィールドプレートを有するワイドバンドギャップトランジスタ
WO2005114743A3 (fr) * 2004-05-11 2006-05-04 Cree Inc Transistors a large bande interdite comprenant de multiples plaques de champ
US8664695B2 (en) 2004-05-11 2014-03-04 Cree, Inc. Wide bandgap transistors with multiple field plates
EP2538446A3 (fr) * 2004-05-11 2014-01-15 Cree, Inc. Transistors à large bande interdite avec de multiples plaques de champ
US7915644B2 (en) 2004-05-11 2011-03-29 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US7550783B2 (en) 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US7573078B2 (en) 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US8592867B2 (en) 2004-05-11 2013-11-26 Cree, Inc. Wide bandgap HEMTS with source connected field plates
US9773877B2 (en) 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US11791385B2 (en) 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US7576387B2 (en) 2005-12-14 2009-08-18 Nxp B.V. MOS transistor and method of manufacturing a MOS transistor
WO2007069188A3 (fr) * 2005-12-14 2007-12-13 Nxp Bv Transistor mos et procédé de fabrication d'un transistor mos
US7960756B2 (en) 2006-01-17 2011-06-14 Cree, Inc. Transistors including supported gate electrodes
US8049252B2 (en) 2006-01-17 2011-11-01 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes and related devices
US7709269B2 (en) 2006-01-17 2010-05-04 Cree, Inc. Methods of fabricating transistors including dielectrically-supported gate electrodes
US7592211B2 (en) 2006-01-17 2009-09-22 Cree, Inc. Methods of fabricating transistors including supported gate electrodes
US9984881B2 (en) 2006-11-06 2018-05-29 Cree, Inc. Methods of fabricating semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
US8823057B2 (en) 2006-11-06 2014-09-02 Cree, Inc. Semiconductor devices including implanted regions for providing low-resistance contact to buried layers and related devices
US8283699B2 (en) 2006-11-13 2012-10-09 Cree, Inc. GaN based HEMTs with buried field plates
US8933486B2 (en) 2006-11-13 2015-01-13 Cree, Inc. GaN based HEMTs with buried field plates
US7692263B2 (en) 2006-11-21 2010-04-06 Cree, Inc. High voltage GaN transistors
US9041064B2 (en) 2006-11-21 2015-05-26 Cree, Inc. High voltage GaN transistor
US9450081B2 (en) 2006-11-21 2016-09-20 Cree, Inc. High voltage GaN transistor
US8169005B2 (en) 2006-11-21 2012-05-01 Cree, Inc. High voltage GaN transistors
US7893500B2 (en) 2006-11-21 2011-02-22 Cree, Inc. High voltage GaN transistors
GB2451122A (en) * 2007-07-20 2009-01-21 X Fab Uk Ltd Low threshold voltage transistor with non-uniform thickness gate dielectric
CN103633136A (zh) * 2012-08-20 2014-03-12 上海华虹宏力半导体制造有限公司 Ldmos器件及其制造方法
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures

Also Published As

Publication number Publication date
AU2002339582A1 (en) 2003-05-12
WO2003038905A3 (fr) 2003-10-23
TW200406924A (en) 2004-05-01

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