WO2005053366A1 - Circuit electrique - Google Patents
Circuit electrique Download PDFInfo
- Publication number
- WO2005053366A1 WO2005053366A1 PCT/EP2004/012607 EP2004012607W WO2005053366A1 WO 2005053366 A1 WO2005053366 A1 WO 2005053366A1 EP 2004012607 W EP2004012607 W EP 2004012607W WO 2005053366 A1 WO2005053366 A1 WO 2005053366A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chip
- circuit arrangement
- arrangement according
- contact
- receiving recess
- Prior art date
Links
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- 239000004020 conductor Substances 0.000 claims abstract description 19
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- 238000009826 distribution Methods 0.000 claims description 11
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- 229910052751 metal Inorganic materials 0.000 claims description 7
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000003848 UV Light-Curing Methods 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
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- 229910052802 copper Inorganic materials 0.000 description 1
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- 238000007667 floating Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- -1 polybutylene terephthalate Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
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- 230000000284 resting effect Effects 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
- H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/32—Holders for supporting the complete device in operation, i.e. detachable fixtures
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0101—Neon [Ne]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01032—Germanium [Ge]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/119—Details of rigid insulating substrates therefor, e.g. three-dimensional details
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0314—Elastomeric connector or conductor, e.g. rubber with metallic filler
Definitions
- the invention relates to an electrical circuit arrangement which has a circuit carrier equipped with an electronic chip, which has a carrier substrate on which conductor tracks are provided which lead to first contact pads arranged on a first contact area, the chip being connected to one of the first contact areas che facing second contact surface has second contact pads, which are electrically contacted with the interposition of anisotropically electrically conductive contact means with the first contact pads.
- the circuit carrier has a carrier substrate with a plurality of protruding contact bumps, the contact bumps carrying first contact pads connected to conductor tracks, which are contacted with assigned second contact pads of the chip set up in flip-chip technology with the interposition of an anisotropically electrically conductive adhesive.
- the adhesive connection also ensures the mechanical attachment of the chip to the circuit carrier.
- the adhesive also takes on the function of an underfiller, which fills the space between the chip and the circuit carrier. Circuit arrangements of a similar type are also apparent from DE 10163799 AI, US 6,555,759 and EP 0782765 B1.
- Manufacturing is less susceptible to temperature fluctuations and at the same time also ensures good mechanical protection of the electronic chip.
- the first contacting puddle is located at the bottom of a receiving recess of the carrier substrate which is closed laterally all round, in which the contact means and the chip are completely received,
- the contact means from at least one placed between the two contact surfaces, elastically deformable in the direction of the vertical axis of the recess Contacting element exist, which has a rubber-elastic base body with mutually opposite, the two contact surfaces facing first and second counter-contact surfaces as well as a large number of elastically deformable guide bodies which pull through the base body with mutual insulation and end on the counter-contact surfaces with guide surfaces,
- a mechanically fixed connection between the contacting areas assigned to one another is no longer required for the electrical contacting of the chip and circuit carrier.
- the desired reliable electrical contact between the contact surfaces on both sides results solely from the pressing of the elastically deformable contact element.
- the elasticity of the contacting element results in a flexible connection that is able to automatically compensate for different expansion coefficients of the chip and the carrier substrate, so that even with large temperature fluctuations and with widely differing expansion coefficients, as in MID technology, it is always secure electrical connection is guaranteed.
- the chip is also always fixed mechanically, with the contacting element at least in the height direction of the receiving recess creating a type of floating mounting that allows relative movements between the components mentioned. Since the chip is sunk in the recess, this avoids an exposed location, which protects the chip from mechanical damage.
- chip is therefore understood to mean both designs without a housing surrounding the chip and designs in which the chip is located in a housing, the second contact pads being able to be provided on the chip itself or on the housing.
- Another advantage of the electrical circuit arrangement is that it does not require an underfiller. There is also no need to apply liquid adhesive in the joining area between the chip and the circuit board. Compared to the flip-chip technology based on soldering, there is also no need to attach the solder pads required for contacting the contact pads.
- WO 96/15551 AI already describes the assembly of electronic components on a printed circuit board, a large number of flexible contact means being used between a semiconductor package and a carrier substrate. However, these contact means are arranged individually free-standing and firmly anchored at one end to the carrier substrate.
- Elastically deformable contacting elements that are suitable for use in the electrical circuit arrangement are already known as such.
- No. 5,617,898 discloses a contacting element which is composed of stacked layers of conductive and non-conductive elastic material.
- the company Shin-Etsu Polymer Europe BV, 5928 NS Venlo, the Netherlands sells a connector under the type designation "GX4", in which a matrix of gold-coated metal wires are embedded in a silicone rubber layer.
- GX4 type designation
- a similarly constructed contacting element is also described in US Pat. No. 4,209,481.
- an elastically deformable contacting element in which the individual guide surfaces each have a smaller surface area than the contact pads on the chip and circuit carrier, the guide surfaces on the countercontacting surfaces being combined in a fine, matrix-like distribution to form one or more guide surface groups are.
- the two mating contact surfaces can each be occupied over the entire surface by a guide surface group, so that no attention has to be paid to the position of the contact pads during manufacture, because in the assembled state those guide bodies automatically ensure the electrical connection, the guide surfaces of which are acted upon by the contact pads.
- the loading structure for the chip expediently has a cover which overlaps the chip and is fixed to the carrier substrate. Optimal protection for the chip is obtained if the lid has no openings and the opening of the receiving recess is completely closed by it.
- the connection between the cover and the support structure is preferably made of a material conclusive connection realized, in particular by an adhesive connection, the use of an adhesive curing by UV radiation is recommended. No heating is necessary here and the time required to mechanically fix the chip until the adhesive bond cures is extremely short.
- the cover can lie completely outside the receiving recess or can also only partially protrude into the receiving recess.
- an embodiment is particularly expedient in which the cover sits completely inside the receiving recess.
- SMD Surf ce Mounted Device
- WO 01/95486 A1 describes a method for producing individual microelectronic devices, a multiplicity of spaced-apart recesses being formed in a non-conductive material, in each of which a component based on piezoelectric principles is seated, the recesses being closed at the top by tightly inserted lids are. Contacting the component by means of elastic contact means is not provided, however.
- a detachable fixation can also be achieved by means of an appropriately designed impact structure.
- the loading structure can be equipped with latching hooks arranged on the support structure, which either overlap the chip directly or over a cover located above the chip and press in the direction of the base of the receiving recess. If the chip is defective, it can be deformed the locking hook is removed from the recess and replaced with a new chip.
- the cover can be provided with cooling fins immediately, so that no special cooling element is required.
- FIG. 1 shows, in a greatly enlarged and schematic illustration, a preferred first embodiment of the electrical circuit arrangement according to the invention in a perspective exploded illustration
- FIG. 2 shows a longitudinal section through the arrangement from FIG. 1 according to section line II-II in the assembled state, the contacting element being cut transversely according to section line Ila-IIa of FIG. 5,
- FIG. 3 shows an individual illustration of the circuit carrier from FIGS. 1 and 2 in a plan view of the side having the receiving recess
- FIG. 4 shows an individual illustration of the chip used in the arrangement according to FIGS. 1 and 2 in a bottom view
- FIG. 5 shows an individual illustration of the contacting element used in the arrangement according to FIGS. 1 and 2 in a perspective illustration
- FIG. 6 shows the contacting element from FIG. 5 in longitudinal section according to section line VT-VT
- FIG. 7 shows an alternative design of a contacting element in a perspective view
- FIG. 8 shows a side view of the contacting element from FIG. 7, the guide bodies passing through the base body being indicated by dash-dotted lines,
- FIG. 9 again shows a further alternative design of the contacting element in a perspective view
- FIG. 10 shows a side view of the contacting element from FIG. 9, the guide bodies again being indicated by dash-dotted lines,
- FIG. 11 shows a modified design of the electrical circuit arrangement in perspective, with a different design of the cover compared to FIG. 1,
- FIG. 12 shows the cover used in the circuit arrangement from FIG. 1 in a perspective individual illustration
- FIG. 13 shows a modified design of the circuit arrangement with rib-like heat sinks arranged on the cover
- FIG. 14 shows a modified design of the circuit arrangement in which the cover is equipped with further electronic components
- FIG. 15 shows a further embodiment of the electrical circuit arrangement, in which latching means are provided for releasably fixing the chip
- FIG. 16 shows a design of the circuit arrangement realized in connection with a multilayer printed circuit board, with one closing the exception recess Lid is only indicated by dash-dotted lines, and
- FIG. 17 shows a side view of the circuit arrangement from FIG. 16, the circled area being shown in longitudinal section along section line XVII.
- the drawing shows several exemplary embodiments of an electrical circuit arrangement, generally designated by reference number 1, which has a circuit carrier 2 which is equipped with at least one electronic chip 3.
- a possible embodiment of such a chip 3 is shown schematically in FIG. 4 in a perspective bottom view.
- the circuit carrier 2 is designed as a three-dimensional MID part. It contains a carrier substrate 4 made of injection-moldable, preferably thermoplastic, plastic material, which is provided on one or more sides with conductor tracks 6, which are used for the transmission of electrical signals between the appropriate placed connection points and the chip 3 and any other existing electronic components 49.
- the exemplary embodiments show arrangements in which a plurality of conductor tracks 6 are electrically contacted at the same time with a chip 3 placed in a receiving recess 5 of the carrier substrate 4.
- circuit carrier 2 is designed as a multilayer printed circuit board, the carrier substrate of which is composed of a plurality of sandwich-like printed circuit boards 7 which are glued to one another.
- the receiving recess 5, which is recessed like a pit from the carrier substrate 4, has a vertical axis 8 which, in the exemplary embodiment, is at right angles to the main plane of expansion of the extends, for example, plate-shaped circuit carrier 2.
- the receiving recess 5 has a bottom 12 at the bottom and an opening 1 opening at the top to the outer surface 13 of the carrier substrate 4. Laterally, the receiving recess 5 between the base 12 and the opening 14 is closed all around and is delimited by an all-round side wall surface 15, which is defined by the carrier substrate 4.
- the conductor tracks 6 extend from the outer surface 13 into the receiving recess 5 until they merge into first contact pads 16, which are arranged on a first contacting surface 18 of the carrier substrate 4 defined by the base 12 of the receiving recess.
- the distribution pattern of the first contact pads 16 corresponds to the specific technical requirements, with two groups of four first contact pads 16 lying next to each other in a row being provided in the exemplary embodiment.
- the first contacting surface 18 is expediently flat, so that all the first contact pads 16 also lie in a common plane, wherein they face the opening 14 in the direction of the vertical axis 8.
- the conductor tracks 6 run at the transition between the outer surface 13 and the base 12 along the side wall surface 15 of the receiving recess 5.
- the corresponding wall region 22 expediently has an oblique shape
- the conductor tracks 6 are here preferably produced using MID technology, for example using the so-called laser direct structuring method.
- the starting point here is, for example, a PBT plastic (polybutylene terephthalate) optimized for MID applications, the plastic material being provided with embedded metal particles or metal nuclei.
- a laser beam is guided over the surface of the carrier substrate 4, with local material activation taking place in the irradiated surface areas.
- metal nuclei are split off from special, non-conductive active substances.
- the receiving recess 5 is formed in the MID production during the injection molding of the carrier substrate 4.
- the receiving recess 5 results from cutouts in some of the circuit board layers formed by the circuit boards 7.
- the recessed boards 7 define the side wall surface 15, while the base 12 is defined by a board 7 which has not been left open.
- vias 23 are used which penetrate different ones of the circuit boards 7 to provide an electrically conductive transition between the conductor track sections running on the outer surface 13 and the base 12 to obtain.
- the chip 3 is completely accommodated in the receiving recess 5 together with an elastically deformable contacting element 24 which serves to make electrical contact with it.
- the contacting element 24 lies in the direction of the vertical axis 8 between the chip 3 and the base 12 of the receiving recess 5.
- the bottom side of the chip 3 facing the base 12 forms a second contact area 19 on which a plurality of second contact pads 17 are provided, which are connected to the circuit integrated in the chip 3.
- These second contact pads 17 are distributed such that they are each opposite one of the first contact pads 16 provided on the carrier substrate 4 in the direction of the vertical axis 8 (FIG. 4).
- the interposed contacting element 24 electrically connects the first and second contact pads 16, 17, which are assigned to one another in pairs in this way.
- the chip 3 can be a housed or an unhoused chip. If the chip 3 has a housing, the second contact pads 17 cooperating with the contacting element 24 are generally located on the chip housing.
- the contacting element 24 has an anisotropic electrical conductivity, the direction of conductivity coinciding with the course of the vertical axis 8.
- FIGS. 5 and 6 each show the contacting element 24 used in the design according to FIGS. 1 to 3 in an individual representation.
- the contacting element 24 is elastically deformable overall in the direction of the vertical axis 8. It has a rubber-elastic base body 25, in particular made of silicone rubber, which has a first or second mating contact surface 20, 21 on opposite sides.
- the base body 25 is preferably of plate-like design and placed in the receiving recess 5 such that the Plate plane is perpendicular to the vertical axis 8.
- the mating contact surfaces 20, 21 are then formed by the two larger outer surfaces of the base body 25, which face the base 12 and the opening 14.
- the base body 25 is traversed in the direction of the vertical axis 8 by a plurality of guide bodies 26 embedded in the base body material with mutual insulation. These guide bodies 26 each end on both mating contact surfaces 20, 21 with first or second guide surfaces 27, 28 accessible from the outside. They are elastically deformable in such a way that they permit a change in the distance between their respectively assigned first and second guide surfaces 27, 28.
- the base body 25 can be compressed in the direction of the vertical axis 8, the acted upon first and second guide surfaces 27, 28 of the individual guide bodies 26 simultaneously approaching one another.
- the two guide surfaces 27, 28 of a guide body 26 approach each other, the latter can, for example, buckle or bend sideways, as is indicated by a dot-dash line at 32 in FIG.
- the guide bodies 26 consist of elastically bendable metal wires, the end faces of which directly form the first and second guide surfaces 27, 28.
- the base body 25 can be completely or only partially penetrated by the guide bodies 26.
- the guide surfaces 27, 28 on the mating contacts tion surfaces 20, 21 combined in a fine matrix-like distribution to form one or more guide surface groups 33.
- the guide bodies 26 are placed in such a way that a number of guide surface groups 33 corresponding to the number of contact pads 16 and 17 to be contacted is obtained on each mating contact surface 20, 21, which groups are arranged such that they are each opposite a first and second contact pad 16, 17 to be contacted. In this way, a punctiform design or distribution of the guide surface groups 33 is achieved.
- the chip 3 is loaded on the upper side opposite the base 12 of the receiving recess 5, so that it is biased against the contacting element 24, which in turn is pressed onto the first contacting surface 18.
- the contacting element 24 is thus clamped in the direction of the vertical axis 8 between the carrier substrate 4 and the chip 3.
- the first and second contact pads 16, 17 are pressed onto the respective facing Lei surfaces 27, 28. In this way, there is an electrical connection between the opposing first and second contact pads 16, 17 via the number of guide bodies 26 arranged between them, which are simultaneously acted upon by these contact pads 16, 17.
- the contacting element 24 builds up a counterpressure which ensures a secure electrical connection between a respective contact pad and the guide bodies 26 resting thereon solely by the contact pressure, so that further connecting measures, for example soldering or gluing by means of conductive adhesive, are in the offing Can be dispensed with in favor of simplified assembly.
- the contacting element 24 of FIGS. 5 and 6 is specific to the distribution of the contact pads 16, 17 with regard to the configuration and distribution of the guide surface groups 33 customized.
- a design that enables use independent of the contact pad distribution is significantly more advantageous.
- Such an embodiment is shown in FIGS. 9 and 10, in which case only one guide surface group 33 is provided on each of the two mating contact surfaces 20, 21, but which in each case extends over the entire surface of the mating contact surfaces 20, 21 in question. In this way, an electrical connection between contact pads lying on opposite sides of the contacting element 24 is possible irrespective of the point at which the
- FIGS. 7 and 8 Another possible alternative design of the contacting element 24 is shown in FIGS. 7 and 8.
- the guide bodies 26 are arranged there in such a way that they form a plurality of strip-like guide surface groups 33 on the two mating contact surfaces 20, 21.
- the loading structure 34 in all exemplary embodiments includes a cover 35 which overlaps the chip 3 on the upper side opposite the base 12 of the receiving recess 5.
- This cover is expediently inserted into the receiving recess 5 in the region of the opening 14 in such a way that it is complete comes to rest in the interior of the recess 5.
- An arrangement is expedient in which the outer surface 36 of the cover 35 which points away from the base 12 in the direction of the vertical axis 8 runs flush with the edge region of the outer surface 13 of the carrier substrate 4 which surrounds the opening 14.
- the cover 35 is integrally connected to the carrier substrate.
- an adhesive connection is used, a suitable adhesive being indicated at 37.
- a UV-curing adhesive 37 is expediently used, which achieves its strength even without the introduction of heat, which means protection for the chip.
- the cover 35 When assembling the circuit arrangement 1, the cover 35 is pressed onto the chip 3 by means of a suitable tool until the adhesive 37 has hardened. In this way it is achieved that the combination of chip 3 and contacting element 34 is clamped non-positively between cover 35 and base 12 of receiving recess 5 with the desired pretension.
- the adhesive 37 is expediently applied in the liquid state due to capillary action in a narrow gap 38 which extends around the cover 35 between the latter and the carrier substrate 4.
- This gap 38 is connected to one or more pot-like recesses 42, which are formed in the outer surface 13 of the carrier substrate 4.
- the opening 14 has a rectangular outline, one of the mentioned pot-like recesses 42 being placed in each of the four corner regions.
- the adhesive is fed into the pot-like recesses 42, from where it is drawn into the gap 38 due to the capillary action until the entire gap 38 is finally filled with adhesive 37.
- FIGS. 11 and 12 there is a pot-like recess 42, in particular at a central point, in the outer surface 36 of the cover 35.
- a pot-like recess 42 in particular at a central point, in the outer surface 36 of the cover 35.
- four such groove-like depressions 43 are provided, each of which lead to an edge center of the cover 35.
- the adhesive 37 is fed into the pot-like recess 42 of the cover 35, from where it reaches the gap 38 via the groove-like depressions 43, in order to spread there again by capillary action.
- the cover 35 completely closes the opening 14 of the receiving recess 5.
- Adhesive 37 ensures the sealing of the joint area.
- a cover can also be used which, in contrast to the design described, is not continuously closed, but has one or more openings.
- the cover can then also be designed, for example, in such a way that it spans only part of the opening 14 of the receiving recess 5, for example in a web-like configuration.
- the cover 35 can be provided on its outer surface 36 with an electrical conductor structure 44, which enables the electrical contacting of one or more electronic components 49.
- FIG. 14 shows two SMD components, some of which are seated on the cover 35 and which are in contact with the electrical conductor structure 44 of the cover 35 and with another electrical conductor structure 45 arranged on the outer surface 13 of the carrier substrate 4.
- the outer surface 36 of the cover 35 can thus be used as a mounting surface for further electronic components. This enables extremely space-saving installation of electrical circuits.
- FIG. 13 shows the possibility of using the cover 35 as a carrier for the heat sink 46 if the chip 3 requires cooling in the intended use.
- the heat sinks 46 are in particular rib-shaped and can be integrally formed on the cover 35.
- the loading structure 34 is designed in such a way that it enables the chip 3 to be fixed releasably.
- it preferably has latching means, which are expediently made in one piece with the carrier substrate 4.
- the latching means consist of latching hooks 48 which can be elastically bent transversely to the vertical axis 8 according to double arrows 47 and which protrude slightly beyond the opening 14.
- the latching hooks 48 are temporarily spread apart in order to spring back in the direction of its starting position after the chip 3 has been passed through, so that on the one hand it overlaps the chip 3 on its upper side and on the other hand it exerts a compressive force acting in the direction of the base 12 exert the top of the chip 3 so that it is pressed against the contacting element 24.
- the latching hooks 48 can be spread apart manually or by means of a suitable tool, so that the chip 3 which is only in contact with the contacting element 24 and is not firmly connected to this contacting element 24 can be removed without problems.
- latching means or latching hooks 48 interact directly with the chip 3 in the exemplary embodiment in FIG. 15, a design would also be possible in which the chip 3 is covered by a cover or another force transmission element, the latching means acting on this cover or the force transmission element.
- the loading structure 34 does not protrude beyond the outer surface of the carrier substrate 4, to which the opening 14 opens. In the exemplary embodiments in FIGS. 1 to 3, 11 and 13 to 15, this is achieved by a recessed arrangement of the cover 35.
- the latching means or latching hooks 48 are located completely within the recess 5 for this purpose.
- the lateral wall surface 15 can in each case have a cross section of the recessed area 5 have enlarging recess 52.
- a plurality of contacting elements 24 arranged next to one another could also be provided.
- the contacting element or elements 24 can be held or stabilized by a separate holding structure.
- the inner contour of the receiving recess 5 can be designed such that the at least one contacting element 24 placed in place is positively fixed transversely to the vertical axis 8 by the wall of the receiving recess 5. Such a design is particularly useful when the guide surface groups 33 have a distribution pattern that is specially adapted to the distribution of the contact pads 16, 17.
- a contacting element 24 can be used with a different structure that has the required rubber elasticity and at the same time is exclusively anisotropically conductive in the direction of the vertical axis 8.
- the circuit arrangement according to the invention can have one or more of the following advantages.
- the expansion coefficient problem encountered with conventional flip-chip technologies is alleviated.
- Additional installation space for further circuit arrangements and / or electronic components can be provided via the circuit arrangement 1.
- a chip exchange can be implemented by appropriately designing the loading structure.
- chips 2 can be used for the circuit arrangement that are also used in conventional flip-chip technologies and are designed, for example, for contacting by bonding. Efficient chip cooling is possible.
- Several chips can be installed one above the other.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Metallurgy (AREA)
- Manufacturing & Machinery (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04797703A EP1688022A1 (fr) | 2003-11-29 | 2004-11-08 | Circuit electrique |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10355921.3 | 2003-11-29 | ||
DE10355921A DE10355921B4 (de) | 2003-11-29 | 2003-11-29 | Elektrische Schaltungsanordnung mit einem elektronischen Chip in einer Aufnahmevorrichtung des Schaltungsträgers |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005053366A1 true WO2005053366A1 (fr) | 2005-06-09 |
Family
ID=34625411
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2004/012607 WO2005053366A1 (fr) | 2003-11-29 | 2004-11-08 | Circuit electrique |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1688022A1 (fr) |
CN (1) | CN1887036A (fr) |
DE (1) | DE10355921B4 (fr) |
TW (1) | TW200537655A (fr) |
WO (1) | WO2005053366A1 (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112582368A (zh) * | 2019-09-27 | 2021-03-30 | 西门子股份公司 | 电路载体、封装及其制造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011109006A1 (de) * | 2011-07-29 | 2013-01-31 | Epcos Ag | Gehäuse für einen Halbleiterchip und Halbleiterchip mit einem Gehäuse |
DE102011121818B4 (de) * | 2011-12-21 | 2024-08-14 | Vitesco Technologies Germany Gmbh | Anordnung eines elektronischen Bauteils in einem Gehäuse |
DE102015121857A1 (de) * | 2015-12-15 | 2017-06-22 | Endress+Hauser Conducta Gmbh+Co. Kg | Verfahren zum Herstellen eines Leitfähigkeitssensors |
DE102017108437B4 (de) * | 2017-04-20 | 2020-07-09 | Gottfried Wilhelm Leibniz Universität Hannover | Elektrische Schaltungsstruktur und Verfahren zu deren Herstellung |
DE102022119313A1 (de) | 2022-08-02 | 2024-02-08 | Tridonic Gmbh & Co Kg | SMD-Bauelemente |
CN116548892B (zh) * | 2023-02-28 | 2024-07-05 | 湖南省华芯医疗器械有限公司 | 一种电路结构、前端组件及内窥镜 |
DE102024201717A1 (de) * | 2024-02-26 | 2025-08-28 | Robert Bosch Gesellschaft mit beschränkter Haftung | Substrat eines Leistungsmoduls |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0245179A2 (fr) * | 1986-05-07 | 1987-11-11 | Digital Equipment Corporation | Système de montage amovible pour semi-conducteurs sur un substrat conducteur |
US5474458A (en) * | 1993-07-13 | 1995-12-12 | Fujitsu Limited | Interconnect carriers having high-density vertical connectors and methods for making the same |
US5929516A (en) * | 1994-09-23 | 1999-07-27 | Siemens N.V. | Polymer stud grid array |
US6399892B1 (en) * | 2000-09-19 | 2002-06-04 | International Business Machines Corporation | CTE compensated chip interposer |
US20020121706A1 (en) * | 2000-12-28 | 2002-09-05 | Matsushita Electic Works, Ltd. | Semiconductor-chip mounting substrate and method of manufacturing the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US4209481A (en) * | 1976-04-19 | 1980-06-24 | Toray Industries, Inc. | Process for producing an anisotropically electroconductive sheet |
DE69233568T2 (de) * | 1991-09-10 | 2006-08-10 | Smc K.K. | Durch Flüssigkeitsdruck betätigte Vorrichtung |
CN1251319C (zh) * | 1994-11-15 | 2006-04-12 | 佛姆法克特股份有限公司 | 微电子组件的插入物的制造方法 |
US6524115B1 (en) * | 1999-08-20 | 2003-02-25 | 3M Innovative Properties Company | Compliant interconnect assembly |
US6230400B1 (en) * | 1999-09-17 | 2001-05-15 | George Tzanavaras | Method for forming interconnects |
AU2001263463A1 (en) * | 2000-06-06 | 2001-12-17 | Sawtek, Inc. | System and method for array processing of surface acoustic wave devices |
-
2003
- 2003-11-29 DE DE10355921A patent/DE10355921B4/de not_active Expired - Fee Related
-
2004
- 2004-11-08 EP EP04797703A patent/EP1688022A1/fr not_active Withdrawn
- 2004-11-08 CN CNA200480035184XA patent/CN1887036A/zh active Pending
- 2004-11-08 WO PCT/EP2004/012607 patent/WO2005053366A1/fr not_active Application Discontinuation
- 2004-11-24 TW TW093136093A patent/TW200537655A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0245179A2 (fr) * | 1986-05-07 | 1987-11-11 | Digital Equipment Corporation | Système de montage amovible pour semi-conducteurs sur un substrat conducteur |
US5474458A (en) * | 1993-07-13 | 1995-12-12 | Fujitsu Limited | Interconnect carriers having high-density vertical connectors and methods for making the same |
US5929516A (en) * | 1994-09-23 | 1999-07-27 | Siemens N.V. | Polymer stud grid array |
US6399892B1 (en) * | 2000-09-19 | 2002-06-04 | International Business Machines Corporation | CTE compensated chip interposer |
US20020121706A1 (en) * | 2000-12-28 | 2002-09-05 | Matsushita Electic Works, Ltd. | Semiconductor-chip mounting substrate and method of manufacturing the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112582368A (zh) * | 2019-09-27 | 2021-03-30 | 西门子股份公司 | 电路载体、封装及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1887036A (zh) | 2006-12-27 |
DE10355921A1 (de) | 2005-06-30 |
TW200537655A (en) | 2005-11-16 |
DE10355921B4 (de) | 2005-12-22 |
EP1688022A1 (fr) | 2006-08-09 |
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