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WO2007035398A2 - Regulation de la contrainte dans des couches de dispositifs par relachement selectif et prevention du relachement - Google Patents

Regulation de la contrainte dans des couches de dispositifs par relachement selectif et prevention du relachement Download PDF

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Publication number
WO2007035398A2
WO2007035398A2 PCT/US2006/035814 US2006035814W WO2007035398A2 WO 2007035398 A2 WO2007035398 A2 WO 2007035398A2 US 2006035814 W US2006035814 W US 2006035814W WO 2007035398 A2 WO2007035398 A2 WO 2007035398A2
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Prior art keywords
strain
strained
layer
transistor
channel
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PCT/US2006/035814
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WO2007035398A3 (fr
Inventor
Matthew T. Currie
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Amberwave Systems Corporation
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Priority claimed from US11/227,529 external-priority patent/US7335545B2/en
Priority claimed from US11/227,472 external-priority patent/US7307273B2/en
Application filed by Amberwave Systems Corporation filed Critical Amberwave Systems Corporation
Publication of WO2007035398A2 publication Critical patent/WO2007035398A2/fr
Publication of WO2007035398A3 publication Critical patent/WO2007035398A3/fr

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    • H—ELECTRICITY
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
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    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
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    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]

Definitions

  • This invention relates to devices and structures comprising strained semiconductor layers and insulator layers.
  • Strained silicon-on-insulator structures for semiconductor devices combine the benefits of two advanced approaches to performance enhancement: silicon-on-insulator (SOI) technology and strained silicon (Si) technology.
  • SOI silicon-on-insulator
  • Si strained silicon
  • the strained silicon-on-insulator configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation.
  • Strained Si provides improved carrier mobilities.
  • Devices such as strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates.
  • MOSFETs metal-oxide-semiconductor field-effect transistors
  • Strained-silicon-on-insulator substrates are typically fabricated as follows. First, a relaxed silicon-germanium (SiGe) layer is formed on an insulator by one of several techniques such as separation by implantation of oxygen (SIMOX), wafer bonding and etch back; wafer bonding and hydrogen exfoliation layer transfer; or recrystallization of amorphous material. Then, a strained Si layer is epitaxially grown to form a strained-silicon-on-insulator structure, with strained Si disposed over SiGe. The relaxed-SiGe-on-insulator layer serves as the template for inducing strain in the Si layer. This induced strain (i.e., a dimensionless value indicating the change in gauge length of a sample, in the direction of an applied stress, divided by its original gauge length) is typically greater than 10 '3 .
  • This induced strain i.e., a dimensionless value indicating the change in gauge length of a sample, in the direction of an applied stress, divided by
  • This structure has limitations. It is not conducive to the production of fully-depleted strained-silicon-on-insulator devices in which the layer over the insulating material must be thin enough ( ⁇ 300 angstroms [A]) to allow for full depletion of the layer during device operation. Fully depleted transistors may be the favored version of SOI for MOSFET technologies beyond the 90 nm technology node.
  • the relaxed SiGe layer adds to the total thickness of this layer and thus makes it difficult to achieve the small thicknesses required for fully depleted SOI device fabrication.
  • the relaxed SiGe layer is not required, however, if a strained Si layer can be produced directly on the insulating material.
  • a method to produce strained silicon - or other semiconductor - layers directly on insulating substrates there is a need for a method to produce strained silicon - or other semiconductor - layers directly on insulating substrates.
  • a uniformly strained layer may not be preferable for the formation of different types of devices on a single substrate.
  • a pre-amorphization implant (PAI) that may be performed to improve device characteristics may result in strained layer relaxation, leading to a loss of carrier mobility enhancement.
  • the present invention includes a strained-semiconductor-on-insulator (SSOI) substrate structure and methods for fabricating the substrate structure in which strain may be selectively and locally relaxed to improve device operation.
  • MOSFETs fabricated on this substrate will have the benefits of SOI MOSFETs as well as the benefits of strained Si mobility enhancement.
  • SSOI technology is simplified. For example, issues such as the diffusion of Ge into the strained Si layer during high temperature processes are avoided.
  • This approach enables the fabrication of well-controlled, epitaxially-defined, thin strained semiconductor layers directly on an insulator layer.
  • Tensile or compressive strain levels of ⁇ 10 "3 or greater are possible in these structures, and are not diminished after thermal anneal cycles.
  • the strain-inducing relaxed layer is not present in the final structure, eliminating some of the key problems inherent in current strained Si-on-insulator solutions.
  • This fabrication process is suitable for the production of enhanced-mobility substrates applicable to partially or fully depleted SSOI technology.
  • Further processing of the SSOI substrates may include control of the degree of strain and/or relaxation of portions of the strained layer to improve performance of devices fabricated on the SSOI substrates. Such control may be attained by, e.g., selective PAI and incorporation of strain-inducing stressors.
  • the invention features a method for forming a structure, the method including forming a strained semiconductor layer over a first substrate. A strained portion of the strained semiconductor layer is masked, and a portion of the strain is selectively relaxed in at least a portion of the strained semiconductor layer to define a relaxed portion of the strained semiconductor layer. The masked strained portion of the strained semiconductor layer remains strained.
  • Selectively relaxing at least a portion of the strain may include performing a pre-amorphization implant by introducing a dose of isoelectronic ions into the strained semiconductor layer, the dose exceeding a critical dose for amorphization.
  • a thickness of the amorphous region may be more than 50% of a thickness of the strained semiconductor layer.
  • the strained semiconductor layer Prior to selectively relaxing at least a portion of the strain, the strained semiconductor layer may be bonded to a dielectric layer disposed on a second substrate.
  • a first transistor may be formed, including a first channel disposed in the relaxed portion, and a second transistor may be formed, including a second channel disposed in the strained portion.
  • a first strain-inducing stressor may be formed, configured to induce a first type of strain in the first channel, and a second strain-inducing stressor may be formed, configured to induce a second type of strain in the second channel, wherein the first type of strain and the second type of strain are different.
  • the first type of strain may be tensile and the second type of strain may be compressive, or the first type of strain may be compressive and the second type of strain may be tensile.
  • the invention features a method for forming a structure, the method including providing a substrate comprising a strained semiconductor layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the strained semiconductor layer having a first strain.
  • a first transistor such as a MOSFET or a finFET, is formed, including a channel disposed in a portion of the strained semiconductor layer, and a strain- inducing stressor configured to induce a second strain in the channel.
  • the strain-inducing stressor may be at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an over layer disposed over a gate of the transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region and a drain region; (vi) a sidewall spacer; (vii) at least one void disposed below at least one of source region, a drain region, and a channel of the transistor; and (viii) a package.
  • a second transistor may be formed, including a second channel disposed in a second portion of the strained semiconductor layer.
  • the second transistor may further include a second strain-inducing stressor configured to induce a third strain in the second channel.
  • a type of the second strain may be different from a type of the third strain.
  • the first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor.
  • the first channel may be tensilely strained and the second channel may be compressively strained. Alternatively, the first channel may be strained and the second channel may be relaxed.
  • the invention features a structure including a substrate comprising a substantially strained layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the substantially strained layer having a first portion and a second portion.
  • a first transistor has a first strained channel, the first channel disposed in the first portion of the substantially strained layer, and a first strain-inducing stressor inducing only a portion of the strain in the first channel.
  • a second transistor has a second strained channel, the second channel disposed in the second portion of the substantially strained layer. At least one second strain-inducing stressor induces substantially all of the strain in the second channel.
  • the first transistor may be an NMOSFET, and the second transistor may be a PMOSFET. At least one of the first and second transistors may be a finFET.
  • the type of strain induced by the first strain-inducing stressor may be different from the type of strain induced by the at least one second strain-inducing stressor.
  • the type of strain induced by the first strain-inducing stressor may be tensile and the type of strain induced by the at least one second strain-inducing stressor may be compressive.
  • the type of strain induced by the first strain-inducing stressor may be compressive and the type of strain induced by the at least one second strain-inducing stressor may be tensile.
  • the first strain-inducing stressor may be at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the first transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region; (vi) a sidewall spacer of the first transistor; (vii) at least one void disposed below at least one of source region, a drain region, and a channel of the first transistor; and (viii) a package.
  • the at least one second strain-inducing stressor may be at least one of (i) strain- inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the second transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region of the second transistor; (vi) a sidewall spacer; (vii) at least one void disposed below at least one of source region, a drain region, and a channel of the second transistor; and (viii) a package. [0020]
  • the type of strain induced by the second strain-inducing stressor may be different from a type of strain in the substantially strained layer.
  • the invention features a method for forming a structure, the method including providing a substrate comprising a strained semiconductor layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the strained semiconductor layer having a first type of strain.
  • a transistor including a channel disposed in a portion of the strained semiconductor layer, is formed by performing an implant of an isoelectronic species to introduce a plurality of point defects into a region of the strained semiconductor layer.
  • a shallow source and drain implant, and a deep source and drain implant are performed.
  • the point defects may include interstitial defects
  • performing the implant may include performing a pre- amorphization implant to introduce at least a critical dose of interstitial defects into the region of the strained semiconductor layer to amorphize the region.
  • the thickness of the amorphous region may be less than 50% of the thickness of the strained semiconductor layer, e.g., less than 25% of the thickness of the strained semiconductor layer.
  • the amorphized region may be recrystallized.
  • the recrystallized region may have a second type of strain substantially the same as the first type of strain.
  • the first and second types of strain may be tensile strain or compressive strain.
  • the pre-amorphization implant may be performed selectively on the region of the strained semiconductor layer.
  • Forming the transistor may include defining a strain-inducing stressor that induces strain of a same type as the first strain, e.g., tensile strain or compressive strain.
  • the point defects may be lattice vacancies and performing the implant may include performing a co-implant to create lattice vacancies in the region of the strained semiconductor layer, the region of the strained semiconductor layer remaining crystalline.
  • the region of the strained semiconductor layer may include a drain of the transistor and the implant may be performed at an angle of less than 90° with respect to a top surface of the drain. The implant may be performed at a temperature above 25 0 C.
  • the invention features a method for forming a structure, the method including providing a substrate including a strained semiconductor layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate, the strained semiconductor layer having a first strain.
  • a first transistor is formed by (i) defining a channel disposed in a portion of the strained semiconductor layer, (ii) removing at least a portion of the strained semiconductor layer proximate the channel to define a recess, and (iii) selectively depositing a conductive material into the recess to define at least a portion of a source or a drain of the first transistor.
  • the conductive material may include at least one of a metal and a doped semiconductor. After deposition of the conductive material, the channel of the first transistor may have a strain of the same type as the first strain.
  • the invention features a structure including a substrate including a substantially strained layer disposed over and contacting a dielectric layer disposed over a semiconductor substrate.
  • a first transistor has a first strained channel, the first channel disposed in a first portion of the substantially strained layer, and a first stain-inducing stressor inducing a first type of strain in the first channel.
  • a second transistor has a second strained channel, the second channel disposed in a second portion of the substantially strained layer, and a second strain-inducing stressor inducing a second type of strain in the second channel.
  • the first strain may be a same type of strain as the second strain, e.g., tensile strain or compressive strain.
  • the first strain-inducing stressor may be at least one of (i) strain-inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the first transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region; (vi) a sidewall spacer of the first transistor; (vii) at least one void disposed below at least one of source region, a drain region, and a channel of the first transistor; and (viii) a package.
  • the at least one second strain-inducing stressor may be at least one of (i) strain- inducing source and drain regions defined in respective recesses; (ii) an overlayer disposed over a gate of the second transistor; (iii) a shallow-trench isolation region; (iv) a gate electrode; (v) metal-semiconductor alloy disposed on at least one of a gate, a source region, and a drain region of the second transistor; (vi) a sidewall spacer; (vii) at least one void disposed below at least one of source region, a drain region, and a channel of the second transistor; and (viii) a package.
  • the first transistor may be an NMOSFET and the second transistor may be a PMOSFET. At least one of the first and second transistors may be a fmFET.
  • the first stress- inducing stressor may induce only a portion of the strain in the first channel and the second stress-inducing stressor may induce only a portion of the strain in the second channel.
  • Figures IA, IB, 2A, 2B, and 3 - 6 are schematic cross-sectional views of substrates illustrating a method for fabricating an SSOI substrate
  • Figure 7 is a schematic cross-sectional view illustrating an alternative method for fabricating the SSOI substrate illustrated in Figure 6;
  • Figure 8 is a schematic cross-sectional view of a transistor formed on the SSOI substrate illustrated in Figure 6;
  • Figures 9 - 10 are schematic cross-sectional views of substrate(s) illustrating a method for fabricating an alternative SSOI substrate;
  • Figure 11 is a schematic cross-sectional view of a substrate having several layers formed thereon;
  • Figures 12 - 13 are schematic cross-sectional views of substrates illustrating a method for fabricating an alternative strained semiconductor substrate
  • Figure 14 is a schematic cross-sectional view of the SSOI substrate illustrated in Figure 6 after additional processing;
  • Figures 15A, 15B, 16A, 16B, 17A, 17B, 17C, 18A, 18B, 18C, 19A, and 19B are schematic cross-sectional views of single transistors disposed on SSOI substrates, illustrating methods of altering strain in the transistors;
  • Figures 20, 21, 22A, 22B, 23A, 23B, 23C, 23D, 24A, 24B, and 25 are schematic sectional views of pairs of transistors disposed on SSOI substrates, illustrating methods of altering strain in the transistors.
  • An SSOI structure may be formed by wafer bonding followed by cleaving.
  • Figures IA - 2B illustrate formation of a suitable strained layer on a wafer for bonding, as further described below.
  • an epitaxial wafer 108 has a plurality of layers 110 disposed over a substrate 112.
  • Substrate 112 may be formed of a semiconductor, such as Si, Ge, or SiGe.
  • Sii -x Ge x may include Sio. 7 oGe ⁇ 3 o and T 2 may be approximately 1.5 ⁇ m.
  • Relaxed layer 116 may be fully relaxed, as determined by triple axis X-ray diffraction, and may have a threading dislocation density of ⁇ 10 6 dislocations/cm 2 , as determined by etch pit density (EPD) analysis. Because threading dislocations are linear defects disposed within a volume of crystalline material, threading dislocation density may be measured as either the number of dislocations intersecting a unit area within a unit volume or the line length of dislocation per unit volume. Threading dislocation density therefore, may, be expressed in either units of dislocations/cm 2 or cm/cm 3 .
  • Relaxed layer 116 may have a surface particle density of, e.g., less than about 0.3 particles/cm 2 . Further, a relaxed layer 116 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm 2 for particle defects having a size (diameter) greater than 0.13 ⁇ m, a defect level of about 0.2 defects/cm 2 for particle defects having a size greater than 0.16 ⁇ m, a defect level of about 0.1 defects/cm 2 for particle defects having a size greater than 0.2 ⁇ m, and a defect level of about 0.03 defects/cm 2 for defects having a size greater than 1 ⁇ m.
  • Substrate 112, graded layer 114, and relaxed layer 116 may be formed from various materials systems, including various combinations of group II, group III, group IV, group V, and group VI elements.
  • each of substrate 112, graded layer 114, and relaxed layer 116 may include or consist essentially of a III-V compound.
  • Substrate 112 may include or consist essentially of gallium arsenide (GaAs), graded layer 114 and relaxed layer 116 may include or consist essentially of indium gallium arsenide (InGaAs) or aluminum gallium arsenide (AlGaAs). These examples are merely illustrative, and many other material systems are suitable.
  • GaAs gallium arsenide
  • InGaAs indium gallium arsenide
  • AlGaAs aluminum gallium arsenide
  • a strained semiconductor layer 118 is disposed over relaxed layer 116.
  • Strained layer 118 may include or consist essentially of a semiconductor such as at least one of a group II, a group III, a group IV, a group V, and a group VI element.
  • Strained semiconductor layer 118 may include or consist essentially of, for example, Si, Ge, SiGe, GaAs, indium phosphide (InP), and/or zinc selenide (ZnSe).
  • strained semiconductor layer 118 may include approximately 100% Ge, and may be compressively strained.
  • Strained layer 118 has a thickness T 3 of, for example, 50 - 1000 A. In an embodiment, T3 may be approximately 200 - 500 A.
  • Strained layer 118 may be formed by epitaxy, such as by atmospheric-pressure CVD (APCVD), low- (or reduced-) pressure CVD (LPCVD), ultra-high-vacuum CVD (UHVCVD), by molecular beam epitaxy (MBE), or by atomic layer deposition (ALD).
  • APCVD atmospheric-pressure CVD
  • LPCVD low- (or reduced-) pressure CVD
  • UHVCVD ultra-high-vacuum CVD
  • MBE molecular beam epitaxy
  • ALD atomic layer deposition
  • Strained layer 118 containing Si may be formed by CVD with precursors such as silane, disilane, or trisilane.
  • Strained layer 118 containing Ge may be formed by CVD with precursors such as germane or digermane.
  • the epitaxial growth system may be a single-wafer or multiple-wafer batch reactor. The growth system may also utilize a low-energy plasma to enhance layer growth kinetics.
  • Strained layer 118 may be formed at a relatively low temperature, e.g., less than 700 0 C, to facilitate the definition of an abrupt interface 117 between strained layer 118 and relaxed layer 116.
  • This abrupt interface 117 may enhance the subsequent separation of strained layer 118 from relaxed layer 116, as discussed below with reference to Figures 4 and 5.
  • Abrupt interface 117 is characterized by the transition of Si or Ge content (in this example) proceeding in at least 1 decade (order of magnitude in atomic concentration) per nanometer of depth into the sample. In an embodiment, this abruptness may be better than 2 decades per nanometer.
  • strained layer 118 may be formed in a dedicated chamber of a deposition tool that is not exposed to Ge source gases, thereby avoiding cross-contamination and improving the quality of the interface between strained layer 118 and relaxed layer 116. Furthermore, strained layer 118 may be formed from an isotopically pure silicon precursor(s). Isotopically pure Si has better thermal conductivity than conventional Si. Higher thermal conductivity may help dissipate heat from devices subsequently formed on strained layer 118, thereby maintaining the enhanced carrier mobilities provided by strained layer 118. [0042] After formation, strained layer 118 has an initial misfit dislocation density, of, for example, 0 - 10 s cm/cm 2 .
  • strained layer 118 has an initial misfit dislocation density of approximately 0 cm/cm 2 . Because misfit dislocations are linear defects generally lying within a plane between two crystals within an area, they may be measured in terms of total line length per unit area. Misfit dislocation density, therefore, may be expressed in units of dislocations/cm or cm/cm 2 .
  • strained layer 118 is tensilely strained, e.g., Si formed over SiGe. In another embodiment, strained layer 118 is compressively strained, e.g., Ge formed over SiGe.
  • Strained layer 118 may have a surface particle density of, e.g., less than about 0.3 particles/cm 2 .
  • surface particle density includes not only surface particles but also light-scattering defects, and crystal-originated pits (COPs), and other defects incorporated into strained layer 118.
  • strained layer 118 produced in accordance with the present invention may have a localized light-scattering defect level of less than about 0.3 defects/cm 2 for particle defects having a size (diameter) greater than 0.13 ⁇ m, a defect level of about 0.2 defects/cm 2 for particle defects having a size greater than 0.16 ⁇ m, a defect level of about 0.1 defects/cm 2 for particle defects having a size greater than 0.2 ⁇ m, and a defect level of about 0.03 defects/cm 2 for defects having a size greater than 1 ⁇ m.
  • Process optimization may enable reduction of the localized light-scattering defect levels to about 0.09 defects/cm 2 for particle defects having a size greater than 0.09 ⁇ m and to 0.05 defects/cm 2 for particle defects having a size greater than 0.12 ⁇ m.
  • These surface particles may be incorporated in strained layer 118 during the formation of strained layer 118, or they may result from the propagation of surface defects from an underlying layer, such as relaxed layer 116.
  • graded layer 114 may be absent from the structure.
  • Relaxed layer 116 may be formed in various ways, and the invention is not limited to embodiments having graded layer 114.
  • strained layer 118 may be formed directly on substrate 112. In this case, the strain in layer 118 may be induced by lattice mismatch between layer 118 and substrate 112; or induced mechanically, e.g., by the deposition of overlayers, such as SisN 4 ; or induced by thermal mismatch between layer 118 and a subsequently grown layer, such as a SiGe layer.
  • a uniform semiconductor layer (not shown), having a thickness of approximately 0.5 ⁇ m and comprising the same semiconductor material as substrate 112, is disposed between graded buffer layer 114 and substrate 112.
  • This uniform semiconductor layer may be grown to improve the material quality of layers subsequently grown on substrate 112, such as graded buffer layer 114, by providing a clean, contaminant-free surface for epitaxial growth.
  • relaxed layer 116 may be planarized prior to growth of strained layer 118 to eliminate the crosshatched surface roughness induced by graded buffer layer 114. (See, e.g., M. T. Currie, et al., Appl. Phys. Lett, 72 (14) p.
  • the planarization may be performed by a method such as chemical mechanical polishing (CMP), and may improve the quality of a subsequent bonding process (see below) because it minimizes the wafer surface roughness and increases wafer flatness, thus providing a greater surface area for bonding.
  • CMP chemical mechanical polishing
  • a relaxed semiconductor regrowth layer 119 including a semiconductor such as SiGe may be grown on relaxed layer 116, thus improving the quality of subsequent strained layer 118 growth by ensuring a clean surface for the growth of strained layer 118.
  • strained material e.g., silicon
  • the conditions for epitaxy of the relaxed semiconductor regrowth layer 119 on the planarized relaxed layer 116 should be chosen such that surface roughness of the resulting structure, including layers formed over regrowth layer 119, is minimized to ensure a surface suitable for subsequent high quality bonding.
  • High quality bonding may be defined as the existence of a bond between two wafers that is substantially free of bubbles or voids at the interface.
  • Measures that may help ensure a smooth surface for strained layer 118 growth, thereby facilitating bonding include substantially matching a lattice of the semiconductor regrowth layer 119 to that of the underlying relaxed layer 116, by keeping the regrowth thickness below approximately 1 ⁇ m, and/or by keeping the growth temperature below approximately 850 0 C for at least a portion of the semiconductor layer 119 growth. It may also be advantageous for relaxed layer 116 to be substantially free of particles or areas with high threading dislocation densities (i.e., threading dislocation pile-ups) which could induce non-planarity in the regrowth and decrease the quality of the subsequent bond.
  • H 2 hydrogen ions are implanted into relaxed layer 116 to define a cleave plane 120.
  • This implantation is similar to the SMARTCUT process that has been demonstrated in silicon by, e.g., SOITEC, S.A., based in Grenoble, France.
  • Implantation parameters may include implantation of hydrogen (H 2 ) to a dose of 2.5- 5 x 10 16 ions/cm at an energy of, e.g., 50 - 100 keV.
  • H 2 + may be implanted at an energy of 75 keV and a dose of 4 x 10 l ⁇ ions/cm 2 through strained layer 118 into relaxed layer 116.
  • other implanted species may be used, such as H + or He + , with the dose and energy being adjusted accordingly.
  • the implantation may also be performed prior to the formation of strained layer 118.
  • the subsequent growth of strained layer 118 is preferably performed at a temperature low enough to prevent premature cleaving along cleave plane 120, i.e., prior to the wafer bonding process.
  • This cleaving temperature is a complex function of the implanted species, implanted dose, and implanted material. Typically, premature cleaving may be avoided by maintaining a growth temperature below approximately 500 0 C.
  • a thin layer 121 of another material, such as Si, may be formed over strained layer 118 prior to bonding (see discussion with respect to Figure 3).
  • This thin layer 121 may be formed to enhance subsequent bonding of strained layer 118 to an insulator, such as an oxide.
  • Thin layer 121 may have a thickness T 2 i of, for example, 0.5 - 5 nm.
  • strained layer 118 may be planarized by, e.g., CMP, to improve the quality of the subsequent bond.
  • Strained layer 118 may have a low surface roughness, e.g., less than 0.5 nm root mean square (RMS).
  • a dielectric layer 122 may be formed over strained layer 118 prior to ion implantation into relaxed layer 116 to improve the quality of the subsequent bond.
  • Dielectric layer 122 may be, e.g., silicon dioxide (SiO 2 ) deposited by, for example, LPCVD or by high density plasma (HDP).
  • An LPCVD deposited SiO 2 layer may be subjected to a densification step at elevated temperature.
  • Suitable conditions for this densification step may be, for example, a 10 minute anneal at 800 0 C in a nitrogen ambient.
  • dielectric layer 122 may include low-temperature oxide (LTO), which may be subsequently densified at elevated temperature in nitrogen or oxygen ambients.
  • LTO low-temperature oxide
  • Suitable conditions for this densification step can be a 10 minute anneal at 800 0 C in an oxygen ambient.
  • Dielectric layer 122 may be planarized by, e.g., CMP to improve the quality of the subsequent bond.
  • strained layer 118 comprises approximately 100% Ge and dielectric layer 122 comprises, for example, germanium dioxide (GeO 2 ); germanium oxynitride (GeON); a high-k insulator having a higher dielectric constant than that of Si such as hafnium oxide (HfO 2 ) or hafnium silicate (HfSiON, HfSiO 4 ); or a multilayer structure including GeO 2 and SiO 2 .
  • Ge has an oxidation behavior different from that of Si, and the deposition methods may be altered accordingly.
  • epitaxial wafer 108 is bonded to a handle wafer 150.
  • Either handle wafer 150, epitaxial wafer 108, or both have a top dielectric layer (see, e.g., dielectric layer 122 in Figure 2B) to facilitate the bonding process and to serve as an insulator layer in the final substrate structure.
  • Handle wafer 150 may have a dielectric layer 152 disposed over a semiconductor substrate 154.
  • Dielectric layer 152 may include or consist essentially of, for example, SiO 2 .
  • dielectric layer 152 includes a material having a melting point (T m ) higher than a T m of pure SiO 2 , i.e., higher than 1700 0 C.
  • handle wafer 150 may include a combination of a bulk semiconductor material and a dielectric layer, such as an SOI substrate.
  • Semiconductor substrate 154 includes or consists essentially of a semiconductor material such as, for example, Si, Ge, or SiGe.
  • Handle wafer 150 and epitaxial wafer 108 are cleaned by a wet chemical cleaning procedure to facilitate bonding, such as by a hydrophilic surface preparation process to assist the bonding of a semiconductor material, e.g., strained layer 118, to a dielectric material, e.g., dielectric layer 152.
  • DI deionized
  • top surfaces 160, 162 of handle wafer 150 and epitaxial wafer 108 may be subjected to a plasma activation, either before, after, or instead of a wet clean, to increase the bond strength.
  • the plasma environment may include at least one of the following species: oxygen, ammonia, argon, nitrogen, diborane, and phosphine.
  • the bond strength may be greater than 1000 mJ/m 2 , achieved at a low temperature, such as less than 600 0 C.
  • a split is induced at cleave plane 120 by annealing handle wafer 150 and epitaxial wafer 108 after they are bonded together. This split may be induced by an anneal at 300 - 700 "C, e.g., 550 0 C, inducing hydrogen exfoliation layer transfer (i.e., along cleave plane 120) and resulting in the formation of two separate wafers 170, 172.
  • One of these wafers (i.e., wafer 170) has a first portion 180 of relaxed layer 116 (see Figure IA) disposed over strained layer 118. Strained layer 118 is in contact with dielectric layer 152 on semiconductor substrate 154.
  • the other of these wafers (i.e., wafer 172) includes substrate 112, graded layer 114, and a remaining portion 182 of relaxed layer 116.
  • wafer splitting may be induced by mechanical force in addition to or instead of annealing.
  • wafer 170 with strained layer 118 may be annealed further at 600 - 900 °C, e.g., at a temperature greater than 800 0 C, to strengthen the bond between the strained layer 118 and dielectric layer 152. In some embodiments, this anneal is limited to an upper temperature of about 900 0 C to avoid the destruction of a strained Si/relaxed SiGe heterojunction by diffusion.
  • Wafer 172 may be planarized, and used as starting substrate 8 for growth of another strained layer 118. In this manner, wafer 172 may be "recycled" and the process illustrated in Figures IA - 5 may be repeated.
  • An alternative "recycling" method may include providing relaxed layer 116 that is several ⁇ m thick and repeating the process illustrated in Figures IA - 5, starting with the formation of strained layer 118. Because the formation of this thick relaxed layer 116 may lead to bowing of substrate 112, a layer including, e.g., oxide or nitride, may be formed on the backside of substrate 112 to counteract the bowing. Alternatively substrate 112 may be pre- bowed when cut and polished, in anticipation of the bow being removed by the formation of thick relaxed layer 116. W
  • relaxed layer portion 180 is removed from strained layer 118.
  • removal of relaxed layer portion 180, containing, e.g., SiGe includes oxidizing the relaxed layer portion 180 by wet (steam) oxidation. For example, at temperatures below approximately 800 0 C, such as temperatures between 600 - 750 0 C, wet oxidation will oxidize SiGe much more rapidly then Si, such that the oxidation front will effectively stop when it reaches the strained layer 118, in embodiments in which strained layer 118 includes Si. The difference between wet oxidation rates of SiGe and Si may be even greater at lower temperatures, such as approximately 400 0 C - 600 0 C.
  • SiGe may be efficiently removed at low temperatures with oxidation stopping when strained layer 118 is reached.
  • This wet oxidation results in the transformation of SiGe to a thermal insulator 184, e.g., Si x Ge y O z .
  • the thermal insulator 184 resulting from this oxidation is removed in a selective wet or dry etch, e.g., wet hydrofluoric acid. In some embodiments, it may be more economical to oxidize and strip several times, instead of just once. [0053] In certain embodiments, wet oxidation may not completely remove the relaxed layer portion 180.
  • a localized rejection of Ge may occur during oxidation, resulting in the presence of a residual Ge-rich SiGe region at the oxidation front, on the order of, for example, several nanometers in lateral extent.
  • a surface clean may be performed to remove this residual Ge.
  • the residual Ge may be removed by a dry oxidation at, e.g., 600 0 C, after the wet oxidation and strip described above.
  • Another wet clean may be performed in conjunction with - or instead of- the dry oxidation.
  • Examples of possible wet etches for removing residual Ge include a Piranha etch, i.e., a wet etch that is a mixture of sulfuric acid and hydrogen peroxide (H 2 SO 4 IH 2 O 2 ) at a ratio of, for example, 3:1.
  • An HF dip may be performed after the Piranha etch.
  • an RCA SCl clean may be used to remove the residual Ge.
  • the process of Piranha or RCA SCl etching and HF removal of resulting oxide may be repeated more than once.
  • relaxed layer portion including, e.g., SiGe is removed by etching and annealing under a hydrochloric acid (HCl) ambient.
  • HCl hydrochloric acid
  • the surface Ge concentration of the final strained Si surface is preferably less than about 10 12 atoms/cm 2 when measured by a technique such as total reflection x-ray fluorescence (TXRF) or the combination of vapor phase decomposition (VPD) with a spectroscopy technique such as graphite furnace atomic absorption spectroscopy (GFAAS) or inductively-coupled plasma mass spectroscopy (ICP-MS).
  • TXRF total reflection x-ray fluorescence
  • VPD vapor phase decomposition
  • a spectroscopy technique such as graphite furnace atomic absorption spectroscopy (GFAAS) or inductively-coupled plasma mass spectroscopy (ICP-MS).
  • GFAAS graphite furnace atomic absorption spectroscopy
  • ICP-MS inductively-coupled plasma mass spectroscopy
  • a planarization step or a wet oxidation step may be performed to remove a portion of the damaged relaxed layer portion 180 as well as to increase the smoothness of its surface.
  • a smoother surface may improve the uniformity of subsequent complete removal of a remainder of relaxed layer portion 180 by, e.g., wet chemical etching.
  • strained layer 118 may be planarized. Planarization of strained layer 118 may be performed by, e.g., CMP; an anneal at a temperature greater than, for example, 800 0 C, in a hydrogen (H 2 ) or hydrochloric acid (HCl) containing ambient; or cluster ion beam smoothing.
  • an SSOI substrate 190 has strained layer 118 disposed over an insulator, such as dielectric layer 152 formed on semiconductor substrate 154.
  • Strained layer 118 has a thickness T 4 selected from a range of, for example, 50 - 1000 A, with a thickness uniformity of better than approximately ⁇ 5% and a surface roughness of less than approximately 20 A.
  • Dielectric layer 152 has a thickness T5 2 selected from a range of, for example, 500 - 3000 A.
  • strained layer 118 includes approximately 100% Si or 100% Ge having one or more of the following material characteristics: misfit dislocation density of, e.g., 0 - 10 5 cm/cm 2 ; a threading dislocation density of about lO'-lO 7 dislocations/cm 2 ; a surface roughness of approximately 0.01 - 1 nm RMS; and a thickness uniformity across SSOI substrate 190 of better than approximately ⁇ 10% of a mean desired thickness; and a thickness T 4 of less than approximately 200 A.
  • SSOI substrate 190 has a thickness uniformity of better than approximately ⁇ 5% of a mean desired thickness.
  • dielectric layer 152 has a T m greater than that of SiO 2 .
  • SSOI substrate 190 may be subjected to high temperatures, i.e., up to 1100 0 C. High temperatures may result in the relaxation of strained layer 118 at an interface between strained layer 118 and dielectric layer 152.
  • the use of dielectric layer with a T m greater than 1700 0 C may help keep strained layer 118 from relaxing at the interface between strained layer 118 and dielectric layer 152 when SSOI substrate is subjected to high temperatures.
  • the misfit dislocation density of strained layer 118 may be lower than its initial dislocation density.
  • the initial dislocation density may be lowered by, for example, performing an etch of a top surface 186 of strained layer 118.
  • This etch may be a wet etch, such as a standard microelectronics clean step such as an RCA SCl, i.e., hydrogen peroxide, ammonium hydroxide, and water (H 2 O 2 + NH 4 OH + H 2 O), which at, e.g., 80 0 C may remove silicon.
  • bonding voids may have a density equivalent to the density of surface particles formed on strained layer 118, e.g., less than about 0.3 voids/cm 2 .
  • strained semiconductor layer 118 includes or consists essentially of Si and is substantially free of Ge; further, any other layer disposed in contact with strained semiconductor layer 118 prior to device processing, e.g., dielectric layer 152, is also substantially free of Ge.
  • relaxed layer portion 180 may be removed by a selective wet etch that stops at the strained layer 118 to obtain SSOI substrate 190 (see Fig. 6).
  • a suitable selective SiGe wet etch may be a solution containing nitric acid (HNO 3 ) and dilute HF at a ratio of 3:1 or a solution containing H 2 O 2 , HF, and acetic acid (CH 3 COOH) at a ratio of 2:1:3.
  • relaxed layer portion 180 may be removed by a dry etch that stops at strained layer 118.
  • relaxed layer portion 180 may be removed completely or in part by a chemical-mechanical polishing step or by mechanical grinding.
  • SSOI substrate 190 may be further processed by CMOS SOI MOSFET fabrication methods.
  • CMOS SOI MOSFET fabrication methods some portions of substantially strained layer 118 may be unintentionally relaxed slightly, for example, during the patterning of the strained layer 118 into smaller regions, such as by the definition shallow trench isolation regions. Some elastic relaxation may occur in some portions of the strained layer 118, particularly near the edges of the smaller defined regions.
  • strained layer 118 may include such unintentionally relaxed portions, as well as intentionally relaxed portions, as discussed below with reference to Figures 14 - 25.
  • a transistor 200 may be formed on SSOI substrate 190.
  • Forming transistor 200 includes forming a gate dielectric layer 210 above strained layer 118 by, for example, growing an SiO 2 layer by thermal oxidation.
  • gate dielectric layer 210 may include or consist essentially of a high-k material with a dielectric constant higher than that of SiO 2 , such as HfO 2 , HfSiON, or HfSiO 4 .
  • gate dielectric layer 210 may be a stacked structure, e.g., a thin SiO 2 layer capped with a high-k material.
  • a gate 212 is formed over gate dielectric layer 210.
  • Gate 212 may be formed of a conductive material, such as doped semiconductor, e.g., polycrystalline Si or polycrystalline SiGe; a metal, e.g., titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), nickel (Ni), or iridium (Ir); or metal compounds, e.g., titanium nitride (TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), tantalum nitride (TaN), tantalum suicide (TaSi), nickel suicide (NiSi), or iridium oxide (IrO 2 ), that provide an appropriate workfunction.
  • a conductive material such as doped semiconductor, e.g., polycrystalline Si or polycrystalline SiGe
  • a metal e.g., titanium (Ti), tungsten (W), molybdenum (Mo), tantalum (Ta), nickel (Ni),
  • a source region 214 and a drain region 216 are formed in a portion 218 of strained semiconductor layer 118, proximate gate dielectric layer 210.
  • Source and drain regions 214, 216 may be formed by, e.g., ion implantation of either n-type or p- type dopants.
  • strained semiconductor layer 118 may be compressively strained when, for example, layer 118 includes strained Ge. Compressively strained layers may be prone to undulation when subjected to large temperature changes. The risk of such undulation may be reduced by reducing the thermal budget of a process for fabricating devices, such as transistor 200. The thermal budget may reduced by, for example, using ALD to deposit gate dielectric layer 210.
  • a maximum temperature for forming gate 212 may be limited to, e.g., 600 0 C by, for example, the use of materials comprising metal or metal compounds, rather than polysilicon or other gate materials that may require higher formation and/or dopant activation temperatures.
  • a transistor 250 formed on SSOI substrate 190 may have an elevated source region and an elevated drain region proximate a first and a second sidewall spacer 252, 254. These elevated regions may be formed as follows.
  • a semiconductor layer 256a - 256c is fo ⁇ ned selectively on exposed silicon surfaces, i.e., on top surface 258 of a gate 259 containing silicon, a top surface 260 of a source 262 defined in strained layer 118, and a top surface 264 of a drain 266 defined in strained layer 118.
  • semiconductor layer 256a - 256c is an epitaxial layer, such as epitaxial silicon, epitaxial germanium, or epitaxial silicon-germanium.
  • No semiconductor layer is fo ⁇ ned on non-silicon features, such as sidewall spacers 252, 254 and dielectric isolation regions 268, 270.
  • Semiconductor layer 256a - 256c has a thickness T 256 of, for example, approximately 100 - 500 A.
  • Semiconductor layer 256a - 256c has a low resistivity of, e.g., 0.001 ⁇ -cm, that facilitates the formation of low-resistance contacts.
  • semiconductor layer 256a - 256c is, for example, epitaxial silicon doped with, for example, arsenic to a concentration of 10 20 atoms/cm 3 .
  • Semiconductor layer 256a - 256c may be doped in situ, during deposition. In alternative embodiments, semiconductor layer 256a - 256c may be doped after deposition by ion implantation or by gas-, plasma- or solid-source diffusion.
  • the doping of semiconductor layer 256a - 256c and the formation of source 262 and drain 266 are performed simultaneously. Portions of semiconductor layer 256a, 256c disposed over source 262 and drain 266 may have top surfaces substantially free of facets. In an embodiment, portions of source 262, drain 266, and/or gate 259 may be etched away to define recess prior to deposition of semiconductor layer 256a - 256c, and semiconductor layer 256a - 256c may then be deposited in the recesses thus formed.
  • Metal layer 272 is formed over transistor 250.
  • Metal layer 272 is formed by, for example, sputter deposition.
  • Metal layer 272 has a thickness T2 72 of, e.g., 50 - 200 A and includes or consists essentially of a metal such as cobalt, titanium, tungsten, nickel, or platinum.
  • the metal is selected to react with semiconductor layer 256a - 256c to form a low-resistance metal-semiconductor alloy when exposed to heat, as described below.
  • the metal is also selected such that the metal-semiconductor alloy remains stable at temperatures typically required to complete transistor 250 fabrication, e.g., 400 - 700 0 C.
  • a first rapid thermal anneal is performed, e.g., at 550 0 C for 60 seconds.
  • This heating step initiates a reaction between metal layer 272 and semiconductor layers 256a - 256c, forming a high resistivity phase of a metal-semiconductor alloy, e.g., cobalt suicide (CoSi).
  • a metal-semiconductor alloy e.g., cobalt suicide (CoSi).
  • Portions of metal layer 272 are removed by a wet etch, such as sulfuric acid and hydrogen peroxide.
  • the wet etch may be ammonium hydroxide, peroxide, and water.
  • SSOI substrate 190 including transistor 250, is subjected to a second heat treatment.
  • SSOI substrate 190 undergoes a rapid thermal anneal at 800 0 C for 60 seconds in a nitrogen ambient.
  • This heating step initiates a reaction in the metal-semiconductor alloy layer which substantially lowers its resistivity, to form a substantially homogeneous contact layer 276a - 276c.
  • Contact layer 276a - 276c includes or consists essentially of a metal-semiconductor alloy, e.g., a metal suicide such as a low resistivity phase of cobalt suicide (CoSi 2 ).
  • Contact layer 276a - 276c has a thickness T 276 of, for example, 400 A.
  • Contact layer 276a - 276c has a low sheet resistance, e.g., less than about 10 ⁇ /D, and enables a good quality contact to be made to source 262 and drain 266, as well as to gate 259.
  • contact layer 276a - 276c may consume substantially all of semiconductor layer 256a - 256c.
  • a bottommost boundary 278a of contact layer 276a therefore, shares an interface 280a with strained layer 118 in source 262, and a bottommost boundary 278c of contact layer 276c, therefore, shares an interface 280c with strained layer 118 in drain 266.
  • a bottommost boundary 278b of contact layer 276b shares an interface 280b with gate 259.
  • contact layer portions 276a, 276c, disposed over source 262 and drain 266, may extend into strained layer 118.
  • Interfaces 280a, 280c between contact layer 276a, 276c and strained layer 118 are then disposed within source 262 and drain 266, respectively, above bottommost boundaries 282a, 282c of strained layer 118.
  • Interfaces 280a, 280c have a low contact resistivity, e.g., less than approximately 5 x 10 "7 ⁇ -cm 2 .
  • contact layer 276a - 276c may not consume all of semiconductor layer 256a - 256c (see Figure 8D).
  • a bottommost boundary 278a of contact layer 276a therefore, shares an interface with semiconductor layer 256a over source 262, and a bottommost boundary 278c of contact layer 276c shares an interface with semiconductor layer 256c over drain 266.
  • strained layer 118 includes a strained material, carrier mobilities in strained layer 118 are enhanced, facilitating lower sheet resistances. This strain also results in a reduced energy bandgap, thereby lowering the contact resistivity between the metal-semiconductor alloy and the strained layer.
  • an SSOI structure may include, instead of a single strained layer, a plurality of semiconductor layers disposed on an insulator layer.
  • epitaxial wafer 300 includes strained layer 118, relaxed layer 116, graded layer 114, and substrate 112.
  • a semiconductor layer 310 is disposed over strained layer 118.
  • Strained layer 118 may be tensilely strained and semiconductor layer 310 may be compressively strained.
  • strained layer 118 may be compressively strained and semiconductor layer 310 may be tensilely strained.
  • Strain may be induced by lattice mismatch with respect to an adjacent layer, as described above, or mechanically. For example, strain may be induced by the deposition of overlayers, such as Si3N 4 .
  • semiconductor layer 310 is relaxed.
  • Semiconductor layer 310 includes or consists essentially of W 2
  • Epitaxial wafer 300 is processed in a manner analogous to the processing of epitaxial wafer 108, as described with reference to Figures 1 - 7. [0073] Referring also to Figure 10, processing of epitaxial wafer 300 results in the formation of SSOI substrate 350, having strained layer 118 disposed over semiconductor layer 310. Semiconductor layer 310 is bonded to dielectric layer 152, disposed over substrate 154. As noted above with reference to Figure 9, strained layer 118 may be tensilely strained and semiconductor layer 310 may be compressively strained. Alternatively, strained layer 118 may be compressively strained and semiconductor layer 310 may be tensilely strained. In some embodiments, semiconductor layer 310 may be relaxed.
  • a thin strained layer 360 may be grown between strained layer 118 and relaxed layer 116 to act as an etch stop during etching, such as wet etching.
  • thin strained layer 360 may include Sii -x Ge x> with a higher Ge content (x) than the Ge content (y) of relaxed layer 116, and hence will be compressively strained. For example, if the composition of the relaxed layer 116 is 20% Ge (Sio.8oGeo. 2 o), thin strained layer 360 may contain 40% Ge (Sio.6oGeo.
  • a second strained layer such as thin strained layer 360 with higher Ge content than relaxed layer 116, may act as a preferential cleave plane in the hydrogen exfoliation/cleaving procedure described above.
  • thin strained layer 360 may contain Si] -x Ge x with lower Ge content than relaxed layer 116.
  • thin strained layer 360 may act as a diffusion barrier during the wet oxidation process. For example, if the composition of relaxed layer 116 is 20% Ge (Sio.8oGe o . 2 o), thin strained layer 360 may contain 10% Ge (Sio.9oGeo. 1 o) to provide a barrier to Ge diffusion from the higher Ge content relaxed layer 116 during the oxidation process.
  • thin strained layer 360 may be replaced with a thin graded SJi -2 Ge 2 layer in which the Ge composition (z) of the graded layer is decreased from relaxed layer 116 to the strained layer 118.
  • a small amount, e.g., approximately 20 - 100 A, of strained layer 118 may be removed at an interface 194 between strained layer 118 and relaxed layer portion 180. This may be achieved by overetching after relaxed layer portion 180 is removed. Alternatively, this removal of strained layer 118 may be W
  • a standard microelectronics clean step such as an RCA SCl, i.e., hydrogen peroxide, ammonium hydroxide, and water (H 2 O 2 + NH 4 OH + H 2 O), which at, e.g., 8O 0 C may remove silicon.
  • This silicon removal may remove any misfit dislocations that formed at the original strained layer 118/relaxed layer 180 interface 194 if strained layer 118 was grown above the critical thickness.
  • the critical thickness may be defined as the thickness of strained layer 118 beyond which it becomes energetically favorable for the strain in the layer to partially relax via the introduction of misfit dislocations at interface 194 between strained layer 118 and relaxed layer 116.
  • the method illustrated in Figures 1 - 7 provides a technique for obtaining strained layers above a critical thickness without misfit dislocations that may compromise the performance of deeply scaled MOSFET devices.
  • handle wafer 150 may have a structure other than a dielectric layer 152 disposed over a semiconductor substrate 154.
  • a bulk relaxed substrate 400 may comprise or consist essentially of a bulk material 410 such as a semiconductor material, e.g., bulk silicon.
  • bulk material 410 may be a bulk dielectric material, such as Al 2 ⁇ 3 (e.g., alumina or sapphire) or SiO 2 (e.g., quartz).
  • Epitaxial wafer 108 may then be bonded to handle wafer 400 (as described above with reference to Figures 1 - 6), with strained layer 118 being bonded to the bulk material 410 comprising handle wafer 400.
  • a hydrophobic clean may be performed, such as an HF dip after an RCA SC 1 clean.
  • a strained-semiconductor-on-semiconductor (SSOS) substrate 420 is formed, having strained layer 118 disposed in contact with relaxed substrate 400.
  • the strain of strained layer 118 is not induced by underlying relaxed substrate 400, and is independent of any lattice mismatch between strained layer 118 and relaxed substrate 400.
  • strained layer 118 and relaxed substrate 400 include the same semiconductor material, e.g., silicon.
  • Relaxed substrate 400 may have a lattice constant equal to a lattice constant of strained layer 118 in the absence of strain.
  • Strained layer 118 may have a strain greater than approximately 10 "3 .
  • Strained layer 118 may have been formed by epitaxy, and may have a thickness T 5 of between approximately 20 A - 1000 A, with a thickness uniformity of better than approximately ⁇ 10%. In an embodiment, strained layer 118 may have a thickness uniformity of better than approximately ⁇ 5%. Surface 186 of strained layer 118 may have a surface roughness of less than 20 A. [0079] A PAI may be performed prior to a source/drain implantation step to reduce channeling in the source/drain regions, thereby enabling the creation of a tighter distribution of source/drain dopants and, thereby, providing abrupt junctions for the source/drain regions.
  • strained active area regions i.e., strained channel and/or source/drain regions
  • This phenomenon is preferably either prevented or combined with various strain-inducing techniques to improve device performance.
  • it may be favorable to selectively relax the strain in at least a portion of strained layer 118.
  • Ion implantation parameters may be, for example, an implant of Si ions at a dose of 10 15 - 10 17 ions/cm 2 , at an energy of 5 - 75 keV.
  • the formation of a MOSFET 1500 on SSOI substrate 190 may include definition of shallow trench isolation (STI) regions 1510, a gate dielectric layer 1520, a gate electrode 1530, and a channel 1535, as is known in the art.
  • shallow source and drain extension regions 1540, 1540' may be formed by, e.g., a shallow ion implantation of the same dopant type as will be used to define the source and drain (see below).
  • a thin dielectric layer 1542 may be formed over SSOI substrate 190 prior to any implantation to prevent the introduction of impurities into MOSFET 1500.
  • the thin dielectric layer 1542 may later become part of a sidewall spacer (see below).
  • the thin dielectric layer 1542 may include or consist • essentially of silicon dioxide or silicon nitride, and may be formed by deposition or oxidation.
  • a PAI 1545 i.e., an implant of a plurality of ions, such as of Si, Ge, or noble gas atoms (e.g., Ar, Kr, or Xe) may be performed to amorphize a region 1550 of the strained layer 118 that is deeper than an eventual desired depth of the shallow source and drain extension regions 1540, 1540'.
  • the atomic species selected for the PAI is preferably isoelectronic, i.e., non-doping, with respect to strained layer 118.
  • the atomic species is relatively heavy, i.e., has a high atomic number, with respect to the material of the strained layer 118, thereby facilitating the inducement of lattice damage. Lattice damage is more easily and cheaply attained with a heavy atom.
  • Xe atoms are introduced into strained layer 118 that consists essentially of Si.
  • the dose is greater than a critical dose for amorphization, i.e., greater than the dose at which the density of point defects introduced into the strained layer 118 exceeds about 10% of the atomic density of the atomic layer.
  • the dose may be greater than 0.5 x 10 14 atoms/cm 2 , and in some embodiments, may be greater than 1 x 10 15 atoms/cm 2 .
  • the critical dose for amorphizing silicon may be calculated by:
  • N 01Jt is the critical dose
  • ⁇ R P is the implant straggle
  • N is the target atom density
  • E 0 is the beam energy
  • E d is the atom displacement energy (approximately 14 - 15 eV for Si and GaAs).
  • a non- amorphized region 1560 of the strained layer 118 having a thickness Te of, e.g., about 10 nm below the amorphized region 1550 is sufficient for recrystallization to occur.
  • the thickness of the amorphous region may be thicker than 50% of the thickness of strained layer 118.
  • a desired dopant species 1570 for the shallow source and drain extension regions 1540, 1540' is implanted into the amorphized regions 1550.
  • the dopant species implanted for the shallow source and drain extension regions 1540, 1540' may be, for example, either n- or p-type dopants, such as B, BF 2, As, P, In, or Sb.
  • a recrystallization anneal is performed to recrystallize the amorphized region 1550 to restore mobility enhancement. Although the channel 1535 was not amorphized, device performance may be improved if lattice damage is healed. Carrier scattering may occur if carriers are transported from a crystalline region to an amorphous region or vice versa.
  • the dopants introduced for the shallow source and drain extension regions 1540, 1540' may be activated during a solid-phase recrystallization process having a relatively low thermal budget.
  • suitable anneals are an anneal at ⁇ 800 0 C for 1 - 30 minutes, an anneal at >900 0 C for less than 10 seconds, an anneal at >1000 0 C for less than 5 seconds, or a laser anneal for less than 1 second or even less than 0.5 seconds, e.g., less than 100 nanoseconds.
  • a suitable laser annealing energy is less than approximately 1 Joules/cm 2 (J/cm 2 ), preferably less than 0.5 J/cm 2 .
  • J/cm 2 the amorphous region 1550 created by the PAI recrystallizes, incorporating the dopant implanted during the shallow source and drain extension region formation step.
  • the low thermal budget of this annealing step reduces the diffusion of the implanted dopants, thereby helping to ensure an abrupt junction between the dopants and the remainder of strained layer 118.
  • the PAI provides several advantages. Because the dopants for the shallow source and drain extension regions 1540, 1540' are implanted into an amorphous region 1550 substantially free of long-range crystalline order, implant channeling does not occur, and the implant profile is very abrupt.
  • the amorphous region 1550 is non-crystalline, i.e., it does not have a regular atomic spacing and lattice that repeats in a regular fashion over many layers.
  • the creation of the amorphous region 1550 helps prevent transient enhanced diffusion (TED) by blocking interstitial defects that tend to form below a peak of a dopant implant.
  • TED transient enhanced diffusion
  • a reduced PAI dose of less than a critical dose i.e., ⁇ 5 x 10 14 cm '2 and/or at a lower energy may be used, such that the amorphous region has a thickness T ? that is less than approximately 50% of the strained semiconductor layer 118 thickness T3, or even less than 25% of the strained semiconductor layer W
  • an amorphization depth is preferably greater than or equal to a depth of the shallow source and drain extension implant.
  • the strained layer 118 may have a first type of strain (e.g., tensile or compressive) and recrystallized regions 1575 of the strained layer 118 may have a second type of strain (e.g., tensile or compressive).
  • the second type of strain may be substantially the same as the first type of strain, i.e., both the first and second types of strain may be tensile strain or compressive strain.
  • dielectric sidewall spacers 1580 are defined proximate the gate electrode 1530 by methods known in the art, and a deep source/drain implant of n- or p-type dopants is performed to define deep source and drain regions 1590.
  • the deep source/drain implant may be the implantation of As at a power of 30 keV and a dose of 10 15 cm "2 .
  • the same n- or p-type dopant atoms, e.g., As or B, are typically implanted, respectively, for both the deep source and drain regions 1590 and the shallow source and drain extension regions 1540, 1540'.
  • a heavier species may be used for implantation of the relatively shallow source and drain extension regions 1540, 1540', such as BF 2
  • a lighter species such as B
  • B may be used for implantation of the deep source and drain regions 1590.
  • a second PAI may be performed prior to the implantation of the deep source and drain regions 1590.
  • This second PAI before the formation of the deep source and drain regions 1590 may be performed for the same reasons as given above for the first PAI before the shallow source and drain extension region 1540, 1540' formation, i.e., reduction of implant channeling, the creation of abrupt implant profiles, and prevention of TED by blocking interstitial defects that tend to form below a peak of a dopant implant.
  • SSOI substrate 190 may be heated during implantation. The thermal energy provided in this way allows the crystalline structure of the strained layer 118 to heal itself, i.e., to recrystallize during implantation.
  • the temperature during implantation may be greater than 25 0 C, and in an embodiment may be greater than approximately 100 0 C.
  • the PAI 1545 may be replaced by a co-implant 1600 that may be performed before or after the implantation of dopants to define the shallow source and drain extension regions 1540, 1540'.
  • the co-implant 1600 is an implantation step in which lattice vacancies 1610 in the strained layer 118 are created. Interstitial defects created by the shallow source and drain extension region implant 1570 recombine with the vacancies created by the co-implant 1600 and are thereby eliminated.
  • the co-implant may introduce elements such as Si, F, O, N, or Ar into the strained layer 118.
  • the criteria for selection of an element for the co-implant 1600 are similar to the selection of an element for the PAI.
  • the co-implant preferably creates vacancies rather than interstitials.
  • the co-implant element is preferably non-doping, and is not necessarily a very heavy atom.
  • a light co-implant element, such as N, O, or F, is preferable so that interstitial lattice damage does not occur.
  • SSOI substrate 190 may be heated, e.g., to ⁇ 50 - 100 0 C, during the co-implant to help prevent amorphization.
  • a hard mask 1700 e.g., an oxide mask, such as silicon dioxide, is defined over the gate electrode 1530.
  • the hard mask 1700 may be initially formed as part of a gate stack, i.e., gate dielectric, gate electrode, and oxide hard mask layers deposited over the substrate (not shown).
  • the gate stack is patterned to define the gate 1710, with the hard mask 1700 disposed on a top surface of the gate electrode 1530.
  • Source and drain regions are defined by first defining first and second recesses 1720, 1720' by removing a first portion and a second portion of the strained layer 118, and then depositing a source/drain material into the recesses 1720, 1720'.
  • the recesses may be formed by a suitable wet or dry etch.
  • the recesses 1720, 1720' may be formed by a selective etch that removes the material of the strained layer 118 selectively with respect to the hard mask 1700 and exposed STI regions 1510.
  • a dry etch containing 40 seem CF 4 , 15 seem HeO 2 , 200 seem He, and 20 seem Cl 2 at 300 W power and a pressure of 20 - 50 mTorr is used.
  • Recesses 1720, 1720' each have a depth di of 20 - 150 nm. This depth d] is preferably deep enough for subsequently deposited source/drain material to adequately conduct carriers traversing the channel 1535.
  • source/drain material is deposited into the recesses 1720, 1720' to define source and drain regions 1725, 1725' by, e.g., selective epitaxy.
  • the source/drain material is selectively deposited only on exposed crystalline surfaces, e.g., in the recesses 1720, 1720'.
  • the source/drain material may be a conductive material such as a heavily doped semiconductor, such as Si, Ge, SiGe, SiC, or SiGeC, or a metal, such as tungsten (W).
  • the deposition step may be followed by an anneal to drive a source/drain junction 1730 with the strained layer 118 deeper than an interface 1740 (see Figure 17C) between the strained layer 118 and the deposited source/drain material, i.e., diffusion of the source/drain dopants result in a source/drain junction 1730 with the strained layer 118 that is deeper than the recesses 1720, 1720'.
  • the anneal may be carried out at 800 - 1000 0 C for 1 - 10 minutes. This anneal may not be needed in embodiments with metal source/drain regions.
  • the depths di of the recesses 1720, 1720' may be deeper than described above with reference to Figures 17A - 17C, for example 100 - 150 nm.
  • the recesses 1720, 1720' preferably do not extend all the way to the underlying dielectric layer 152, as this configuration would not leave a crystalline semiconductor template for the selective epitaxy step.
  • the junction 1730 of the source and drain regions with the strained layer 118 may extend as far as the dielectric layer 152 disposed below the recesses 1720, 1720'.
  • the source/drain junctions 1730 with the strained layer 118 may reach all the way to the buried dielectric layer 152, thereby reducing junction capacitance.
  • amorphization by PAI may be performed such that amorphization occurs only in, e.g., a drain region and not in other regions, such as source regions. Because device performance typically depends predominantly on carrier injection velocity from the source side, relaxation may be tolerated on the drain side, as long as the source side remains strained.
  • formation of transistor 1500 on SSOI substrate 190 includes the definition of STI regions 1510, a gate dielectric layer 1520, and a gate electrode 1530, as is known in the art.
  • the PAI 1545' is performed at an angle 1900 less than 90° with respect to a surface 1910 of a drain region 1920 on SSOI substrate 190 so that the incident ions impinge on the drain region 1920, but not on a source region 1930. At least a portion of the ions are blocked from entering the source region by the gate electrode 1530.
  • the shadowing effect of the gate electrode 1530 may be enhanced by forming an additional layer (not shown) on a top surface of the gate electrode 1530 to temporarily provide additional gate height and shadowing ability.
  • the additional layer may be similar (and formed similarly) to the hard mask described above. Thus, substantially fewer, or even no ions may impinge on the source side 1940 of the gate electrode 1530, such that an amorphous region is formed only on the drain side 1950 of the structure.
  • shallow source and drain extension regions 1540, 1540' may be implanted as described above with respect to Figures 15A - 15D, followed by a recrystallization anneal. Because of the angled PAI, although the drain region 1920 may be partially relaxed after amorphization, the source region 1930 remains fully strained throughout the PAI and the shallow source and drain extension region 1540, 1540' formation.
  • a structure 2000 formed in accordance with the process described above may include an NMOS transistor 2010 and a PMOS transistor 2020, with each transistor including the fully strained semiconductor material of strained layer 118 over an insulator, i.e., dielectric layer 152.
  • the strained material may retain the tensile or compressive strain inherent to the SSOI substrate 190.
  • a strain-inducing overlayer 2030 may be formed over each of the NMOS and PMOS transistors 2010, 2020, further inducing additional strain in each transistor.
  • First and second channels may be disposed in tensilely strained semiconductor material of strained layer 118, and the overlayer 2030 may be, e.g., a Si 3 N 4 layer that induces tensile strain in each type of device, thereby enhancing the performance of both devices.
  • the overlayer 2030 may be, e.g., a Si 3 N 4 layer that induces tensile strain in each type of device, thereby enhancing the performance of both devices.
  • the tensile strain-inducing overlayer 2030 works in concert with that innate strain rather than against it.
  • the desired overlayer 2030 may induce compressive strain on both devices. .
  • a structure formed in accordance with the process described above may include first and second transistors, such as NMOS and PMOS field-effect transistors 2010, 2020, with each transistor including a fully strained semiconductor bonded to an insulator, e.g., strained layer 118 over dielectric layer 152.
  • the strained material of layer 118 may have a first type of strain, e.g., tensile strain.
  • first and second transistors may be a fin-field-effect transistor (finFET).
  • Each transistor 2010, 2020 includes strain-inducing epitaxially refilled source/drain regions 1725, 1725' that induce additional strain of a second type, e.g., tensile train, in the channel 2040, 2040' of the respective transistor.
  • These epitaxially refilled source/drain regions 1725, 1725' may be formed as discussed above with reference to Figures 17A - 17C.
  • the first type of strain and the second type of strain are the same, e.g., both tensile.
  • the first type of strain is different from the second type of strain, e.g., the first type of strain is tensile and the second type of strain is compressive.
  • desired types of stress may be selectively induced into the channel.
  • a first channel may be under tensile strain, and/or the second channel may be under compressive strain.
  • the channel 2040' of the PMOS transistor 2020 is compressively strained and the channel 2040 of the NMOS transistor 2010 is tensilely strained; thus, the carrier mobilities of both devices are enhanced.
  • the NMOS transistor source/drain material has a lattice constant that is smaller than a lattice constant of the NMOS transistor channel.
  • the NMOS transistor channel 2040 is tensilely strained.
  • the lattice constant of the PMOS transistor source/drain material is larger than a lattice constant of the PMOS transistor channel, and as a result, the PMOS transistor channel 2040' is compressively strained.
  • the NMOS transistor source/drain material may include or consist essentially of SiC
  • the PMOS transistor source/drain material may include or consist essentially of SiGe
  • the channel material include or consist essentially of Si.
  • the structure 2000 includes first and second transistors, such as NMOS field-effect transistor 2010 and PMOS field- effect transistor 2020, with each transistor including a fully strained semiconductor bonded to an insulator, e.g., dielectric layer 152.
  • the strained material may be, e.g., strained layer 118 having a first type of strain, such as tensile strain.
  • one or both of the first and second transistors may be a finFET.
  • Each of the transistors 2010, 2020 includes a strain-inducing stressor that induces a second strain in the respective channels 2040, 2040' of the transistors.
  • the strain-inducing stressor for each of these transistors may be at least one of the following: STI region 1510 disposed proximate a source/drain region 1590; a gate electrode 1530 disposed over the strained layer 118; a metal-semiconductor alloy 2100, such as suicide, disposed on the source/drain regions 1590; or dielectric sidewall spacers 1580 disposed proximate the gate electrode 1530.
  • the strain-inducing stressor may be a void 2110 implanted into the source/drain regions 1590 or below the channel 2040, 2040'.
  • the void 2110 may be defined by the implantation of a gaseous species, e.g., hydrogen, oxygen, helium, or other noble gas, prior to gate electrode formation; alternatively, it may be introduced by an angled implant after gate electrode formation.
  • a gaseous species e.g., hydrogen, oxygen, helium, or other noble gas
  • both NMOS and PMOS transistors 2010, 2020 incorporate the same strain-inducing stressor that induces, e.g., tensile strain.
  • each device incorporates a different strain-inducing stressor, each of which induces the same type of strain, e.g., tensile strain.
  • each of the NMOS and PMOS devices may incorporate a compressive strain-inducing stressor.
  • strain-inducing stressors can be the same or different, as in the case of the tensile strain-inducing stressors.
  • the strain-inducing stressor may be introduced during back- end metallization steps or during die-level packaging of a chip 2200 including NMOS and
  • the strain-inducing stressor may be a package 2210 to which the chip 2200 is attached after the completion of device fabrication
  • a package 2210 can be engineered, e.g., deformed or strained, to induce strain across an entire chip along one or more directions, thereby inducing strain in channels 2040, 2040'.
  • the underlying substrate may have a reduced thickness, e.g., due to removal of material by backside grinding.
  • the strain-inducing stressor may be a metallization layer or a dielectric layer between metal wiring layers deposited and/or processed in a manner such that strain is induced in channels 2040, 2040'.
  • the STI trench may include a fill material that includes an amorphous semiconductor, e.g., amorphous silicon.
  • the fill material may be heated to a temperature above its amorphous- polycrystalline phase transition temperature by annealing or by irradiation with ultraviolet or laser energy. Depending on the method, this may include heating the fill material to a temperature higher than approximately 500 - 700 0 C. During the phase transition that takes place above its amorphous-polycrystalline phase transition temperature, the fill material contracts, W
  • the fill material has a thermal expansion coefficient greater than that of the material within which it is predominantly formed (i.e. strained layer 118) and it is deposited at elevated temperatures.
  • the fill material may be selected to have a coefficient of thermal expansion greater than that of Si (2.6 x 1(T 6 / 0 C), Ge (5.8 x 10 '6 / 0 C), or GaAs (6.86 x 1(T 6 / 0 C).
  • the coefficient of thermal expansion of the SiGe may be approximated as the weighted average of the coefficients of thermal expansion of Si and Ge.
  • the fill material may be chosen to have a coefficient of thermal expansion greater than 8 x 10 "6 / 0 C.
  • a material suitable for use as the fill material is zinc-alumina-silicate glass.
  • the fill material is not fully densified, e.g., the fill material may include low temperature oxide (LTO), medium temperature oxide (MTO), and/or silicon dioxide deposited from a tetraethylorthosilicate (TEOS) precursor.
  • LTO low temperature oxide
  • MTO medium temperature oxide
  • TEOS tetraethylorthosilicate
  • An anneal at a temperature above the deposition temperature, e.g., above 700 0 C, may cause the fill material to densify, i.e., contract, thereby inducing tensile strain in the region bounded by the trench structure, e.g., in the channel region of a subsequently fabricated device.
  • Such a densification anneal is preferably performed at a temperature sufficiently low, e.g., below 1100 - 1200 0 C, to prevent strain relief by flow of the fill material.
  • the trench structure induces compressive strain, and fill material with a coefficient of thermal expansion smaller than that of the surrounding material may be deposited at elevated temperature.
  • the fill material may be silicon dioxide.
  • the fill material may induce tensile strain as-deposited and may be densified or annealed at high temperatures, e.g., above 900 0 C. Flow of the fill material at such high temperatures may result in compressive strain being induced by the fill material after cooling.
  • compressive silicon dioxide may be deposited by PECVD.
  • a protective liner may be absent in the trench, and an oxidation step may be performed after filling the trench with the fill material. Such oxidation is accompanied by a volume expansion which may further induce compressive strain in the region bounded by the trench structure, e.g., in the channel region of a subsequently fabricated device.
  • the gate electrode 1530 of each of the NMOS and PMOS transistors 2010, 2020 may also induce strain in the respective channel 2040, 2040' if the gate electrode 1530 is composed completely or nearly completely of a metal suicide, metal germanosilicide, or metal germanocide, e.g., nickel suicide (NiSi), nickel germanosilicide (NiSiGe), or nickel germanocide (NiGe).
  • a metal suicide metal germanosilicide
  • metal germanocide e.g., nickel suicide (NiSi), nickel germanosilicide (NiSiGe), or nickel germanocide (NiGe).
  • NiSi nickel suicide
  • NiSiGe nickel germanosilicide
  • NiGe nickel germanocide
  • the reaction between the metal and the gate polycrystalline silicon, polycrystalline silicon-germanium, or polycrystalline germanium may result in a volumetric change that may induce strain in channel region 2040, 2040' after processing.
  • strain in gate electrode 1530 may be induced by deposition of an overlayer, e.g., an oxide, and annealing prior to complete or incomplete silicidation of the gate.
  • Gate electrode 1530 may include or consist essentially of a semiconductor material that has been amorphized, e.g., by an ion implantation step, and may undergo an amorphous-crystalline phase transition (and accompanying volumetric change) during a subsequent anneal. The presence of an overlayer during such an anneal may result in a strain being induced in channel 2040, 2040', even after the overlayer is removed and the gate is suicided.
  • strain in NMOS and PMOS channels 2040, 2040' may also be induced predominantly by a suicided region of source/drain region 1590 in the respective NMOS and PMOS transistor 2010, 2020.
  • Volumetric changes during the reaction of the suicide metal with the semiconductor material in source/ drain region 1590 may cause strain to be induced in channels 2040, 2040'.
  • Such metals may include titanium, nickel, cobalt, platinum or other suitable metals.
  • source/drain region 1590 may not be etched and refilled with alternative semiconductor materials.
  • the dielectric sidewall spacers include or consist essentially of silicon nitride.
  • the composition of these layers may be selected as described above with respect to the overlayers to induce a desired level of strain.
  • the sidewall spacers include or consist essentially of silicon dioxide.
  • Deposited TEOS oxide may exert tensile strain and deposited high-density plasma (HDP) oxide may exert corapressive strain. Both types may be used together, e.g., an oxide/nitride stacked spacer, with each layer exerting the same type of strain.
  • Selective PAI-induced relaxation may be used to enhance compatibility with other device stressors.
  • the performance of a PAI step may be omitted, or one of the methods described above may be used to prevent relaxation of one type of device.
  • a PAI may be formed selectively on a PMOS device so that inherent strain in the PMOS SSOI material relaxes after a recrystallization anneal.
  • the NMOS device on the same substrate may not be subjected to a PAI, so that the inherent SSOI tensile or compressive strain is retained in the NMOS regions.
  • the selectively-relaxed SSOI substrate is highly compatible with process-inducing strain sequences that apply different types of strain to different device types.
  • a photoresist mask 2300 is defined over the NMOS transistor features.
  • An aggressive PAI 1545 is performed on the PMOS transistor 2020 region, such that the regions 1550 of the strained layer 118 in which the PMOS source/drain will be formed amorphize to a large degree.
  • the PAI parameters 1545 may be a Ge implant at a dose of 5 x 10 14 - 2 x 10 15 cm "2 , an energy of 10 - 50 keV, with the source/drain regions being amorphized to a depth of 30 - 80 nm.
  • an implantation step is performed to introduce p-type dopants 1570, thereby defining the PMOS shallow source and drain extension regions 1540, 1540'.
  • the NMOS transistor 2010 features are shielded by the photoresist mask 2300 during the PAI and PMOS shallow source and drain extension region 1540, 1540' formation.
  • Regions 2310 of the strained layer 118 in which the NMOS source and drain regions will be formed are not amorphized because of the shielding effect of the photoresist mask 2300.
  • the photoresist mask 2300 over the NMOS region is removed and a recrystallization anneal is performed. After the recrystallization anneal, a region 2310 of the strained semiconductor layer 118 in which the NMOS device is to be formed remains strained, but at least the amorphized region 1550 of the strained semiconductor layer 118 in which the PMOS source/drain and channel will be disposed relaxes significantly. In an embodiment, the channel of the PMOS transistor may also relax significantly upon recrystallization of region 1550.
  • This sequence for the definition of the PMOS transistor 2020 is repeated for the definition of the NMOS transistor 2010.
  • a photoresist mask (not shown) is formed over the PMOS transistor region.
  • a PAI may be performed over the NMOS transistor region, but with less aggressive parameters than those used for the PMOS PAL
  • the PAI performed on NMOS transistor region may utilize Ge at a dose of less than 5 x 10 14 cm "2 and an energy of 10 - 20 keV.
  • no PAI is performed over the NMOS transistor region.
  • a dopant implant is performed to define the NMOS shallow source and drain extension regions. After the formation of the NMOS shallow source and drain extension regions, a recrystallization anneal is performed.
  • one or more of the other techniques described above may be used to maintain the strain in the NMOS region.
  • source/drain regions may be defined by the definition of recesses and selective growth of source/drain material.
  • An angled and/or heated PAI may be performed.
  • strain in the NMOS region may be maintained by applying heat to the substrate during the shallow source and drain extension region implant.
  • sidewall spacers 1580, and NMOS and PMOS shallow and deep source and drain regions 1540, 1540', 1590, 1590' are defined, as described above.
  • the NMOS channel 2040 is strained, e.g., tensilely strained, and the PMOS channel 2040' is at least partially relaxed. This structure is particularly compatible with strain-inducing processes that induce tensile NMOS stain and compressive PMOS strain.
  • a first overlayer 2030 is disposed over the NMOS transistor 2010.
  • the NMOS transistor 2010 includes a strained SSOI channel 2040 that is, e.g., tensilely strained, and the first overlayer 2030 contributes additional tensile strain.
  • the first overlayer includes silicon nitride.
  • a second overlayer 2030' is disposed over the PMOS transistor 2020.
  • the PMOS transistor 2020 includes an at least partially relaxed channel 2040', and the second overlayer 2030' induces compressive strain.
  • the PMOS channel 2040' is initially relaxed, rather than fully tensilely strained, so that the final strain state is compressive.
  • the overlayer 2030' does not have to reverse much strain inherent to the strained semiconductor layer, but substantially alone determines the final strain state of the channel 2040'.
  • the second overlayer 2030' includes silicon nitride.
  • First and second overlayers 2030, 2030' can include or consist essentially of different dielectric materials, such as silicon oxynitride.
  • the strain of the overlayers may be selected as described below. [0117] The strain of silicon nitride films grown by LPCVD at temperatures greater than approximately 700 0 C may be selected by varying the silicon content of the nitride film.
  • LPCVD stoichiometric silicon nitride films i.e., Si 3 N 4
  • silicon-rich nitride films e.g., with a silicon volume fraction greater than 0.1 - 0.15, or with a Si/N atomic ratio greater than 0.75
  • the silicon content of a nitride film formed by LPCVD may be varied by changes in the ratio of silicon and nitrogen precursors utilized in the growth process.
  • a nitride growth process performed at 850 0 C and a pressure of 200 milliTorr (mTorr) utilizing dichlorosilane (SiCl 2 H 2 ) as a silicon precursor and ammonia (NH 3 ) as a nitrogen precursor will form a silicon-rich nitride when the ratio of dichlorosilane flow to the total gas flow is greater than approximately 0.85.
  • the relative amount of dichlorosilane may need to be increased to form silicon-rich nitride films.
  • Compressive silicon nitride films may have a refractive index greater than approximately 2.4, and tensile silicon nitride films may have a refractive index smaller than approximately 2.4. (See, e.g., M. Sekimoto, et al., J. Vac. ScI Technol, 21 (4) p. 1017 (1982), incorporated herein by reference.)
  • silicon nitride films for various strain levels may be formed by PECVD at deposition temperatures less than approximately 700 0 C. Variations in precursor gas ratio, RF power, dilution gas, and plasma excitation frequency may lead to strain variations in the final film. For example, for a PECVD process performed at 220 0 C, 200 Pascals pressure, 100 watts RF power, and helium dilution, a compressive silicon nitride film may be deposited when the ratio of silane flow to total gas flow (silane, ammonia, and nitrogen) is smaller than approximately 0.03. When this ratio is larger than approximately 0.03, a tensilely strained silicon nitride film may be deposited. (See, e.g., M. J. Loboda, et al., J. Mater. Res., 11 (2) p. 391 (1996), incorporated herein by reference.)
  • silicon nitride films of varying strain levels may be produced by high density plasma CVD (HDPCVD) in a process utilizing an inductively coupled plasma (ICP) source at temperatures less than 500 0 C with precursors such as silane, ammonia, and nitrogen.
  • the plasma used in this process may utilize noble gases such as argon or helium, which may also act as dilution gases in this process.
  • the chuck power levels may be varied to tailor strain levels in silicon nitride films.
  • a process at 150 0 C and 10 mTorr utilizing silane, ammonia, and helium gases (total gas flow of 40 standard cubic centimeters per minute (seem)) and an ICP power of 800 watts may produce compressively strained silicon nitride films for RF chuck power levels less than approximately 40 watts and tensilely strained silicon nitride films for RF chuck power levels greater than approximately 40 watts.
  • relaxed PMOS devices may incorporate strain-inducing stressors such as recessed source/drain stressors, STI strain, suicide strain, gate strain, package strain, or a combination thereof.
  • strain-inducing stressors such as recessed source/drain stressors, STI strain, suicide strain, gate strain, package strain, or a combination thereof.
  • both NMOS and PMOS device types are fabricated separately and device performance may be better than that achieved by separate fabrication on a bulk SOI wafer or on a non-selectively relaxed SSOI wafer that includes the global incorporation of additional strain.
  • an SSOI strained layer 118 is initially tensilely strained.
  • An NMOS transistor 2010 includes a strained SSOI channel 2040 that is, e.g., tensilely strained, and strain-inducing epitaxial refilled source and drain regions 1725, 1725' that induce the same type of strain as is present in the NMOS channel 2040, e.g., tensile strain.
  • the refilled source and drain regions 1725, 1725' may be defined as discussed above with reference to Figures 17A - 17C.
  • a PMOS transistor 2020 may be defined, including an initially relaxed channel 2040' and strain-inducing epitaxial refilled source and drain regions 1725, 1725'.
  • the strain induced in the PMOS channel 2040' by the epitaxial refilled source and drain regions 1725, 1725' may be of a type opposite to the strain induced by the NMOS source and drain regions 1725, 1725'.
  • the PMOS source and drain regions 1725, 1725' may induce compressive strain, such that the PMOS channel 2040' is compressively strained.
  • the SSOI channels of both the NMOS and PMOS devices 2010, 2020 may include or consist essentially of silicon
  • the NMOS source/drain material may be SiC (generally, a material with a smaller lattice constant than the channel material)
  • the PMOS source/drain material may include or consist essentially of SiGe or Ge (generally, a material with a larger lattice constant than the channel material).
  • the NMOS transistor 2010 may include a compressively strained channel 2040 and/or a compressive strain-inducing stressor
  • the PMOS transistor 2020 may include a tensilely strained channel 2040 and/or a tensile strain-inducing stressor.
  • an NMOS transistor 2010 includes a strained SSOI channel 2040 that is, e.g., tensilely strained, as well as at least one additional strain-inducing stressor that induces additional strain of the same type as the strained SSOI channel, e.g., tensile strain.
  • a PMOS transistor 2020 includes an initially relaxed channel 2040' and a strain-inducing stressor that induces strain of the opposite type induced by the strain-inducing stressor in NMOS transistor 2010, e.g., the strain-inducing stressor induces compressive strain.
  • an NMOS transistor 2010 includes an initially relaxed channel 2040 and a strain-inducing stressor induces tensile strain.
  • a PMOS transistor 2020 includes a strained SSOI channel 2040' that is, e.g., compressively strained, and at least one additional strain-inducing stressor induces additional strain of the same type as the strained SSOI channel, e.g., compressive strain.
  • the NMOS and PMOS strain-inducing stressors may be, for example, STI regions 1510, gate electrodes 1530, metal-semiconductor alloy 2100, e.g., suicide, disposed on the gate electrode 1530 and/or the source and drain regions 1590, 1590', sidewall spacers 1580, voids 2110 implanted into the source and drain regions or below the channels 2040, 2040', or the package 2210 to which the chip 2200 including NMOS and PMOS transistors 2010, 2020 is attached.
  • metal-semiconductor alloy 2100 e.g., suicide
  • the NMOS transistor 2010 may include a compressively strained channel 2040 and/or a compressive strain-inducing stressor
  • the PMOS transistor 2020 may include a tensilely strained channel 2040' and/or a tensile strain-inducing stressor.
  • Such an embodiment may be preferable for channel materials other than Si that may have different piezoresistance coefficients.
  • a planar transistor 2500 e.g., an NMOS transistor or PMOS transistor as described above and a finFET 2510 are both formed on SSOI substrate 190.
  • strain in the strained layer 118 is selectively relaxed in a region where the finFET is to be defined.
  • a planar transistor is defined in another, unrelaxed region. Because the finFET will have carrier conduction (channels) that are vertical (on the sides of the fin) and perhaps horizontal (on the top of the fin), it may be preferable to make the finFET from an isotropic material (e.g., relaxed in both directions) rather than one that is strained in one direction.
  • FinFETs typically have two gates (one on either side of the channel, where the channel is here oriented vertically), allowing much greater control of channel charge than in a single gate device. This configuration may also result in higher drive current and lower stand-by leakage current Unlike in a traditional planar FET, this channel region is raised above the wafer surface: the channel (or portions of the channel) falls in a plane perpendicular (or at least non- parallel) to the wafer surface. There may in addition be gates below the channel region, such as in a wrap-around gate FET.
  • the finFET 2510 is defined as follows. A portion of the substrate is relaxed by, e.g., a PAI as described above. The relaxed semiconductor layer 118 portion may be patterned to define a plurality of fins 2520. In particular, fins 2520 may be defined by the formation of a photolithographic mask (not shown) over the substrate 190, followed by anisotropic reactive ion etching (RIE) of the substrate 130. The photolithographic mask is removed after the RIE step. A dielectric layer 2530 is conformally deposited over and between the fins 2520, to define a gate dielectric. Dielectric layer 2530 is a gate dielectric layer and includes a dielectric material that may include a first metal nitride and/or a metal oxide.
  • electrode layer 2540 is subsequently formed to define a gate electrode.
  • the electrode layer 2540 is conformally deposited over dielectric layer 2530.
  • Electrode layer 2540 includes or consists essentially of at least one of a metal or a second metal nitride.
  • a photolithographic mask is formed over electrode layer 2540. Portions of the electrode layer 2540 are selectively removed by, e.g., RTF, to define a gate crossing over the fins 2520, and terminating in a gate contact area. Portions of the dielectric layer 2530 are exposed (or even removed) by the RIE of electrode layer 2540.
  • the formation .of a finFET may completed by methods known to those of skill in the art. FinFET 2510 may also include a tensile or compressive strain-inducing stressor, as described above with respect to NMOS transistor 2010 and PMOS transistor 2020.
  • an NMOS or PMOS transistor may be defined on a strained portion of strained layer 118, as described above.
  • the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The foregoing embodiments are therefore to be considered in all respects illustrative rather than limiting on the invention described herein. Scope of the invention is thus indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

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Abstract

Selon cette invention, les bienfaits de semi-conducteurs contraints sont combinés à des approches silicium sur isolant de fabrication de substrats et de dispositifs. La contrainte dans les semi-conducteurs contraints est régulée afin que les performances des dispositifs soient améliorées.
PCT/US2006/035814 2005-09-15 2006-09-14 Regulation de la contrainte dans des couches de dispositifs par relachement selectif et prevention du relachement WO2007035398A2 (fr)

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US11/227,529 US7335545B2 (en) 2002-06-07 2005-09-15 Control of strain in device layers by prevention of relaxation
US11/227,472 US7307273B2 (en) 2002-06-07 2005-09-15 Control of strain in device layers by selective relaxation
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007030056B3 (de) * 2007-06-29 2009-01-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Blockieren einer Voramorphisierung einer Gateelektrode eines Transistors
WO2017171844A1 (fr) 2016-04-01 2017-10-05 Intel Corporation Transistor à performances thermiques améliorées

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6624037B2 (en) * 2001-08-01 2003-09-23 Advanced Micro Devices, Inc. XE preamorphizing implantation
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
DE102004031710B4 (de) * 2004-06-30 2007-12-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen unterschiedlich verformter Halbleitergebiete und Transistorpaar in unterschiedlich verformten Halbleitergebieten

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007030056B3 (de) * 2007-06-29 2009-01-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Blockieren einer Voramorphisierung einer Gateelektrode eines Transistors
US7879667B2 (en) 2007-06-29 2011-02-01 Globalfoundries Inc. Blocking pre-amorphization of a gate electrode of a transistor
WO2017171844A1 (fr) 2016-04-01 2017-10-05 Intel Corporation Transistor à performances thermiques améliorées
EP3440706B1 (fr) * 2016-04-01 2023-11-01 INTEL Corporation Transistor à performances thermiques améliorées

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