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WO2008016419A3 - Réseau de mémoires polyvalent et procédé d'utilisation correspondant - Google Patents

Réseau de mémoires polyvalent et procédé d'utilisation correspondant Download PDF

Info

Publication number
WO2008016419A3
WO2008016419A3 PCT/US2007/013769 US2007013769W WO2008016419A3 WO 2008016419 A3 WO2008016419 A3 WO 2008016419A3 US 2007013769 W US2007013769 W US 2007013769W WO 2008016419 A3 WO2008016419 A3 WO 2008016419A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cells
memory array
mixed
therewith
memory
Prior art date
Application number
PCT/US2007/013769
Other languages
English (en)
Other versions
WO2008016419A2 (fr
Inventor
Roy E Scheuerlein
Original Assignee
Sandisk 3D Llc
Roy E Scheuerlein
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/496,983 external-priority patent/US7450414B2/en
Priority claimed from US11/496,874 external-priority patent/US20080023790A1/en
Application filed by Sandisk 3D Llc, Roy E Scheuerlein filed Critical Sandisk 3D Llc
Publication of WO2008016419A2 publication Critical patent/WO2008016419A2/fr
Publication of WO2008016419A3 publication Critical patent/WO2008016419A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5641—Multilevel memory having cells with different number of storage levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/33—Material including silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

La présente invention concerne un réseau de mémoires polyvalent et un procédé d'utilisation correspondant. Dans un mode de réalisation préféré, on utilise un réseau de mémoires comprenant un premier ensemble de cellules mémoire fonctionnant comme des cellules mémoire programmables une seule fois et un deuxième ensemble de cellules mémoire fonctionnant comme des cellules mémoire réinscriptibles. Dans un autre mode de réalisation préféré, on utilise un réseau de mémoires comprenant un premier ensemble de cellules mémoire fonctionnant comme des cellules mémoire qui sont programmées avec une polarisation directe et un deuxième ensemble de cellules mémoire fonctionnant comme des cellules mémoire qui sont programmées avec une polarisation inverse.
PCT/US2007/013769 2006-07-31 2007-06-12 Réseau de mémoires polyvalent et procédé d'utilisation correspondant WO2008016419A2 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/496,874 2006-07-31
US11/496,983 US7450414B2 (en) 2006-07-31 2006-07-31 Method for using a mixed-use memory array
US11/496,983 2006-07-31
US11/496,874 US20080023790A1 (en) 2006-07-31 2006-07-31 Mixed-use memory array

Publications (2)

Publication Number Publication Date
WO2008016419A2 WO2008016419A2 (fr) 2008-02-07
WO2008016419A3 true WO2008016419A3 (fr) 2008-05-22

Family

ID=38997614

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/013769 WO2008016419A2 (fr) 2006-07-31 2007-06-12 Réseau de mémoires polyvalent et procédé d'utilisation correspondant

Country Status (2)

Country Link
TW (1) TWI455130B (fr)
WO (1) WO2008016419A2 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788113A1 (fr) * 1996-01-31 1997-08-06 STMicroelectronics S.r.l. Circuits de mémoire multi-niveau et méthodes de lecture et d'écriture correspondants
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
WO2005066969A1 (fr) * 2003-12-26 2005-07-21 Matsushita Electric Industrial Co., Ltd. Dispositif memoire, circuit memoire et circuit integre semi-conducteur a resistance variable

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034882A (en) * 1998-11-16 2000-03-07 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
US7003619B1 (en) * 2001-04-09 2006-02-21 Matrix Semiconductor, Inc. Memory device and method for storing and reading a file system structure in a write-once memory array
US6768661B2 (en) * 2002-06-27 2004-07-27 Matrix Semiconductor, Inc. Multiple-mode memory and method for forming same
JP3875153B2 (ja) * 2002-07-04 2007-01-31 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置およびその書き換え禁止制御方法
EP1450261A1 (fr) * 2003-02-18 2004-08-25 STMicroelectronics S.r.l. Mémoire semiconductrice avec mécanisme de protection d'accès
JP4282529B2 (ja) * 2004-04-07 2009-06-24 株式会社東芝 半導体集積回路装置及びそのプログラム方法
US7398348B2 (en) * 2004-08-24 2008-07-08 Sandisk 3D Llc Method and apparatus for using a one-time or few-time programmable memory with a host device designed for erasable/rewritable memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788113A1 (fr) * 1996-01-31 1997-08-06 STMicroelectronics S.r.l. Circuits de mémoire multi-niveau et méthodes de lecture et d'écriture correspondants
US6483734B1 (en) * 2001-11-26 2002-11-19 Hewlett Packard Company Memory device having memory cells capable of four states
WO2005066969A1 (fr) * 2003-12-26 2005-07-21 Matsushita Electric Industrial Co., Ltd. Dispositif memoire, circuit memoire et circuit integre semi-conducteur a resistance variable

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BANDYOPADHYAY A ET AL: "Vertical p-i-n Polysilicon Diode With Antifuse for Stackable Field-Programmable ROM", IEEE ELECTRON DEVICE LETTERS, IEEE SERVICE CENTER, NEW YORK, NY, US, vol. 25, no. 5, May 2004 (2004-05-01), pages 271 - 273, XP011112176, ISSN: 0741-3106 *

Also Published As

Publication number Publication date
TWI455130B (zh) 2014-10-01
WO2008016419A2 (fr) 2008-02-07
TW200811865A (en) 2008-03-01

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