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WO2008120335A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2008120335A1
WO2008120335A1 PCT/JP2007/056716 JP2007056716W WO2008120335A1 WO 2008120335 A1 WO2008120335 A1 WO 2008120335A1 JP 2007056716 W JP2007056716 W JP 2007056716W WO 2008120335 A1 WO2008120335 A1 WO 2008120335A1
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WO
WIPO (PCT)
Prior art keywords
gate electrode
side wall
semiconductor device
strain
channel region
Prior art date
Application number
PCT/JP2007/056716
Other languages
English (en)
French (fr)
Inventor
Toshihiko Miyashita
Keiji Ikeda
Original Assignee
Fujitsu Microelectronics Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Microelectronics Limited filed Critical Fujitsu Microelectronics Limited
Priority to CN200780052401XA priority Critical patent/CN101641770B/zh
Priority to JP2009507327A priority patent/JP5206668B2/ja
Priority to PCT/JP2007/056716 priority patent/WO2008120335A1/ja
Publication of WO2008120335A1 publication Critical patent/WO2008120335A1/ja
Priority to US12/561,841 priority patent/US20100025744A1/en
Priority to US13/440,625 priority patent/US20120190162A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
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    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

　半導体装置は、半導体基板上のゲート電極（１３）と、前記ゲート電極下方の半導体基板領域に設けられるチャネル領域（ＣＨ）と、前記チャネル領域に応力を与える歪生成層（２１）と、を有し、前記チャネル領域のソース端（Ａ）に印加される歪みの絶対値は、ドレイン端に印加される歪みの絶対値よりも大きい。良好な構成例では、ゲート電極の側壁に形成されるサイドウォールスペーサ（１７）をさらに有し、前記ゲート電極のソース側に形成されるサイドウウォール幅（Ｗ１）が、前記ゲート電極のドレイン側に形成されるサイドウォール幅（Ｗ２）よりも小さい。
PCT/JP2007/056716 2007-03-28 2007-03-28 半導体装置およびその製造方法 WO2008120335A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN200780052401XA CN101641770B (zh) 2007-03-28 2007-03-28 半导体器件及其制造方法
JP2009507327A JP5206668B2 (ja) 2007-03-28 2007-03-28 半導体装置の製造方法
PCT/JP2007/056716 WO2008120335A1 (ja) 2007-03-28 2007-03-28 半導体装置およびその製造方法
US12/561,841 US20100025744A1 (en) 2007-03-28 2009-09-17 Semiconductor device and method of manufacturing same
US13/440,625 US20120190162A1 (en) 2007-03-28 2012-04-05 Semiconductor device and method of manufacturing same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/056716 WO2008120335A1 (ja) 2007-03-28 2007-03-28 半導体装置およびその製造方法

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US12/561,841 Continuation US20100025744A1 (en) 2007-03-28 2009-09-17 Semiconductor device and method of manufacturing same

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WO2008120335A1 true WO2008120335A1 (ja) 2008-10-09

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JP (1) JP5206668B2 (ja)
CN (1) CN101641770B (ja)
WO (1) WO2008120335A1 (ja)

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JP2010103495A (ja) * 2008-09-29 2010-05-06 Adeka Corp 半導体デバイス、その製造装置及び製造方法
JP2010118500A (ja) * 2008-11-13 2010-05-27 Toshiba Corp 半導体装置及びその製造方法
JP2011035393A (ja) * 2009-07-29 2011-02-17 Internatl Business Mach Corp <Ibm> 埋め込み拡張領域を有するｓｏｉトランジスタ、及びその形成方法
JP2011054972A (ja) * 2009-09-03 2011-03-17 Internatl Business Mach Corp <Ibm> 集積回路構造及びその製造方法
EP2115778A4 (en) * 2007-02-28 2011-11-02 Freescale Semiconductor Inc SOURCE DRAIN STRESSOR AND METHOD THEREFOR
JP2013229597A (ja) * 2012-04-25 2013-11-07 Samsung Electronics Co Ltd 応力近接効果を有する集積回路
KR20230018302A (ko) * 2021-07-29 2023-02-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 감소된 도펀트 손실 및 증가된 치수를 갖는 콘택트 형성

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CN104835737B (zh) * 2014-02-07 2018-09-04 无锡华润上华科技有限公司 半导体器件及其制作方法
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US11205578B2 (en) * 2017-10-18 2021-12-21 Texas Instruments Incorporated Dopant anneal with stabilization step for IC with matched devices
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CN110233107A (zh) * 2018-03-05 2019-09-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
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JPH07235675A (ja) * 1994-02-24 1995-09-05 Nec Corp 半導体装置の製造方法
JP2003086708A (ja) * 2000-12-08 2003-03-20 Hitachi Ltd 半導体装置及びその製造方法
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2115778A4 (en) * 2007-02-28 2011-11-02 Freescale Semiconductor Inc SOURCE DRAIN STRESSOR AND METHOD THEREFOR
JP2010103495A (ja) * 2008-09-29 2010-05-06 Adeka Corp 半導体デバイス、その製造装置及び製造方法
JP2010118500A (ja) * 2008-11-13 2010-05-27 Toshiba Corp 半導体装置及びその製造方法
JP2011035393A (ja) * 2009-07-29 2011-02-17 Internatl Business Mach Corp <Ibm> 埋め込み拡張領域を有するｓｏｉトランジスタ、及びその形成方法
JP2011054972A (ja) * 2009-09-03 2011-03-17 Internatl Business Mach Corp <Ibm> 集積回路構造及びその製造方法
JP2013229597A (ja) * 2012-04-25 2013-11-07 Samsung Electronics Co Ltd 応力近接効果を有する集積回路
KR20230018302A (ko) * 2021-07-29 2023-02-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 감소된 도펀트 손실 및 증가된 치수를 갖는 콘택트 형성
KR102785525B1 (ko) 2021-07-29 2025-03-21 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 감소된 도펀트 손실 및 증가된 치수를 갖는 콘택트 형성

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US20120190162A1 (en) 2012-07-26
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JP5206668B2 (ja) 2013-06-12
JPWO2008120335A1 (ja) 2010-07-15

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