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WO2008136813A2 - Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement - Google Patents

Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement Download PDF

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Publication number
WO2008136813A2
WO2008136813A2 PCT/US2007/024544 US2007024544W WO2008136813A2 WO 2008136813 A2 WO2008136813 A2 WO 2008136813A2 US 2007024544 W US2007024544 W US 2007024544W WO 2008136813 A2 WO2008136813 A2 WO 2008136813A2
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WO
WIPO (PCT)
Prior art keywords
floating
cell
terminal
volts
data
Prior art date
Application number
PCT/US2007/024544
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English (en)
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WO2008136813A3 (fr
Inventor
Yuniarto Widjaja
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Yuniarto Widjaja
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Application filed by Yuniarto Widjaja filed Critical Yuniarto Widjaja
Publication of WO2008136813A2 publication Critical patent/WO2008136813A2/fr
Publication of WO2008136813A3 publication Critical patent/WO2008136813A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Definitions

  • the present inventions relates to semiconductor memory technology. More specifically, the present invention relates to semiconductor memory having both volatile and non-volatile semiconductor memory features.
  • Memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and nonvolatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Non-volatile memory devices such as flash erasable programmable read only memory (Flash EPROM) device, retain stored data even in the absence of power supplied thereto.
  • Flash EPROM flash erasable programmable read only memory
  • non-volatile memory devices typically operate more slowly than volatile memory devices. Accordingly, it would be desirable to provide a universal type memory device that includes the advantages of both volatile and non-volatile memory devices, i.e., fast operation on par with volatile memories, while having the ability to retain stored data when power is discontinued to the memory device. It would further be desirable to provide such a universal type memory device having a size that is not prohibitively larger than comparable volatile or non-volatile devices.
  • the present invention provides semiconductor memory having both volatile and non-volatile modes and methods of operation of the same.
  • a semiconductor memory cell including: a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second Atty.
  • ZENO-OOl WO location the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; and a control gate positioned above the floating gate or trapping layer and a second insulating layer between the floating gate or trapping layer and the control gate.
  • the surface comprises a top surface, the cell further comprising a buried layer at a bottom portion of the substrate, the buried layer having the second conductivity type.
  • the first conductivity type is "p" type and the second conductivity type is "n" type.
  • insulating layers bound the side surfaces of the substrate.
  • the floating body is configured so that data can be written thereto by hot hole injection.
  • the floating gate or trapping layer stores a charge in non-volatile memory that is complementary to a charge that was stored in the floating body at a time when the power is interrupted.
  • a state of the floating gate or trapping layer is set to a positive state after the data is transferred from the floating gate or trapping layer to the floating body.
  • the semiconductor memory cell functions as Atty. Docket: ZENO-OOl WO a binary cell.
  • the semiconductor memory cell functions as a multi-level cell.
  • a method of operating a memory cell having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory including: storing data to the floating body while power is applied to the memory cell; transferring the data stored in the floating body to the floating gate or trapping layer when power to the cell is interrupted; and storing the data in the floating gate or trapping layer as non-volatile memory.
  • the data stored in the floating body is stored as volatile memory.
  • the method further includes: transferring the data stored in the floating gate or trapping layer to the floating body when power is restored to the cell; and storing the data in the floating body as volatile memory.
  • the data transferred is stored in the floating gate or trapping layer with a charge that is complementary to a charge of the floating body when storing the data.
  • the transferring is a non-algorithmic process.
  • the transferring is a parallel, non-algorithmic process.
  • the method further includes restoring the floating gate or trapping layer to a predetermined charge state.
  • the method further includes writing a predetermined state to the floating body prior to the transferring the data stored in the floating gate or trapping layer to the floating body.
  • the predetermined state is state "0".
  • a method of operating a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory is provided, including: storing data to the floating bodies as volatile memory while power is applied to the device; transferring the Atty. Docket: ZENO-OOl WO data stored in the floating bodies, by a parallel, non-algorithmic process, to the floating gates or trapping layers corresponding to the floating bodies, when power to the device is interrupted; and storing the data in the floating gates or trapping layers as non-volatile memory.
  • the method further includes: transferring the data stored in the floating gates or trapping layers, by a parallel, non-algorithmic restore process, to the floating bodies corresponding to the floating gates or trapping layers, when power is restored to the cell; and storing the data in the floating bodies as volatile memory.
  • the method further includes initializing the floating gates or trapping layers, to each have the same predetermined state prior to the transferring.
  • the predetermined state comprises a positive charge.
  • the data transferred is stored in the floating gates or trapping layers with charges that are complementary to charges of the floating bodies when storing the data.
  • the method further includes restoring the floating gates or trapping layers to a predetermined charge state after the restore process.
  • the method further includes writing a predetermined state to the floating bodies prior to the transferring the data stored in the floating gates or trapping layers to the floating bodies.
  • a semiconductor storage device comprising a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory, and a floating gate or trapping layer for storing data as non-volatile memory is provided, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.
  • data is transferred from the volatile memory to the non-volatile memory by a parallel, non-algorithmic mechanism.
  • the device is configured to transfer data stored in non-volatile memory to store the data in the volatile memory when Atty. Docket: ZENO-OOl WO power is restored to the device.
  • the data is transferred from the non-volatile memory to the volatile memory by a parallel, non- algorithmic mechanism.
  • a semiconductor memory cell includes a fin structure extending from a substrate.
  • the fin structure includes a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate.
  • the substrate includes a substrate insulating layer that insulates the floating substrate region from a portion of the substrate below the substrate insulating layer.
  • the substrate comprises a silicon-on-insulator
  • the substrate insulating layer comprises a buried oxide insulating layer.
  • the fin structure extends substantially perpendicularly from a plane of the substrate, forming a three-dimensional memory cell.
  • control gate is capacitively coupled to the floating gates or trapping layers and insulated from the floating gates or trapping layers by a dielectric layer.
  • the first conductivity type is "p" type and the second conductivity type is "n" type.
  • the floating substrate region is configured so that data can be written thereto by hot hole injection. Atty. Docket: ZENO-OOl WO
  • the floating gates or trapping layers store a charge in non-volatile memory that is complementary to a charge that was stored in the floating substrate region at a time when the power is interrupted.
  • a state of the floating gates or trapping layers is set to a predetermined state after the data is transferred from the floating gates or trapping layers to the floating substrate region.
  • the semiconductor memory cell functions as a binary cell.
  • the semiconductor memory cell functions as a multi-level cell.
  • a memory string includes a plurality of semiconductor memory cells connected in series, wherein each semiconductor memory cell includes: a floating substrate region having a first conductivity type; first and second regions each having a second conductivity type and interfacing with the floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; a control gate positioned adjacent the floating gate or trapping layer; and a second insulating layer between the floating gate or trapping layer and the control gate.
  • the semiconductor memory cells are substantially planar. Atty. Docket: ZENO-OOl WO
  • the semiconductor memory cells comprise three-dimensional cells, each having a fin extending from a substrate.
  • a string selection transistor is connected to one end of the plurality of semiconductor memory cells connected in series, and a ground selection transistor is connected to an opposite end the plurality of semiconductor memory cells connected in series.
  • a memory cell device includes a plurality of memory strings assembled to form a grid of semiconductor memory cells, wherein each memory string comprising a plurality of semiconductor memory cells connected in series, each semiconductor memory cell comprising: a floating substrate region having a first conductivity type; first and second regions each having a second conductivity type and interfacing with the floating substrate region, such that at least a portion of the floating substrate region is located between the first and second regions and functions to store data in volatile memory; a floating gate or trapping layer positioned in between the first and second regions, adjacent a surface of the floating substrate region and insulated from the floating substrate region by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell; a control gate positioned adjacent the floating gate or trapping layer; and a second insulating layer between the floating gate or trapping layer and the control gate.
  • the memory strings form columns of the grid.
  • the columns are insulated from one another by insulating members placed between the columns.
  • FIG. l is a flowchart illustrating operation of a non-volatile memory device according to the present invention. Atty. Docket: ZENO-OOl WO
  • FIG. 2 schematically illustrates an embodiment of a memory cell according to the present invention.
  • Figs. 3A-3B illustrate alternative write state "1" operations that can be carried out on a memory cell according to the present invention.
  • Fig. 4 illustrates a write state "0" operation that can be carried out on a memory cell according to the present invention.
  • Fig. 5 illustrates a read operation that can be carried out on a memory cell according to the present invention.
  • Figs. 6A and 6B illustrate shadowing operations according to the present invention.
  • Figs. 7A and 7B illustrate restore operations according to the present invention.
  • FIG. 8A-8D illustrate another embodiment of operation of a memory cell to perform volatile to non-volatile shadowing according to the present invention.
  • Fig. 8E illustrates the operation of an NPN bipolar device.
  • Figs. 9A-9B illustrate another embodiment of operation of a memory cell to perform a restore process from non -volatile to volatile memory according to the present invention.
  • Fig. 10 illustrates resetting the floating gate(s)/trapping layer(s) to a predetermined state.
  • Figs. 1 IA illustrates the states of a binary cell, relative to threshold voltage.
  • Fig. HB illustrates the states of a multi-level cell, relative to threshold voltage.
  • Fig. 12 illustrates a fin-type semiconductor memory cell device according to an embodiment of the present invention.
  • Fig. 13 is a schematic illustration of a top view of the cell of Fig. 12.
  • Figs. 14A and 14B are referenced to illustrate write "1" operations on the device of Fig. 12.
  • Fig. 15 is referenced to illustrate a write "0" operation on the device of Fig.
  • Fig. 16 is referenced to illustrate a read operation on the device of Fig. 12.
  • Figs. 17A and 17B illustrate a shadowing operation on the device of Fig. 12.
  • Fig. 18 is referenced to illustrate a restore operation on the device of Fig. 12. Atty. Docket: ZENO-OOl WO
  • Fig. 19 is referenced to illustrate a reset operation on the device of Fig. 12.
  • Fig. 20 is a cross-sectional schematic illustration of a memory string according to an embodiment of the present invention.
  • Fig. 21 illustrates a top schematic view of the string of Fig. 20.
  • Figs. 22A and 22B illustrate alternative write state "1" operations that can be carried out on the string of Fig. 20.
  • Fig. 23 illustrates a write state "0" operation on the string of Fig. 20.
  • Fig. 24 illustrates a read operation on the string of Fig. 20.
  • Figs. 25A-25B illustrate a shadowing operation on the string of Fig. 20.
  • Fig. 26 illustrates a restore operation on the string of Fig. 20.
  • Fig. 27 illustrates a reset operation on the string of Fig. 20.
  • shadowing refers to a process of copying the content of volatile memory to nonvolatile memory.
  • Restore refers to a process of copying the content of non-volatile memory to volatile memory.
  • Reset refers to a process of setting non-volatile memory to a predetermined state following a restore process, or when otherwise setting the non-volatile memory to an initial state (such as when powering up for the first time, prior to ever storing data in the non-volatile memory, for example).
  • Fig. 1 is a flowchart 100 illustrating operation of a memory device according to the present invention.
  • the memory device At event 102, when power is first applied to Atty. Docket: ZENO-OOl WO the memory device, the memory device is placed in an initial state, in a volatile operational mode and the nonvolatile memory is set to a predetermined state, typically set to have a positive charge.
  • the memory device of the present invention operates in the same manner as a conventional DRAM memory cell, i.e., operating as volatile memory.
  • the content of the volatile memory is loaded into non-volatile memory at event 106, during a process which is referred to here as "shadowing" (event 106), and the data held in volatile memory is lost. Shadowing can also be performed during backup operations, which may be performed at regular intervals during DRAM operation 104 periods, and/or at any time that a user manually instructs a backup. During a backup operation, the content of the volatile memory is copied to the non-volatile memory while power is maintained to the volatile memory so that the content of the volatile memory also remains in volatile memory.
  • the device can be configured to perform the shadowing process anytime the device has been idle for at least a predetermined period of time, thereby transferring the contents of the volatile memory into non-volatile memory and conserving power.
  • the predetermined time period can be about thirty minutes, but of course, the invention is not limited to this time period, as the device could be programmed with virtually any predetermined time period.
  • the memory device functions like a Flash EPROM device in that it retains the stored data in the nonvolatile memory.
  • the content of the nonvolatile memory is restored by transferring the content of the non-volatile memory to the volatile memory in a process referred to herein as the "restore" process, after which, upon resetting the memory device at event 110, the memory device is again set to the initial state (event 102) and again operates in a volatile mode, like a DRAM memory device, event 104.
  • Event 102 the initial state
  • the present invention thus provides a memory device which combines the fast operation of volatile memories with the ability to retain charge that is provided in nonvolatile memories. Further, the data transfer from the volatile mode to the non-volatile mode and vice versa, operate in parallel by a non- algorithmic process described below, which greatly enhances the speed of operation of the storage device.
  • a description of operation of the memory device in a personal computer follows.
  • the volatile mode provides a fast access speed and is what is used during normal operations (i.e., when the power is on to the memory device).
  • the memory device according to the present invention operates in volatile mode.
  • Fig. 2 schematically illustrates an embodiment of a memory cell 50 according to the present invention.
  • the cell 50 includes a substrate 12 of a first conductivity type, such as a p-type conductivity type, for example.
  • Substrate 12 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • the substrate 12 has a surface 14.
  • a first region 16 having a second conductivity type, such as n-type, for example, is provided in substrate 12 and which is exposed at surface 14.
  • a second region 18 having the second Atty. Docket: ZENO-OOlWO conductivity type is also provided in substrate 12, which is exposed at surface 14 and which is spaced apart from the first region 16.
  • First and second regions 16 and 18 are formed by an implantation process formed on the material making up substrate 12, according to any of implantation processes known and typically used in the art.
  • a buried layer 22 of the second conductivity type is also provided in the substrate 12, buried in the substrate 12, as shown. Region 22 is also formed by an ion implantation process on the material of substrate 12.
  • a body region 24 of the substrate 12 is bounded by surface 14, first and second regions 16,18 and insulating layers 26 (e.g. shallow trench isolation (STI)), which may be made of silicon oxide, for example. Insulating layers 26 insulate cell 50 from neighboring cells 50 when multiple cells 50 are joined to make a memory device.
  • a floating gate or trapping layer 60 is positioned in between the regions 16 and 18, and above the surface 14. Trapping layer/floating gate 60 is insulated from surface 14 by an insulating layer 62.
  • Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high "K" dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide.
  • Floating gate/trapping layer 60 may be made of polysilicon material. If a trapping layer is chosen, the trapping layer may be made from silicon nitride or silicon nanocrystal, etc. Whether a floating gate 60 or a trapping layer 60 is used, the function is the same, in that they hold data in the absence of power. The primary difference between the floating gate 60 and the trapping layer 60 is that the floating gate 60 is a conductor, while the trapping layer 60 is an insulator layer. Thus, typically one or the other of trapping layer 60 and floating gate 60 are employed in device 50, but not both.
  • a control gate 66 is positioned above floating gate/trapping layer 60 and insulated therefrom by insulating layer 64 such that floating gate/trapping layer 60 is positioned between insulating layer 62 and surface 14 underlying floating gate/trapping layer 60, and insulating layer 64 and control gate 66 positioned above floating gate/trapping layer 60, as shown.
  • Control gate 66 is capacitively coupled to floating gate/trapping layer 60.
  • Control gate 66 is typically made of polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides. The relationship between the floating gate/trapping layer 60 Atty.
  • ZENO-OOl WO and control gate 66 is similar to that of a nonvolatile stacked gate floating gate/trapping layer memory cell.
  • the floating gate/trapping layer 60 functions to store non-volatile memory data and the control gate 66 is used for memory cell selection.
  • Cell 50 includes four terminals: word line (WL) terminal 70, source line (SL) terminal 72, bit line (BL) terminal 74 and buried well (BW) terminal 76.
  • Terminal 70 is connected to control gate 66.
  • Terminal 72 is connected to first region 16 and terminal 74 is connected to second region 18.
  • terminal 72 can be connected to second region 18 and terminal 74 can be connected to first region 16.
  • Terminal 76 is connected to buried layer 22.
  • cell 50 When power is applied to cell 50, cell 50 operates like a currently available capacitorless DRAM cell.
  • the memory information i.e., data that is stored in memory
  • the memory information is stored as charge in the floating body of the transistor, i.e., in the body 24 of cell 50.
  • the presence of the electrical charge in the floating body 24 modulates the threshold voltage of the cell 50, which determines the state of the cell 50.
  • Figs. 3A-3B illustrate alternative write state "1" operations that can be carried out on cell 50, by performing band-to-band tunneling hot hole injection (Fig. 3A) or impact ionization hot hole injection (Fig. 3B).
  • electrons can be transferred, rather than holes.
  • Fig. 3A to write a state "1" into the floating body region 24, a substantially neutral voltage is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a negative voltage is applied to WL terminal 70 and a positive voltage less than the positive voltage applied to the BL terminal 74 is applied to BW terminal 76. Under these conditions, holes are injected from BL terminal 76 into the floating body region 24, leaving the body region 24 positively charged.
  • a charge of about 0.0 volts is applied to terminal 72
  • a charge of about +2.0 volts is applied to terminal 74
  • a charge of about -1.2 volts is applied to terminal 70
  • a charge of about +0.6 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.4 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts Atty.
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about -3.0 volts, and voltage applied to terminal 76 may be in the range of about 0.0 volts to about +1.0 volts. Further, the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a positive voltage applied to terminal 72 and a neutral charge applied to terminal 74.
  • a substantially neutral voltage is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a positive voltage less positive than the positive voltage applied to terminal 72 is applied to WL terminal 70 and a positive voltage less positive than the positive voltage applied to terminal 74 is applied to BW terminal 76.
  • holes are injected from BL terminal 74 into the floating body region 24, leaving the body region 24 positively charged, hi one particular non-limiting embodiment, about 0.0 volts is applied to terminal 72, about +2.0 volts is applied to terminal 74, about +1.2 volts is applied to terminal 70, and about +0.6 volts is applied to terminal 76.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about +1.6 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about 1.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a positive voltage applied to terminal 72 and a neutral charge applied to terminal 74.
  • Fig. 4 illustrates a write state "0" operation that can be carried out on cell 50.
  • a negative voltage is applied to SL terminal 72
  • a substantially neutral voltage is applied to BL terminal 74
  • a negative voltage less negative than the negative voltage applied to terminal 72 is applied to WL terminal 70 and a positive voltage is applied to BW terminal 76.
  • the p-n junction junction between 24 and 16 and between 24 and 18
  • the p-n junction is forward-biased, evacuating any holes from the Atty. Docket: ZENO-OOl WO floating body 24.
  • about -2.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about -1.2 volts is applied to terminal 70, and about +0.6 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about -1.0 volts to about - 3.0 volts
  • voltage applied to terminal 74 may be in the range of about -1.0 volts to about -3.0 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about 1.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a substantially neutral voltage applied to terminal 72 and a negative charge applied to terminal 74.
  • a read operation of the cell 50 is now described with reference to Fig. 5.
  • a substantially neutral charge volts is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a positive voltage that is more positive than the positive voltage applied to terminal 74 is applied to WL terminal 70 and a positive voltage that is less than the positive voltage applied to terminal 70 is applied to BW terminal 76.
  • a lower threshold voltage gate voltage where the transistor is turned on
  • about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to terminal 74, about +1.2 volts is applied to terminal 70, and about +0.6 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • terminal 72 is grounded and is thus at about 0.0 volts
  • voltage applied to terminal 74 may be in the range of about +0.1 volts to about +1.0 volts
  • voltage applied to terminal 70 may be in the range of about +1.0 volts to about +3.0 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about 1.0 volts.
  • terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a positive voltage applied to terminal 72 and a neutral charge applied to terminal Atty. Docket: ZENO-OOl WO 74.
  • a high positive voltage (e.g., about +18 volts) is applied to WL terminal 70 and a low positive voltage (e.g., about +0.6 volts) is applied to BW terminal 76.
  • a low positive voltage e.g., about +0.6 volts
  • BW terminal 76 If cell 50 is in a state "1" as illustrated in Fig. 6A, thus having holes in body region 24, a lower electric field between the floating gate/trapping layer 60 and the floating body region 24 is observed in comparison to the electric field observed between the floating gate/trapping layer 60 and the floating body region 24 when cell 50 is in a state "0" as illustrated in Fig. 6B.
  • terminals 72 and 74 are allowed to float, about +18 volts is applied to terminal 70, and about +0.6 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 70 may be in the range of about +12.0 volts to about +20.0 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about 1.0 volts.
  • floating gate/trapping layer 60 If the floating gate/trapping layer 60 is not negatively charged, no electrons will tunnel from floating gate/trapping layer 60 to floating body 24, and cell 50 will therefore be in a state "1". Conversely, if floating gate/trapping layer 60 is negatively charged, electrons tunnel from floating gate/trapping layer 60 into floating body 24, thereby placing cell 50 in a state "0".
  • about -18.0 volts is applied to terminal 70
  • about +0.6 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 70 may be in the range of about -12.0 volts to about -20.0 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about +1.0 volts.
  • this process occurs non-algorithmically, as the state of the floating gate/trapping layer 60 does not have to be read, interpreted, or otherwise measure to determine what state to restore the floating body 24 to. Rather, the restoration process occurs automatically, driven by electrical potential differences. Accordingly, this process is orders of magnitude faster than one that requires algorithmic intervention. Similarly, it is noted that the shadowing process also is performed as a non-algorithmic process. From these operations, it has been shown that cell 50 provides a memory cell having the advantages of a DRAM cell, but where non-volatility is also achieved.
  • FIGs. 8A-8D illustrate another embodiment of operation of cell 50 to perform a volatile to non-volatile shadowing process, which operates by a hot electron injection process, in contrast to the tunneling process (e.g., Fowler- Nordheim tunneling process) described above with regard to Figs. 6A-6B.
  • Fig. 8E illustrates the operation of an NPN bipolar device 90, as it relates to the operation of cell 50.
  • Floating body 24 is represented by the terminal to which Atty. Docket: ZENO-OOl WO voltage V FB is applied in Fig. 8E, and the terminals 72 and 74 are represented by terminals to which voltages V SL and V BL are applied, respectively.
  • V FB When V FB is a positive voltage, this turns on the bipolar device 90, and when V FB is a negative or neutral voltage, the device 90 is turned off.
  • V FB When V FB is a positive voltage, this turns on the bipolar device 90, and when V FB is a negative or neutral voltage, the device 90 is turned off.
  • floating body 24 has a positive voltage, this turns on the cell 50 so that current flows through the NPN junction formed by 16, 24 and 18 in the direction indicated by the arrow in floating body 24 in Fig. 8A, and when floating body 24 has a negative or neutral voltage, cell is turned off, so that there is no current flow through the NPN junction.
  • a high positive voltage is applied to terminal 72 and a substantially neutral voltage is applied to terminal 74.
  • a high positive voltage can be applied to terminal 74 and a substantially neutral voltage can be applied to terminal 72.
  • a positive voltage is applied to terminal 70 and a low positive voltage is applied to terminal 76.
  • a high voltage in this case is a voltage greater than or equal to about +3 volts. In one example, a voltage in the range of about +3 to about +6 volts is applied, although it is possible to apply a higher voltage.
  • the floating gate/trapping layer 60 will have been previously initialized or reset to have a positive charge prior to the operation of the cell 50 to store data in non-volatile memory via floating body 24.
  • the NPN junction is on, as noted above, and electrons flow in the direction of the arrow shown in the floating body 24 in Fig. 8 A.
  • the application of the high voltage to terminal 72 at 16 energizes/accelerates electrons traveling through the floating body 24 to a sufficient extent that they can "jump over" the oxide barrier between floating body 24 and floating gate/trapping layer 60, so that electrons enter floating gate/trapping layer 60 as indicated by the arrow into floating gate/trapping layer 60 in Fig. 8A.
  • floating gate/trapping layer 60 becomes negatively charged by the shadowing process, when the volatile memory of cell 50 is in state "1" (i.e., floating body 24 is positively charged), as shown in Fig. 8B.
  • the high positive voltage applied to terminal 72 does not cause an acceleration of electrons in order to cause hot electron injection into floating gate/trapping layer 60, since the electrons are not flowing. Accordingly, floating gate/trapping layer 60 retains its positive charge at the end of the shadowing process, when the volatile memory of cell 50 is in state "0" (i.e., floating body 24 is neutral or negatively charged), as shown in Fig. 8D. Note that the charge state of the floating gate/trapping layer 60 is complementary to the charge state of the floating body 24 after completion of the shadowing process.
  • the floating gate/trapping layer 60 will become negatively charged by the shadowing process, whereas if the floating body of the memory cell 50 has a negative or neutral charge in volatile memory, the floating gate/trapping layer 60 will be positively charged at the end of the shadowing operation.
  • the charges/states of the floating gates/trapping layers 60 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
  • voltage applied to terminal 72 may be in the range of about +3 volts to about +6 volts
  • the voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.4 volts
  • the voltage applied to terminal 70 may be in the range of about 0.0 volts to about +1.6 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about +1.0 volts.
  • FIGs. 9A- 9B another embodiment of operation of cell 50 to perform a restore process from non-volatile to volatile memory is schematically illustrated, in which the restore process operates by a band-to-band tunneling hot hole injection process (modulated by the floating gate/trapping layer 60 charge), Atty. Docket: ZENO-OOl WO in contrast to the electron tunneling process described above with regard to Figs. 7A-7B.
  • the floating body 24 is set to a neutral or negative charge prior to the performing the restore operation/process, i.e., a "0" state is written to floating body 24.
  • a neutral or negative charge prior to the performing the restore operation/process
  • terminal 72 is set to a substantially neutral voltage, a positive voltage is applied to terminal 74, a negative voltage is applied to terminal 70 and a positive voltage that is less positive than the positive voltage applied to terminal 74 is applied to terminal 76.
  • the floating gate/trapping layer 60 is negatively charged, as illustrated in Fig. 9A, this negative charge enhances the driving force for the band-to-band hot hole injection process, whereby holes are injected from the n-region 18 into floating body 24, thereby restoring the "1" state that the volatile memory cell 50 had held prior to the performance of the shadowing operation.
  • the floating gate/trapping layer 60 is not negatively charged, such as when the floating gate/trapping layer 60 is positively charged as shown in Fig.
  • voltage applied to terminal 72 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about +1.0 volts.
  • the floating gate(s)/trapping layer(s) 60 is/are reset to a predetermined state, e.g., a positive state as illustrated in Fig. 10, so that each floating gate/trapping layer 60 has a known state prior to performing another shadowing operation.
  • the reset process operates by the mechanism of electron tunneling from the floating gate/trapping layer 60 to the source region 18, as illustrated in Fig. 10.
  • a highly negative voltage is applied to terminal 70, a substantially neutral voltage is applied to SL terminal 72, BL terminal 74 is allowed to float or is grounded, and a positive voltage is applied to terminal 76.
  • a neutral voltage is applied to terminal 72 and maintaining the voltage of region 16 to be substantially neutral, this causes region 16 to function as a sink for the electrons from floating gate/trapping layer 60 to travel to by electron tunneling.
  • a large negative voltages is applied to WL terminal 70 and a low positive voltage is applied to BW terminal 76. If the floating gate/trapping layer 60 is negatively charged, electrons will tunnel from floating gate/trapping layer 60 to region 16, and floating gate/trapping layer 60 will therefore become positively charged.
  • -18.0 volts is applied to terminal 70
  • +0.6 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 70 may be in the range of about -12.0 volts to about - 20.0 volts
  • the voltage applied to terminal 76 may be in the range of about 0.0 volts to about 1.0 volts.
  • ZENO-OOl WO made to Fig. 1 to describe operation of a memory device having a plurality of memory cells 50.
  • the number of memory cells can vary widely, for example ranging from less than 100 Mb to several Gb, or more. It is noted that, except for the DRAM operations of writing and reading (event 104), which by necessity must be capable of individual, controlled operations, the remaining operations shown in Fig. 1 can all be carried out as parallel, non-algorithmic operations, which results in a very fast operating memory device.
  • the memory device is initialized by first setting all of the floating gates/trapping layers to a positive state, in a manner as described above with reference to Fig. 10, for example.
  • a control line can be used to input a highly negative voltage to each of terminals 70, in parallel, with voltage settings at the other terminals as described above with reference to Fig. 10.
  • Individual bits (or multiple bits, as described below) of data can be read from or written to floating bodies 24 of the respective cells at event 104.
  • the shadowing operation at event 106 is conducted in a mass parallel, non- algorithmic process, in any of the same manners described above, with each of the cells 50 performing the shadowing operation simultaneously, in a parallel operation. Because no algorithmic interpretation or measurement is required to transfer the data from non-volatile to volatile memory (24 to 60), the shadowing operation is very fast and efficient.
  • a state "0" is first written into each of the floating bodies 24, by a parallel process, and then each of the floating bodies is restored in any of the same manners described above with regard to a restoration process of a single floating body 24.
  • This process is also a mass, parallel non-algorithmic process, so that no algorithmic processing or measurement of the states of the floating gates/trapping layers 60 is required prior to transferring the data stored by the floating gates/trapping layers 60 to the floating bodies 24.
  • the floating bodies are restored simultaneously, in parallel, in a very fast and efficient process.
  • the floating gates/trapping layers 60 are then reset at event 102, to establish a positive charge in each of the floating gates/trapping layers, in the same manner as described above with Atty. Docket: ZENO-OOl WO regard to initializing at event 102.
  • Fig. HA illustrates the states of a binary cell, relative to threshold voltage, wherein a voltage less than or equal to a predetermined voltage (in one example, the predetermined voltage is 0 volts, but the predetermined voltage may be a higher or lower voltage) in floating body 24 is interpreted as state "0", and a voltage greater than the predetermined voltage in floating body 24 is interpreted as state "1".
  • a predetermined voltage in one example, the predetermined voltage is 0 volts, but the predetermined voltage may be a higher or lower voltage
  • the memory cells described herein can be configured to function as multi-level cells, so that more than one bit of data can be stored in each cell 50.
  • Fig. HB illustrates an example of voltage states of a multi-level cell wherein two bits of data can be stored in each cell 50.
  • a voltage less than or equal to a first predetermined voltage e.g., 0 volts or some other predetermined voltage
  • a second predetermined voltage that is less than the first predetermined voltage e.g., about -0.5 volts or some other voltage less than the first predetermined voltage in floating body 24 volts
  • a voltage less than or equal to the second predetermined voltage is interpreted as state "00”
  • a voltage greater than the first predetermined voltage and less than or equal to a third predetermined voltage that is greater than the first predetermined voltage e.g., about +0.5 volts or some other predetermined voltage that is greater than the first predetermined voltage
  • a voltage greater than the third predetermined voltage is interpreted as state "11".
  • the memory cell 50 described above with regard to Figs. 2-10 can be described as a substantially planar memory cell. As the memory cell 50 is scaled to sub-50 nm features, it may be beneficial to provide a structure that overcomes short channel effects. As the channel length decreases, less gate charge is required to turn on the transistor. This results in a decrease of the threshold voltage and an increase of the off state leakage current. A device 50 such as illustrated in Fig. 12 suppresses the short channel effect by providing a gate that wraps around the silicon body, resulting in a stronger gate control of the transistor performance. Atty. Docket: ZENO-OOlWO
  • FIGs. 12 and 13 illustrate perspective and top views of an alternative embodiment of a memory cell 50 according to the present invention.
  • cell 50 has a fin structure 52 fabricated on a silicon-on-insulator (SOI) substrate 12, so as to extend from the surface of the substrate to form a three-dimensional structure, with fin 52 extending substantially perpendicularly to, and above the top surface of the substrate 12.
  • Cell 50 is a capacitorless, one- transistor device.
  • Fin structure 52 is conductive and is built on buried insulator layer 22, which may be buried oxide (BOX). Insulator layer 22 insulates the floating substrate region 24, which has a first conductivity type, from the bulk substrate 12.
  • Fin structure 52 includes first and second regions 16, 18 having a second conductivity type.
  • the floating body region 24 is bounded by the top surface of the fin 52, the first and second regions 16, 18 and the buried insulator layer 22.
  • Fin 52 is typically made of silicon, but may comprise germanium, silicon germanium, gallium arsenide, carbon nanotubes, or other semiconductor materials known in the art.
  • Device 50 further includes floating gates or trapping layers 60 on two opposite sides of the floating substrate region 24, as shown in Figs. 12 and 13.
  • Floating gates/trapping layers 60 are insulated from floating body 24 by insulating layers 62.
  • Floating gates/trapping layers 60 are positioned between the first and second regions 16, 18, adjacent to the floating body 24.
  • a control gate 66 is capacitively coupled to floating gates/trapping layers 60 and is insulated therefrom via dielectric layer 64.
  • the first and second regions 16,18 are spaced apart from one another on opposite ends of floating body 24 and define the channel region and the floating substrate region (floating body) 24.
  • Device 50 includes four terminals: word line (WL) terminal 70, source line (SL) terminal 72, bit line (BL) terminal 74 and substrate (SUB) terminal 76.
  • Control gate 66 is connected to terminal 70, first and second regions 16, 18 are connected to terminals 72 and 74, respectively, or vice versa, and the bulk substrate 12 is connected to terminal 76.
  • cell 50 When power is applied, cell 50 operates in volatile mode, like a Atty. Docket: ZENO-OOl WO capacitorless DRAM cell. That is, data (memory information) is stored in the floating body 24 of the transistor. The presence of electrical charge in the floating body 24 modulates the threshold voltage of the device 50.
  • Figs. 14A-14B illustrate alternative write state "1" operations that can be carried out on an embodiment of cell 50 as described in Fig. 12-13, by performing band-to-band tunneling hot hole injection (Fig. 14A) or impact ionization hot hole injection (Fig. 14B).
  • electrons can be transferred, rather than holes.
  • Fig. 14 A to write a state "1" into the floating body region 24, a neutral voltage is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a negative voltage is applied to WL terminal 70 and a large negative voltage which is more negative than the negative voltage applied to terminal 70, is applied to SUB terminal 76. Under these conditions, holes are injected from BL terminal 74 into the floating body region 24, leaving the body region 24 positively charged.
  • a charge of about 0.0 volts is applied to terminal 72, a charge of about +2.0 volts is applied to terminal 74, a charge of about -1.2 volts is applied to terminal 70, and a charge of about -10.0 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.4 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result.
  • a substantially neutral voltage is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a positive voltage less positive than the positive voltage applied to terminals 72 and 74 is applied to WL terminal 70 and a negative is applied to SUB terminal 76. Under these conditions, holes are injected from BL terminal 74 into the floating body region 24, leaving the body region 24 positively charged.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about +1.6 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a positive voltage applied to terminal 72 and a neutral charge applied to terminal 74.
  • Fig. 15 illustrates a write state "0" operation that can be carried out on cell 50.
  • a negative voltage is applied to SL terminal 72
  • a substantially neutral voltage is applied to BL terminal 74
  • a negative voltage that is less negative than the negative voltage applied to terminal 72 is applied to WL terminal 70
  • a substantially neutral voltage is applied to SUB terminal 76.
  • all p-n junctions junction between 24 and 16 and between 24 and 18 are forward-biased, evacuating any holes from the floating body 24.
  • about -2.0 volts is applied to terminal 72, about 0.0 volts is applied to terminal 74, about -1.2 volts is applied to terminal 70, and about 0.0 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about -1.0 volts to about -3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to terminal 76 may be in the range of about 0.0 volts to about +2.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a substantially neutral voltage applied to terminal 72 and a negative charge applied to terminal 74.
  • a substantially neutral charge is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a positive voltage that is more positive than the positive voltage applied to terminal 74 is applied to WL terminal 70 and a negative voltage is applied to SUB terminal 76. If cell 50 is in a state "1" having holes in the body region 24, then a lower threshold voltage (gate voltage where the transistor is turned on) is observed compared to the threshold voltage observed when cell 50 is in a state "0" having no holes in body region 24.
  • about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to terminal 74, about +1.2 volts is applied to terminal 70, and about -10.0 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • terminal 72 is grounded and is thus at about 0.0 volts
  • voltage applied to terminal 74 may be in the range of about +0.1 volts to about +1.0 volts
  • voltage applied to terminal 70 may be in the range of about +1.0 volts to about +3.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, e.g., a positive voltage applied to terminal 72 and a neutral charge applied to terminal 74.
  • the shadowing operation may be performed by first applying a high positive voltage to terminal 72. After a short period of time (e.g., a time period in the range of about 500 ns to about 10 ⁇ s, typically about 1 ⁇ s), the voltage applied to terminal 72 is brought down to substantially neutral (i.e., ground), followed by application of a high positive voltage to terminal 70.
  • a short period of time e.g., a time period in the range of about 500 ns to about 10 ⁇ s, typically about 1 ⁇ s
  • substantially neutral i.e., ground
  • a negative voltage is applied to terminal 76 throughout the operation, and a substantially neutral voltage is applied to terminal 74. If the memory transistor does not have holes in the floating substrate 24 (state "0") the voltage conditions applied to cell 50 as described will result in a potential Atty. Docket: ZENO-OOl WO difference between the n + junctions and the p-type floating substrate 24, sufficient to generate substrate transient hot electrons. If cell 50 is in a state "1" (i.e., memory transistor has holes in the floating substrate 24), a lower electric field between the n + junctions and the p-type floating substrate 24 exists, and, as a result, no transient hot electrons are generated.
  • the transient hot electrons that are generated are collected in the floating gate/trapping layer 60 due to the electric field resulting from the high positive bias applied on the control gate 66 via terminal 70.
  • a high negative voltage can be applied to terminal 70 to collect transient hot holes.
  • a voltage of about +6.0 volts is initially applied to terminal 72. After bringing the voltage applied to terminal 72 down to ground, a voltage of about +10.0 volts is applied to terminal 70. Voltages of about 0 volts and about -10.0 volts, respectively, are applied to terminals 74 and 76 throughout the process. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about +3.0 volts to about +6.0 volts, prior to dropping the voltage to about 0 volts; voltage applied to terminal 70 may be in the range of about +3.0 volts to about +12.0 volts; voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.6 volts, and voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts. Further, the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result.
  • the state of the cell 50 memory transistor as stored on floating gate/trapping layer 60 is restored into floating body region 24.
  • the restore operation data restoration from non-volatile memory to volatile memory
  • the floating body 24 is set to a neutral or negative charge, i.e., a "0" state is written to floating body 24.
  • a substantially neutral voltage is applied to terminal 72
  • a positive voltage is applied to terminal 74
  • a positive voltage that is less positive than the positive voltage applied to terminal 74 is applied to terminal 70
  • a negative voltage is applied to terminal 76.
  • a voltage of about 0 volts is applied to terminal 72
  • a voltage of about +2.0 volts is applied to terminal 74
  • a voltage of about +1.2 volts is applied to terminal 70
  • a voltage of about -10 volts is applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about +1.6 volts
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result.
  • the process operates by a hot electron injection process.
  • a high positive voltage is applied to terminal 72 and a substantially neutral voltage is applied to terminal 74.
  • a high positive voltage can be applied to terminal 74 and a substantially neutral voltage can be applied to terminal 72.
  • a positive voltage is applied to terminal 70 and a negative voltage is applied to terminal 76.
  • a high voltage in this case is a voltage greater than or equal to about +3 volts, hi one example, a voltage in the range of about +3 to about +6 volts is applied, although it is possible to apply a higher voltage.
  • the floating gate/trapping layer 60 will have been previously initialized or reset to have a positive charge prior to the operation of the cell 50 to store data in non-volatile memory via floating body 24.
  • the NPN junction is on, as noted above.
  • the application of the high voltage to terminal 72 at 16 energizes/accelerates electrons traveling through the floating body 24 to a sufficient extent that they can "jump over" the oxide barrier 62 between floating body 24 and floating gate/trapping layer 60, so Atty. Docket: ZENO-OOl WO that electrons enter floating gate/trapping layer 60. Accordingly, floating gate/trapping layer 60 becomes negatively charged by the shadowing process, when the volatile memory of cell 50 is in state "1" (i.e., floating body 24 is positively charged).
  • the charge state of the floating gate/trapping layer 60 is complementary to the charge state of the floating body 24 after completion of the shadowing process.
  • the floating gate/trapping layer 60 will become negatively charged by the shadowing process, whereas if the floating body of the memory cell 50 has a negative or neutral charge in volatile memory, the floating gate/trapping layer 60 will be positively charged at the end of the shadowing operation.
  • the charges/states of the floating gates/trapping layers 60 are determined non-algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
  • ZENO-OOlWO voltage applied to terminal 76 may be in the range of about -4.0 volts to about - 12.0 volts.
  • terminal 72 is set to a substantially neutral voltage, a positive voltage is applied to terminal 74, a negative voltage is applied to terminal 70 and a negative voltage that is more negative than the negative voltage applied to terminal 70 is applied to terminal 76. If the floating gate/trapping layer 60 is negatively charged, this negative charge enhances the driving force for the band-to-band hot hole injection process, whereby holes are injected from the n-region 18 into floating body 24, thereby restoring the "1" state that the volatile memory cell 50 had held prior to the performance of the shadowing operation.
  • the floating gate/trapping layer 60 is not negatively charged, such as when the floating gate/trapping layer 60 is positively charged or is neutral, the hot band-to-band hole injection process will not occur, resulting in memory cell 50 having a "0" state, just as it did prior to performance of the shadowing process. Accordingly, if floating gate/trapping layer 60 has a positive charge after shadowing is performed, the volatile memory of floating body 24 will be restored to have a negative charge ("0" state), but if the floating gate/trapping layer 60 has a negative or neutral charge, the volatile memory of floating body 24 will be restored to have a positive charge ("1" state).
  • voltage applied to terminal 72 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 70 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the restore processes described above are non-algorithmic processes, as the state of the floating gate/trapping layer 60 does not have to be read, interpreted, or otherwise measured to determine what state to restore the Atty. Docket: ZENO-OOlWO floating body 24 to. Rather, the restoration process occurs automatically, driven by electrical potential differences. Accordingly, this process is orders of magnitude faster than one that requires algorithmic intervention.
  • the shadowing processes described above are also performed as non- algorithmic processes. When multiple cells 50 are provided in a memory device, shadowing and restore operations are performed as parallel, non-algorithmic processes.
  • cell 50 provides a memory cell having the advantages of a DRAM cell, but where non-volatility is also achieved, and wherein a fin is provided to facilitate denser packing of memory cells and to suppress short channel effects, which in turn allows device scaling to smaller geometry.
  • the floating gate(s)/trapping layer(s) 60 is/are reset to a predetermined initial state, e.g., a positive state as illustrated in Fig. 19, so that each floating gate/trapping layer 60 has a known state prior to performing another shadowing operation.
  • the reset process operates by the mechanism of electron tunneling from the floating gate/trapping layer 60 to the source region 18, as illustrated in Fig. 19.
  • a highly negative voltage is applied to terminal 70
  • a substantially neutral voltage is applied to SL terminal 72
  • BL terminal 74 is allowed to float or is grounded (e.g., a substantially neutral charge can be applied)
  • a negative voltage that is less negative than the negative voltage applied to terminal 70 is applied to terminal 76.
  • floating gate/trapping layer 60 If the floating gate/trapping layer 60 is negatively charged, electrons will tunnel from floating gate/trapping layer 60 to region 16, and floating gate/trapping layer 60 will therefore become positively charged. As a result of the reset operation, all of the floating gate/trapping layer will become positively charged. In one particular non- limiting embodiment, about -18.0 volts is applied to terminal 70, and about -10.0 volts is applied to terminal 76. However, these voltage levels may vary, while Atty. Docket: ZENO-OOl WO maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 70 may be in the range of about -12.0 volts to about -20.0 volts
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about +3.0 volts
  • the voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result.
  • a high positive voltage e.g., about +18.0 volts, or a voltage in the range of about +12.0 volts to about +20.0 volts is applied to terminal 70 to reset the floating gate(s)/trapping layer(s) 60 to the initial state.
  • a high positive voltage e.g., about +18.0 volts, or a voltage in the range of about +12.0 volts to about +20.0 volts is applied to terminal 70 to reset the floating gate(s)/trapping layer(s) 60 to the initial state.
  • n + junction region either 16 or 18, or both, depending on whichever region(s) is/are grounded
  • Memory string 500 includes a plurality of memory cells 50 connected in a NAND architecture, in which the plurality of memory cells 50 are serially connected to make one string of memory cells.
  • String 500 includes "n" memory cells 50, where "n” is a positive integer, which typically ranges between 8 and 64, and in at least one example, is 16.
  • String 500 includes a selection transistor 68, a ground selection transistor 80, and a plurality (i.e., "n") memory cell transistors 50 (50a, 50b, ..., 50m, 5On), all of which are connected in series.
  • Each memory cell transistor 50 includes a floating body region 24 of a first conducting type, and first and second regions 20 (corresponding to first and second regions 16 and 18 in the single cell embodiments of cell 50 described above) of a second conductivity type, which are spaced apart from each other and define a channel region.
  • a buried insulator layer 22 isolates the floating body region 24 from the bulk substrate 12.
  • a floating gate or trapping layer 60 is positioned above the surface of floating body 24 and is in between the first and second regions 20.
  • ZENO-OOlWO insulating layer 62 is provided between floating gate/trapping layer 60 and floating body 24 to insulate floating gate/trapping layer 60 from floating body 24.
  • a control gate 66 is insulated and separated from the floating gate/trapping layer 60 by an insulating layer 64. The control gate 66 is capacitively coupled to the floating gate/trapping layer 60.
  • the relationship between the floating gate/trapping layer 60 and the control gate 66 is similar to that of a non-volatile stacked gate floating gate memory cell.
  • Cells 50 may be provided as substantially planar cells, such as the embodiments described above with reference to Figs. 1-10, or may be provided as fin-type, three-dimensional cells, such as the embodiments described above with reference to Figs. 12-19. Other variations, modifications and alternative cells 50 may be provided without departing from the scope of the present invention and its functionality.
  • Fig. 21 illustrates a top view of the string 500.
  • the memory cell transistors 50 are serially connected.
  • a memory array is typically arranged in a grid, with the WL terminal being used to select the row and the BL terminal being sued to select the column, so that, in combination, any single memory cell (or more) in the grid can be selected.
  • String 500 lies in the column direction of the grid.
  • the serial connection arrangement typically defines a memory array column direction. Adjacent columns are separated by columns of isolation, such as shallow trench isolation (STI).
  • the drain region of the string selection transistor 68 is connected to the bit line (BL) 74.
  • Fig. 21 illustrates two columns, and thus, two bit lines 74, for exemplary purposes. In practice, there will typically be many more than two columns.
  • the source region of the ground selection transistor 80 is connected to the SL terminal 72.
  • the control gates 66 extend in row directions.
  • the WL and BL pitches can each be made to be 2F, where F is defined as the feature size (the smallest lithography feature). Accordingly, each memory cell transistor 50 has a size of 4F 2 .
  • Figs. 22A-22B illustrate alternative write state "1" operations that can be carried out string 500, by performing band-to-band tunneling hot hole injection (Fig. 22A) or impact ionization hot hole injection (Fig. 22B).
  • electrons can be transferred, rather than holes.
  • Fig. 22A to write a state "1" into a floating body region 24 of a selected cell 50, a Atty. Docket: ZENO-OOlWO substantially neutral voltage is to terminal 72, a positive voltage is applied to BL terminal 74, a negative voltage is applied to the selected control gate 66 (i.e., 66b in the example of Fig.
  • a positive voltage, more positive that the positive voltage applied to terminal 74 is applied to the passing control gates 66 (i.e., control gates 66 of the cells 50 not having been selected), positive voltage about equal to the positive voltage applied to the passing control gates 66 is applied to the gates of the string selection transistor 68 and the ground selection transistor 80, and a negative voltage more negative than the negative voltage applied to the selected control gate 66 is applied to the substrate via terminal 76.
  • the voltages applied to the selection transistors 68 and 80 and the passing control gates 66 are such that the channel regions underneath the respective gates of these transistors are turned on.
  • a voltage of about 0.0 volts is applied to terminal 72, about +2.0 volts is applied to terminal 74, about -1.2 volts is applied to terminal 70 of the selected control gate 66, about +3.0 is applied to the terminals 70 of the passing control gates 66, about +3.0 volts is applied to the gate of the string selection transistor 68, about +3.0 volts is applied to the gate of the ground selection transistor 80, and a voltage of about -10.0 volts is applied to the substrate via terminal 76.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 70 of the selected control gate 66 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to the terminals 70 of the passing control gates 66 of the cells 50 not selected may be in the range of about +2.0 volts to about +6.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the ground selection transistor 80 may be in Atty Docket ZENO-OOlWO the range of about +1.0 volts to about +5.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts
  • a substantially neutral voltage may be applied to terminal 72, a positive voltage may be applied to BL terminal 74, a positive voltage less positive than the positive voltage applied to terminal 74 may be applied to gate 66 of the selected cell 50 via terminal 70 of the selected cell 50, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to terminals 70 of each of the non-selected cells 50, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to the gate of string selection transistor 68, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to the gate of ground selection transistor 80, and a negative voltage is applied to the substrate via terminal 76. Under these conditions, holes are injected from the drain side of the selected memory transistor cell 50 into the floating body region 24 of the selected memory cell 50, leaving the body region 24 positively charged and thus putting the selected memory cell 50 in state "1".
  • 0.0 volts is applied to terminal 72
  • about +2.0 volts is applied to terminal 74
  • about +1.2 volts is applied to control gate 66 via terminal 70 of the selected memory cell (in this example, cell 50b)
  • about +3.0 volts is applied to each of the control gates 66 of the non-selected memory cells
  • a voltage of about +3.0 volts is applied to the gate of the string selection transistor 68
  • a voltage of about +3.0 volts is applied to the gate of the ground selection transistor 80
  • a voltage of about -10.0 volts is applied to terminal 76.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 70 of the selected control gate 66 may be in the range of about 0.0 volts to about +1.6 volts; voltage applied to the Atty.
  • ZENO-OOlWO terminals 70 of the passing control gates 66 of the cells 50 not selected may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the ground selection transistor 80 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result.
  • Fig. 23 illustrates an example of a write state "0" operation carried out on a selected cell 50 of the string 500.
  • a negative voltage is applied to SL terminal 72
  • a substantially neutral voltage is applied to BL terminal 74
  • a substantially neutral voltage is applied to all of the control gates 66 via their respective WL terminals 70
  • a positive voltage is applied to the gate of the ground selection transistor 80
  • a substantially neutral voltage is applied to the gate of the string selection transistor 68
  • a substantially neutral voltage is applied to the substrate via terminal 76.
  • all p-n junctions are forward -biased, evacuating any holes from the floating body 24.
  • the write "0" operation is performed simultaneously on all cells sharing the same SL terminal 72.
  • voltage applied to terminal 72 may be in the range of about -1.0 volts to about - 3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to each of the terminals 70 may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about 0.0 volts to about 5.0 volts, Atty.
  • ZENO-OOl WO voltage applied to the gate of the ground selection transistor 80 may be in the range of about 0.0 volts to about +5.0 volts, and voltage applied to terminal 76 may be in the range of about 0.0 volts to about +2.0 volts. Further, the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, even when the voltages applied to terminals 72 and 74 are not equal.
  • a read operation is now described with reference to Fig. 24.
  • a substantially neutral charge is applied to SL terminal 72, a positive voltage is applied to BL terminal 74, a positive voltage that is more positive than the positive voltage applied to terminal 74 is applied to WL terminal 70 of the control gate 66 of the selected cell 50, a positive voltage that is more positive than the positive voltage applied to the terminal 70 of the selected cell is applied to each of passing control gates 66 via the terminals 70 of the non-selected cells 50, a positive voltage that is more positive than the positive voltage applied to the terminal 70 of the selected cell is applied to the gate of the string selection transistor 68, a positive voltage that is more positive than the positive voltage applied to the terminal 70 of the selected cell is applied to the gate of the ground selection terminal 80, and a negative voltage is applied to terminal 76.
  • the voltages applied to the selection transistors 68, 80 and the passing control gates 66 are such that the channel regions underneath these gates are turned on. If the selected memory transistor cell 50 is in a state "1" having holes in the floating body region 24 thereof, then a relatively lower threshold voltage is observed, relative to when the selected memory transistor cell 50 is in a state "0" and has no holes in the floating body region 24.
  • about 0.0 volts is applied to terminal 72, about +0.4 volts is applied to terminal 74, about +1.2 volts is applied to terminal 70 (and thus control gate 66) of the selected memory cell 50, about +3.0 volts is applied to each of the terminals 70 (and thus the passing control gates 66) of the non-selected memory cells ' 50, a voltage of about +3.0 volts is applied to the gate of the string selection transistor 68, a voltage of about +3.0 volts is applied to the gate of the ground selection transistor 80, and about - 10.0 volts is applied to terminal 76.
  • Atty. Docket: ZENO-OOlWO terminal 72 is grounded, and thus at about 0.0 volts, voltage applied to terminal 74 may be in the range of about +0.1 volts to about +1.0 volts, voltage applied to terminal 70 of the selected control gate 66 may be in the range of about 0.0 volts to about +3.0 volts; voltage applied to the terminals 70 of the passing control gates 66 of the cells 50 not selected may be in the range of about +1.0 volts to about +5.0 volts, voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts, voltage applied to the gate of the ground selection transistor 80 may be in the range of about +1.0 volts to about +5.0 volts, and voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result, even when the voltages applied to terminals 72 and 74 are not equal.
  • power down e.g., when a user turns off the power to string 500, or the power is inadvertently interrupted, or for any other reason, power is at least temporarily discontinued to string 500
  • data stored in the floating body regions 24 are transferred to floating gate/trapping layers 60 via a shadowing operation.
  • the shadowing operation may be performed by first applying a high positive voltage to terminal 72. After a short period of time, e.g.
  • the voltage applied to terminal 72 is brought down to substantially neutral (i.e., ground), followed by application of a high positive voltage to each of terminals 70 and thus to each of control gates 66.
  • a negative voltage is applied to terminal 76 throughout the operation, and a substantially neutral voltage is applied to terminal 74. If a memory transistor cell 50 does not have holes in the floating substrate 24 (state "0") the voltage conditions applied to that cell 50 as described will result in a potential difference between the n + junctions and the p-type floating substrate 24, sufficient to generate substrate transient hot electrons.
  • a cell 50 is in a state "1" (i.e., memory transistor cell 50 has holes in the floating substrate 24), a lower electric field between the n + junctions and the p-type floating substrate 24 exists, and, as a result, no transient hot electrons are generated.
  • state "0" the transient hot electrons that are generated are collected in the floating gate/trapping layer 60 of that cell 50 due to the electric field resulting from the Atty. Docket: ZENO-OOl WO high positive bias applied on the control gate 66 via terminal 70.
  • a high negative voltage can be applied to all terminals 70 to collect transient hot holes from floating bodies in state "1".
  • a voltage of about +6.0 volts is initially applied to terminal 72. After bringing the voltage applied to terminal 72 down to ground, a voltage of about +10.0 volts is applied to each terminal 70. Voltages of about 0 volts and about -10.0 volts, respectively, are applied to terminals 74 and 76 throughout the process. However, these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about +3.0 volts to about +6.0 volts, prior to dropping the voltage to about 0 volts; voltage applied to terminals 70 may be in the range of about +3.0 volts to about +12.0 volts; voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.6 volts, and voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts. Further, the voltages applied to terminals 72 and 74 may be reversed, and still obtain the same result.
  • a substantially neutral voltage is applied to terminal 72, a positive voltage is applied to terminal 74, a positive voltage that is less positive than the positive voltage applied to terminal 74 is applied to each selected terminal 70 of each selected cell 50, a positive voltage that is more positive than the positive voltage applied to terminal 74 is applied to each passing control gate via each terminal 70 of each non-selected cell 50, a positive voltage that is more positive than the positive voltage applied to Atty.
  • Docket: ZENO-OOl WO terminal 74 is applied to the gate of the string selection transistor 68, a positive voltage that is more positive than the positive voltage applied to terminal 74 is applied to the gate of the ground selection transistor, and a negative voltage is applied to terminal 76.
  • a voltage of about 0 volts is applied to terminal 72, a voltage of about +2.0 volts is applied to terminal 74, a voltage of about +1.2 volts is applied to terminal 70 of each selected cell 50, a voltage of about +3.0 volts is applied to each terminal 70 of each non-selected cell 50, a voltage of about +3.0 volts is applied to the gate of the string selection transistor 68, a voltage of about +3.0 volts is applied to the gate of the ground selection transistor 80, and a voltage of about -10 volts is applied to terminal 76.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 74 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 70 of the selected control gate 66 may be in the range of about 0.0 volts to about +1.6 volts
  • voltage applied to the terminals 70 of the passing control gates 66 of the cells 50 not selected may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the ground selection transistor 80 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the voltages applied to terminals 72 may be in the range of about 0.0 volts to about +0.6 volts
  • shadowing and restore operations are performed as parallel, non-algorithmic processes.
  • string 50 can be operated to perform a volatile to non- volatile shadowing process by a hot electron injection process.
  • a high positive voltage is applied to terminal 72 and a substantially neutral voltage is applied to terminal 74.
  • a high positive voltage can be applied to terminal 74 and a substantially neutral voltage can be applied to terminal 72.
  • a positive voltage is applied to terminal 70 of the selected cell 50, a positive voltage that is more positive than the positive voltage applied to the terminal 70 of the selected cell is applied to each of passing control gates 66 via the terminals 70 of the non- selected cells 50, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to the gate of string selection transistor 68, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to the gate of ground selection transistor 80, and a negative voltage is applied to terminal 76.
  • a high voltage in this case is a voltage greater than or equal to about +3 volts. In one example, a voltage in the range of about +3 to about +6 volts is applied, although it is possible to apply a higher voltage.
  • the floating gate/trapping layer 60 will have been previously initialized or reset to have a positive charge prior to the operation of the cell 50 to store data in nonvolatile memory via floating body 24.
  • the NPN junction is on, as noted above, and electrons flow in the floating body 24.
  • the application of the high voltage to terminal 72 at 16 energizes/accelerates electrons traveling through the floating body 24 to a sufficient extent that they can "jump over" the oxide barrier 62 Atty. Docket: ZENO-OOlWO between floating body 24 and floating gate/trapping layer 60, so that electrons enter floating gate/trapping layer 60. Accordingly, floating gate/trapping layer 60 becomes negatively charged by the shadowing process, when the volatile memory of cell 50 is in state "1" (i.e., floating body 24 is positively charged).
  • the charge state of the floating gate/trapping layer 60 is complementary to the charge state of the floating body 24 after completion of the shadowing process.
  • the floating gate/trapping layer 60 will become negatively charged by the shadowing process, whereas if the floating body of the memory cell 50 has a negative or neutral charge in volatile memory, the floating gate/trapping layer 60 will be positively charged at the end of the shadowing operation.
  • the charges/states of the floating gates/trapping layers 60 are determined non- algorithmically by the states of the floating bodies, and shadowing of multiple cells occurs in parallel, therefore the shadowing process is very fast.
  • the voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.4 volts
  • the voltage applied to terminal 70 of the selected cells may be in the range of about 0.0 volts to about +1.6 volts
  • voltage applied to the terminals 70 of the passing control gates 66 of the cells 50 not selected may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the ground selection transistor 80 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • terminal 72 is set to a substantially neutral voltage, a positive voltage is applied to terminal 74, a negative voltage is applied to terminal 70 of the selected cells, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to terminal 70 of the unselected cells, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to the gate of string selection transistor 68, a positive voltage more positive than the positive voltage applied to terminal 74 is applied to the gate of ground selection transistor 80, and a negative voltage that is more negative than the negative voltage applied to terminal 70 is applied to terminal 76.
  • the floating gate/trapping layer 60 of a selected cell 50 is negatively charged, this negative charge enhances the driving force for the band-to-band hot hole injection process, whereby holes are injected from the n-region 18 into floating body 24, thereby restoring the "1" state that the volatile memory cell 50 had held prior to the performance of the shadowing operation. If the floating gate/trapping layer 60 of a selected cell is not negatively charged, such as when the floating gate/trapping layer 60 is positively charged or is neutral, the hot band-to-band hole injection process will not occur, resulting in memory cell 50 having a "0" state, just as it did prior to performance of the shadowing process.
  • floating gate/trapping layer 60 has a positive charge after shadowing is performed, the volatile memory of floating Atty. Docket: ZENO-OOl WO body 24 will be restored to have a negative charge ("0" state), but if the floating gate/trapping layer 60 has a negative or neutral charge, the volatile memory of floating body 24 will be restored to have a positive charge (“1" state).
  • 0 volts is applied to terminal 72
  • about +2 volts is applied to terminal 74
  • about -1.2 volts is applied to terminal 70 of the selected cells
  • about +3.0 volts are applied to terminal 70 of the unselected cells
  • a voltage of about +3.0 volts is applied to the gate of the string selection transistor 68
  • a voltage of about +3.0 volts is applied to the gate of the ground selection transistor 80
  • about -10.0 volts are applied to terminal 76.
  • these voltage levels may vary, while maintaining the relative relationships between the charges applied, as described above.
  • voltage applied to terminal 72 may be in the range of about +1.5 volts to about +3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about +0.6 volts
  • voltage applied to terminal 70 of the selected cells may be in the range of about 0.0 volts to about -3.0 volts
  • voltage applied to the terminals 70 of the passing control gates 66 of the cells 50 not selected may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the ground selection transistor 80 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.
  • the floating gates/trapping layers 60 are reset to a predetermined initial state, e.g., a positive state as illustrated in Fig. 27, so that each floating gate/trapping layer 60 has a known state prior to performing another shadowing operation.
  • the reset process operates by the mechanism of electron tunneling from the floating gates/trapping layers 60 to the source regions 20, as illustrated in Fig. 27.
  • a substantially neutral voltage is applied to SL terminal 72, a substantially neutral voltage is applied to BL terminal 74.
  • a highly negative voltage is applied to the terminal 70 and thus the control gate 66 of the selected cell 50, a positive voltage is applied to each terminal 70 and passing control gate of the non-selected cells, a positive voltage is applied to the gate of the ground selection transistor, a Atty. Docket: ZENO-OOlWO substantially neutral voltage is applied to the gate of the string selection transistor, and a negative voltage, having a less negative voltage than the negative voltage applied to the selected cell terminal 70, is applied to terminal 76.
  • the reset operation is performed in the direction of the common source (from memory cell transistor 58n) to the bit line (to memory cell transistor 58a), i.e. in the direction of the arrow shown in Fig. 27.
  • the reset operations described herein with regard to NAND strings are performed "n" times.
  • 0 volts is applied to terminal 72
  • about 0 volts is applied to terminal 74
  • about - 12.0 volts is applied to each terminal 70 of a selected cell 50
  • about +3 V is applied to each terminal 70 (and passing control gate 66) of a non-selected cell 50
  • about +3 volts is applied to the gate of the ground selection transistor 80
  • about 0 volts is applied to the gate of the string selection transistor
  • about - 10.0 volts is applied to terminal 76.
  • voltage applied to terminal 72 may be in the range of about 0.0 volts to about +3.0 volts
  • voltage applied to terminal 74 may be in the range of about 0.0 volts to about +3.0 volts
  • voltage applied to terminal 70 of the selected control gate 66 may be in the range of about -12.0 volts to about -20.0 volts
  • voltage applied to the terminals 70 of the passing control gates 66 of the cells 50 not selected may Atty.
  • ZENO-OOl WO be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the string selection transistor 68 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to the gate of the ground selection transistor 80 may be in the range of about +1.0 volts to about +5.0 volts
  • voltage applied to terminal 76 may be in the range of about -4.0 volts to about -12.0 volts.

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  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une mémoire à semi-conducteurs présentant deux modes de fonctionnement (mémoire volatile et mémoire non volatile) et ses procédés de fonctionnement. Une cellule mémoire à semi-conducteurs comprend : une première région incorporée à un premier emplacement dans le substrat et possédant un second type de conductivité; une seconde région incorporée à un second emplacement dans le substrat et possédant le second type de conductivité, de sorte qu'au moins une partie du substrat possédant le premier type de conductivité est située entre le premier et le second emplacement, et fonctionne comme un corps flottant pour stocker des données dans la mémoire volatile; une grille flottante ou une couche de piégeage positionnée entre le premier et le second emplacement et au-dessus d'une surface du substrat et isolée de cette dernière par une couche d'isolation; la grille flottante ou la couche de piégeage étant configurées pour recevoir un transfert de données stockées dans la mémoire volatile et stocker les données sous forme de mémoire non volatile dans la grille flottante ou la couche de piégeage lors d'une interruption d'alimentation de la cellule mémoire; et une grille de commande positionnée au-dessus de la grille flottante ou de la couche de piégeage et une seconde couche d'isolation positionnée entre la grille flottante ou la couche de piégeage et la grille de commande.
PCT/US2007/024544 2006-11-29 2007-11-29 Mémoire à semi-conducteurs à modes volatil et non volatil et son procédé de fonctionnement WO2008136813A2 (fr)

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