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WO2008136813A3 - Semiconductor memory having both volatile and non-volatile functionality and method of operating - Google Patents

Semiconductor memory having both volatile and non-volatile functionality and method of operating Download PDF

Info

Publication number
WO2008136813A3
WO2008136813A3 PCT/US2007/024544 US2007024544W WO2008136813A3 WO 2008136813 A3 WO2008136813 A3 WO 2008136813A3 US 2007024544 W US2007024544 W US 2007024544W WO 2008136813 A3 WO2008136813 A3 WO 2008136813A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile
semiconductor memory
operating
floating gate
functionality
Prior art date
Application number
PCT/US2007/024544
Other languages
French (fr)
Other versions
WO2008136813A2 (en
Inventor
Yuniarto Widjaja
Original Assignee
Yuniarto Widjaja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yuniarto Widjaja filed Critical Yuniarto Widjaja
Publication of WO2008136813A2 publication Critical patent/WO2008136813A2/en
Publication of WO2008136813A3 publication Critical patent/WO2008136813A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/711—Insulated-gate field-effect transistors [IGFET] having floating bodies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a floating gate or trapping layer positioned in between first and second locations and above a surface of the substrate and insulated from the surface by an insulating layer; the floating gate or trapping layer being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gate or trapping layer upon interruption of power to the memory cell.
PCT/US2007/024544 2006-11-29 2007-11-29 Semiconductor memory having both volatile and non-volatile functionality and method of operating WO2008136813A2 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US86177806P 2006-11-29 2006-11-29
US60/861,778 2006-11-29
US98237407P 2007-10-24 2007-10-24
US98238207P 2007-10-24 2007-10-24
US60/982,374 2007-10-24
US60/982,382 2007-10-24

Publications (2)

Publication Number Publication Date
WO2008136813A2 WO2008136813A2 (en) 2008-11-13
WO2008136813A3 true WO2008136813A3 (en) 2008-12-31

Family

ID=39944139

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/024544 WO2008136813A2 (en) 2006-11-29 2007-11-29 Semiconductor memory having both volatile and non-volatile functionality and method of operating

Country Status (1)

Country Link
WO (1) WO2008136813A2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519831A (en) * 1991-06-12 1996-05-21 Intel Corporation Non-volatile disk cache
US20050024968A1 (en) * 2003-07-31 2005-02-03 Brocade Communications Systems, Inc. Apparatus for reducing data corruption in a non-volatile memory
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519831A (en) * 1991-06-12 1996-05-21 Intel Corporation Non-volatile disk cache
US20060125010A1 (en) * 2003-02-10 2006-06-15 Arup Bhattacharyya Methods of forming transistor constructions
US20050024968A1 (en) * 2003-07-31 2005-02-03 Brocade Communications Systems, Inc. Apparatus for reducing data corruption in a non-volatile memory

Also Published As

Publication number Publication date
WO2008136813A2 (en) 2008-11-13

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