[go: up one dir, main page]

WO2009008130A1 - 動作保証システム - Google Patents

動作保証システム Download PDF

Info

Publication number
WO2009008130A1
WO2009008130A1 PCT/JP2008/001686 JP2008001686W WO2009008130A1 WO 2009008130 A1 WO2009008130 A1 WO 2009008130A1 JP 2008001686 W JP2008001686 W JP 2008001686W WO 2009008130 A1 WO2009008130 A1 WO 2009008130A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
input
frequency
cpu
data signal
Prior art date
Application number
PCT/JP2008/001686
Other languages
English (en)
French (fr)
Inventor
Masahiro Takatori
Original Assignee
Panasonic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corporation filed Critical Panasonic Corporation
Priority to US12/668,336 priority Critical patent/US8072824B2/en
Publication of WO2009008130A1 publication Critical patent/WO2009008130A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Dram (AREA)
  • Memory System (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

　動作保証システムは、デコーダ回路、比較回路、ＣＰＵ回路、周波数調整回路およびＤＱ調整回路を含む。比較回路は、デコーダ回路から入力されるテストデータ信号と外部から入力される期待値データ信号とを比較し、デコーダ回路の出力エラーの有無を検出する。ＣＰＵ回路は、周波数調整回路およびＤＱ調整回路を制御することにより、外部メモリに入力されるクロック信号の周波数およびデータ信号の遅延量を種々変化させる。また、ＣＰＵ回路は、それら変化される種々の条件下において比較回路の検出結果を取得する。そして、ＣＰＵ回路は、上記種々の条件と上記出力エラーの有無との関係に基づいて、外部メモリに入力されるクロック信号の適切な周波数を判定する。
PCT/JP2008/001686 2007-07-12 2008-06-27 動作保証システム WO2009008130A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/668,336 US8072824B2 (en) 2007-07-12 2008-06-27 Operation guarantee system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007183667A JP5049065B2 (ja) 2007-07-12 2007-07-12 動作保証システム
JP2007-183667 2007-07-12

Publications (1)

Publication Number Publication Date
WO2009008130A1 true WO2009008130A1 (ja) 2009-01-15

Family

ID=40228324

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/001686 WO2009008130A1 (ja) 2007-07-12 2008-06-27 動作保証システム

Country Status (3)

Country Link
US (1) US8072824B2 (ja)
JP (1) JP5049065B2 (ja)
WO (1) WO2009008130A1 (ja)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8516315B2 (en) 2010-09-03 2013-08-20 Stmicroelectronics International N.V. Testing of non stuck-at faults in memory
PT2432161E (pt) 2010-09-16 2015-11-20 Deutsche Telekom Ag Método de e sistema para medir qualidade de transmissões de fluxo de bits de vídeo e áudio através de uma cadeia de transmissão
JP6058835B2 (ja) * 2016-01-29 2017-01-11 ルネサスエレクトロニクス株式会社 半導体装置
CN111163311B (zh) * 2020-02-13 2022-05-24 维沃移动通信有限公司 一种相位校准方法及电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001160000A (ja) * 1999-12-03 2001-06-12 Nec Kofu Ltd メモリ制御集積回路、メモリカード、メモリ装置、情報処理装置、クロック設定方法、記録媒体
US6370067B1 (en) * 2001-01-25 2002-04-09 Ishoni Networks, Inc. Automatic configuration of delay parameters in a dynamic memory controller
JP2005530297A (ja) * 2002-06-12 2005-10-06 マイクロン　テクノロジー　インコーポレイテッド 遅延回路のための方法および装置
JP2006107352A (ja) * 2004-10-08 2006-04-20 Fujitsu Ltd メモリコントローラ
JP2006189916A (ja) * 2004-12-28 2006-07-20 Matsushita Electric Ind Co Ltd タイミング調整方法及び装置
JP2006338130A (ja) * 2005-05-31 2006-12-14 Fujitsu Ltd メモリ制御方法およびこれを実施する情報処理装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08110872A (ja) 1994-10-11 1996-04-30 Fuji Photo Film Co Ltd コンピュータシステム
JPH08137783A (ja) 1994-11-15 1996-05-31 Canon Inc バスサイクルタイムコントロール回路およびバスサイクル処理方法
JP2001290697A (ja) 2000-04-06 2001-10-19 Hitachi Ltd 情報処理システム
JP2002366421A (ja) 2001-06-07 2002-12-20 Oki Electric Ind Co Ltd メモリ制御回路とメモリ制御方法
JP2005141725A (ja) 2003-10-16 2005-06-02 Pioneer Plasma Display Corp メモリアクセス回路、そのメモリアクセス回路の動作方法およびそのメモリアクセス回路を用いる表示装置
US20050135167A1 (en) 2003-10-16 2005-06-23 Nec Plasma Display Corporation Memory access circuit for adjusting delay of internal clock signal used for memory control
US7298188B2 (en) 2004-04-30 2007-11-20 Fujitsu Limited Timing adjustment circuit and memory controller

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001160000A (ja) * 1999-12-03 2001-06-12 Nec Kofu Ltd メモリ制御集積回路、メモリカード、メモリ装置、情報処理装置、クロック設定方法、記録媒体
US6370067B1 (en) * 2001-01-25 2002-04-09 Ishoni Networks, Inc. Automatic configuration of delay parameters in a dynamic memory controller
JP2005530297A (ja) * 2002-06-12 2005-10-06 マイクロン　テクノロジー　インコーポレイテッド 遅延回路のための方法および装置
JP2006107352A (ja) * 2004-10-08 2006-04-20 Fujitsu Ltd メモリコントローラ
JP2006189916A (ja) * 2004-12-28 2006-07-20 Matsushita Electric Ind Co Ltd タイミング調整方法及び装置
JP2006338130A (ja) * 2005-05-31 2006-12-14 Fujitsu Ltd メモリ制御方法およびこれを実施する情報処理装置

Also Published As

Publication number Publication date
US20100182854A1 (en) 2010-07-22
JP2009020764A (ja) 2009-01-29
US8072824B2 (en) 2011-12-06
JP5049065B2 (ja) 2012-10-17

Similar Documents

Publication Publication Date Title
MX2010001526A (es) Dispositivo de circuito y metodo para medir inestabilidad de reloj.
WO2008141102A3 (en) Systems and methods for providing a clock signal
WO2009079175A3 (en) Self-timed error correcting code evaluation system and method
WO2004095240A3 (en) A method and apparatus for detecting on-die voltage variations
TW200718930A (en) Temperature detecting apparatus
WO2007120957A3 (en) Dynamic timing adjustment in a circuit device
TW200701639A (en) Touch sensor and signal generation method thereof
TW200721673A (en) Semiconductor integrated circuit
US9111599B1 (en) Memory device
JP4852770B2 (ja) 遅延回路のための方法および装置
WO2009008130A1 (ja) 動作保証システム
US20140281643A1 (en) Apparatus and method for detecting clock tampering
US20140204974A1 (en) Temperature sensor and temperature sensing method
US7307895B2 (en) Self test for the phase angle of the data read clock signal DQS
WO2010013464A1 (ja) 試験装置
WO2011081330A3 (ko) 스퀄치 감지 회로
TW200943071A (en) Electronic device for contention detection of bidirectional bus and related method
WO2009063612A1 (ja) シンセサイザ、シンセサイザモジュール、およびこれを用いた受信装置、電子機器
US20080136456A1 (en) Sampling circuit and sampling method thereof
CN109101691B (zh) 一种双倍速率数据传输接口的数据采样方法
US8269535B1 (en) Delay-locked loop and method of using the same
TW200741237A (en) Calibration device, calibration method, test apparatus and test method
WO2008095985A3 (en) A multi-rate tracking circuit
TW200744322A (en) Phase-frequency detector capable of reducing dead-zone range
WO2008117361A1 (ja) 論理シミュレーション方法及び論理シミュレータ

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 08776756

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 12668336

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 08776756

Country of ref document: EP

Kind code of ref document: A1