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WO2013015573A2 - Transistor à effet de champ utilisant de l'oxyde de graphène et son procédé de fabrication - Google Patents

Transistor à effet de champ utilisant de l'oxyde de graphène et son procédé de fabrication Download PDF

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Publication number
WO2013015573A2
WO2013015573A2 PCT/KR2012/005809 KR2012005809W WO2013015573A2 WO 2013015573 A2 WO2013015573 A2 WO 2013015573A2 KR 2012005809 W KR2012005809 W KR 2012005809W WO 2013015573 A2 WO2013015573 A2 WO 2013015573A2
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WO
WIPO (PCT)
Prior art keywords
graphene oxide
effect transistor
thin film
layer
field effect
Prior art date
Application number
PCT/KR2012/005809
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English (en)
Korean (ko)
Other versions
WO2013015573A3 (fr
Inventor
이상욱
강태원
파닌겐나디
Original Assignee
동국대학교 산학협력단
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Publication of WO2013015573A2 publication Critical patent/WO2013015573A2/fr
Publication of WO2013015573A3 publication Critical patent/WO2013015573A3/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
    • C—CHEMISTRY; METALLURGY
    • C01—INORGANIC CHEMISTRY
    • C01B—NON-METALLIC ELEMENTS; COMPOUNDS THEREOF; METALLOIDS OR COMPOUNDS THEREOF NOT COVERED BY SUBCLASS C01C
    • C01B32/00—Carbon; Compounds thereof
    • C01B32/15—Nano-sized carbon materials
    • C01B32/182—Graphene
    • C01B32/194—After-treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates

Definitions

  • the present invention relates to a field effect transistor, and more particularly, the field effect transistor using a conventional silicon material can be fabricated only on a rigid substrate, while the present invention can be fabricated on a flexible substrate, and particularly used as a channel layer.
  • the graphene oxide that has undergone the reduction process is well dispersed in water, and thus can be manufactured as a suspension, and thus relates to a field effect transistor using graphene oxide and a method for manufacturing the thin film using a printing method.
  • RFID Radio Frequency Identification
  • RFID Radio Frequency Identification
  • RFID technology If RFID technology is widely used, the efficient management of production and logistics will be virtuous cycle by the convergence between information and communication technology and manufacturing industry, which will have a positive effect on the economy and the environment and improve convenience in real life such as health management and disaster relief. It is expected to develop technologies such as manufacturing low-cost RFID tags for RFID distribution.
  • the process of producing RFID tags is divided into antenna manufacturing, chip manufacturing, antenna and chip mounting process, and converting process of attaching double-sided tape for convenient use by consumers.
  • a thin film transistor (TFT) constituting a logic circuit In order to manufacture an RFID tag chip using a printing method, first, a thin film transistor (TFT) constituting a logic circuit must be developed.
  • a widely used device for a thin film transistor is a field effect transistor (FET).
  • FETs used in existing industries have used crystalline silicon or amorphous silicon thin films.
  • the silicon thin film can be manufactured only on a rigid substrate such as glass due to the use of equipment such as vacuum deposition equipment and rigidity, so that the mass production of the roll-to-roll method on the flexible plastic substrate is impossible.
  • the first problem to be solved by the present invention is to provide a field effect transistor that can be fabricated on a flexible substrate, a thin film can be produced using a printing method.
  • the second problem to be solved by the present invention is to provide a field effect transistor manufacturing method capable of manufacturing a flexible and inexpensive electronic products by manufacturing a logic circuit by a printing method on a thin plastic substrate.
  • the present invention in order to achieve the first object, a substrate; A gate electrode formed on the substrate; A dielectric layer formed on the gate electrode; A source electrode and a drain electrode formed on the dielectric layer; And a channel layer connecting the source electrode and the drain electrode to provide a field effect transistor including graphene oxide that has undergone a reduction process.
  • the dielectric layer may be formed of a BaTiO 3 layer or a graphene oxide layer.
  • the present invention a substrate; A graphene oxide layer that has undergone a reduction process formed on the substrate; A source electrode and a drain electrode formed on the graphene oxide layer subjected to the reduction process; A dielectric layer formed on the source electrode and the drain electrode; It provides a field effect transistor including a gate electrode formed on the dielectric layer, using a graphene oxide layer subjected to a reduction process connecting the source electrode and the drain electrode as a channel layer.
  • the present invention comprises the steps of producing a graphene oxide suspension using a graphene oxide powder to achieve the second object; Generating a graphene oxide thin film from the graphene oxide suspension; And heating the generated graphene oxide thin film to reduce the graphene oxide thin film, thereby producing graphene oxide that has undergone a reduction process, wherein the graphene oxide that has undergone the reduction process is formed between a source electrode and a drain electrode.
  • a field effect transistor manufacturing method is provided, which is used as a channel layer.
  • ascorbic acid may be added to the graphene oxide suspension.
  • the method may further include oxidizing graphite to produce the graphene oxide powder.
  • the conductivity of the graphene oxide subjected to the reduction process may be controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film.
  • the graphene oxide thin film may be generated from the graphene oxide suspension using inkjet printing or spin coating.
  • the graphene oxide thin film is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing graphene oxide through the reduction process. can do.
  • the field effect transistor using a conventional silicon material can be fabricated only on a rigid substrate, but the present invention can be fabricated on a flexible substrate.
  • the reduced graphene oxide used as a channel layer is dispersed in water. It is possible to manufacture a suspension so that it is possible to produce a thin film using the printing method.
  • a logic circuit is manufactured by a printing method on a thin plastic substrate, flexible and inexpensive electronic products can be manufactured.
  • the charge mobility of the graphene oxide after reduction is currently 200 cm 2 / Vs, but the theoretical charge mobility of graphene reaches 200,000 cm 2 / Vs.
  • the degree of reduction to bring the charge mobility close to the graphene's theory, an ultrafast FET using a graphene oxide thin film as a channel layer can be developed.
  • the semiconductor process can be used to manufacture ultra-high speed devices, and the industrial ripple effect will be great.
  • FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention.
  • FIG. 3 is a flowchart illustrating a method of generating a graphene oxide layer that has undergone a reduction process according to an embodiment of the present invention.
  • Field effect transistor is a substrate; A gate electrode formed on the substrate; A dielectric layer formed on the gate electrode; A source electrode and a drain electrode formed on the dielectric layer; And a graphene oxide having a reduction process as a channel layer connecting the source electrode and the drain electrode.
  • the present invention provides a field effect transistor using a reduced graphene oxide thin film having a high charge mobility (50 cm 2 / Vs or more) and excellent dispersibility in water and printing and high chemical stability as a channel layer. It is the content regarding a manufacturing method.
  • FIG. 1 is a cross-sectional view of a field effect transistor according to an embodiment of the present invention.
  • the field effect transistor includes a substrate 100, a gate electrode 110, a dielectric layer 120, a source electrode 130, a drain electrode 140, and graphene that have undergone a reduction process. It is composed of an oxide layer 150.
  • the substrate 100 may be a thin plastic substrate such as polyester (PET), polycarbonate (PC), polyvinyl chloride (PVC), poly acrylate (PAR), polyimide (PI), paper, or fiber. .
  • PET polyester
  • PC polycarbonate
  • PVC polyvinyl chloride
  • PAR poly acrylate
  • PI polyimide
  • the gate electrode 110, the source electrode 130, and the drain electrode 140 may be formed of any one of gold, silver, copper, nickel, or aluminum powder in an ink or paste state, such as inkjet printing, offset printing, or screen printing. It can be formed using one of the methods. Drying and curing takes place in the range of 100-140 ° C.
  • the dielectric layer 120 may be formed using one of inkjet printing, offset printing, screen printing, or spin coating by preparing BaTiO 3 powder in ink or paste, or preparing graphene oxide powder in suspension. have. Drying and curing takes place in the range of 100-140 ° C.
  • graphene oxide is an insulator, it can be used as a dielectric layer of FETs, but it is limited to use as a channel layer. However, when graphene oxide is reduced to remove oxygen in the thin film, it becomes conductive and can operate as a channel layer of the FET.
  • the graphene oxide layer 150 subjected to the reduction process may be a channel layer between the source electrode 130 and the drain electrode 140.
  • the gate electrode 110 is formed on the substrate 100, the dielectric layer 120 is formed on the gate electrode 110, and two electrodes are formed on the dielectric layer 120.
  • the graphene oxide layer 150 is formed on the source electrode 130 and the drain electrode 140 through the reduction process, and serves as the electrode 130 and the drain electrode 140. 140) Connect the two electrodes.
  • a voltage is applied to the gate electrode 110 to control the opening and closing of the channel layer while applying a voltage to the source electrode and the drain electrode to flow a current.
  • FIG. 2 is a cross-sectional view of a field effect transistor according to another embodiment of the present invention.
  • the graphene oxide layer 150 which has undergone a reduction process is formed on the substrate 100, and two electrodes are formed on the graphene oxide layer 150 which have undergone the reduction process. 130 and the drain electrode 140, and the dielectric layer 120 is formed on the source electrode 130 and the drain electrode 140 to insulate the two electrodes, and then the gate electrode 110 on the dielectric layer 120. To form.
  • the field effect transistor type shown in FIG. 1 is referred to as a bottom-gate type FET because the gate electrode is formed at the bottom of the FET structure, and the field effect transistor type type shown in FIG. It is called FET of -gate type.
  • the shape can be determined in an advantageous manner depending on the fabrication environment and the state of the peripheral elements formed together on the integrated circuit, respectively.
  • FIG. 3 is a flowchart illustrating a method of generating a graphene oxide layer that has undergone a reduction process according to an embodiment of the present invention.
  • step 310 a graphene oxide suspension is generated using the graphene oxide powder.
  • the graphene oxide powder may be produced by oxidizing graphite.
  • ascorbic acid may be added to the graphene oxide suspension.
  • a graphene oxide thin film is formed from the graphene oxide suspension.
  • the graphene oxide thin film may be formed using the method of inkjet printing or spin coating the graphene oxide suspension.
  • the graphene oxide thin film is heated to reduce the graphene oxide thin film.
  • the graphene oxide thin film generated in step 320 is heat-treated in an argon atmosphere at 130 to 140 ° C. for 24 hours to reduce the graphene oxide thin film, thereby producing graphene oxide that has undergone a reduction process.
  • the conductivity of the graphene oxide subjected to the reduction process is controlled by the degree of reduction determined by the temperature or time of heating the graphene oxide thin film. Further, the degree of reduction may be determined according to the gap between the source electrode and the drain electrode of the field effect transistor.
  • the field effect transistor using the graphene oxide having undergone the reduction process may be manufactured. will be.
  • the present invention is a technique for a thin film transistor (TFT).
  • TFT thin film transistor
  • FET field effect transistor
  • Field effect transistors using a graphene oxide layer that has undergone a reduction process have a wide range of applications, such as RFID-Tag, TFT-LCD, and disposable cell phones.

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  • Chemical & Material Sciences (AREA)
  • Organic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Nanotechnology (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Carbon And Carbon Compounds (AREA)

Abstract

Cette invention concerne un transistor à effet de champ (FET) comprenant un oxyde de graphène ayant été soumis à un procédé de réduction, ledit transistor à effet de champ comprenant : un substrat ; une électrode de grille formée sur le substrat ; une couche diélectrique formée sur l'électrode de grille ; une électrode source et une électrode de drain formées sur la couche diélectrique ; et l'oxyde de graphène réduit sous forme de couche de canal reliant l'électrode source à l'électrode de drain. Le transistor à effet de champ selon cette invention peut être fabriqué sur un substrat flexible, contrairement à un FET classique utilisant un matériau silicié qui ne peut être fabriqué que sur un substrat dur. En particulier, l'oxyde de graphène réduit utilisé à titre de couche de canal se disperse bien dans l'eau et peut par conséquent être fabriqué sous la forme d'une suspension, permettant ainsi la formation d'un film mince à l'aide d'un procédé d'impression.
PCT/KR2012/005809 2011-07-22 2012-07-20 Transistor à effet de champ utilisant de l'oxyde de graphène et son procédé de fabrication WO2013015573A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2011-0073292 2011-07-22
KR20110073292 2011-07-22

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WO2013015573A2 true WO2013015573A2 (fr) 2013-01-31
WO2013015573A3 WO2013015573A3 (fr) 2013-03-21

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103531664A (zh) * 2013-10-28 2014-01-22 苏州大学 柔性衬底上制备石墨烯基光电晶体管的方法
US20140291733A1 (en) * 2013-03-28 2014-10-02 Intellectual Discovery Co., Ltd. Strain sensing device using reduced graphene oxide and method of manufacturing the same
WO2018072103A1 (fr) * 2016-10-18 2018-04-26 广东东邦科技有限公司 Structure de tft basée sur un matériau de substrat de carbone quantique de graphène multicouche flexible et procédé de fabrication

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CN103295912B (zh) 2013-05-21 2015-12-02 中国电子科技集团公司第十三研究所 一种基于自对准技术的石墨烯晶体管制造方法
KR101424603B1 (ko) 2013-09-10 2014-08-04 한국과학기술연구원 박막 트랜지스터의 제조 방법
KR101906005B1 (ko) * 2016-11-29 2018-10-10 국민대학교산학협력단 종이기판 상에 제작된 소멸가능 트랜지스터 전자장치 및 그 제조방법
KR102639314B1 (ko) * 2020-04-13 2024-02-21 고려대학교 세종산학협력단 수직 구조 전계효과 트랜지스터 및 그 제조방법

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KR101084975B1 (ko) * 2009-06-19 2011-11-23 한국과학기술원 그래핀 필름 제조방법, 이에 의하여 제조된 그래핀 필름, 이를 포함하는 전극재료
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140291733A1 (en) * 2013-03-28 2014-10-02 Intellectual Discovery Co., Ltd. Strain sensing device using reduced graphene oxide and method of manufacturing the same
US9291513B2 (en) * 2013-03-28 2016-03-22 Intellectual Discovery Co., Ltd. Strain sensing device using reduced graphene oxide and method of manufacturing the same
CN103531664A (zh) * 2013-10-28 2014-01-22 苏州大学 柔性衬底上制备石墨烯基光电晶体管的方法
CN103531664B (zh) * 2013-10-28 2016-08-17 苏州大学 柔性衬底上制备石墨烯基光电晶体管的方法
WO2018072103A1 (fr) * 2016-10-18 2018-04-26 广东东邦科技有限公司 Structure de tft basée sur un matériau de substrat de carbone quantique de graphène multicouche flexible et procédé de fabrication
US11011646B2 (en) 2016-10-18 2021-05-18 Guang Dong Dongbond Technology Co., Ltd. TFT structure based on flexible multi-layer graphene quantum carbon substrate material and method for manufacturing same

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KR101428015B1 (ko) 2014-08-11
KR20130011966A (ko) 2013-01-30
WO2013015573A3 (fr) 2013-03-21

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