WO2013039377A1

WO2013039377A1 - A wrapper circuit capable of reducing latency in operation between interfaced memory controller and memory

Info

Publication number: WO2013039377A1
Application number: PCT/MY2012/000176
Authority: WO
Inventors: Leong Son Wee; Bahisham Bin Jusoh @ Yusoff Suhaimi
Original assignee: Mimos Berhad
Priority date: 2011-09-12
Filing date: 2012-06-29
Publication date: 2013-03-21
Also published as: MY174430A

Abstract

The present invention relates to a wrapper circuit (112) used for interfacing a non- mux ed memory controller (101) and a muxed-memory. Particularly, the wrapper lOcircuit (112) uses timing control select (TCS) input prompting one or more processing circuit to generate a data enable timing control signal (1 10) to permit the select circuit (103) to control the write operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory. The disclosed wrapper circuit (1 12) I Savoid any pre-fix clock cycles which probably contains more clock cycles than the minimum number needed to fulfill the minimum access time therefore the disclosed circuit promotes faster write operation between the interfaced non-muxed memory controller (101) and muxed memory.

Description

A WRAPPER CIRCUIT CAPABLE OF REDUCING LATENCY IN OPERATION BETWEEN INTERFACED MEMORY CONTROLLER AND

MEMORY

5

Field Of Invention

The present invention relates to a wrapper circuit used for interfacing a non-muxed memory controller and a muxed memory. More specifically, the disclosed wrapper circuit is incorporated with a mechanism promote faster read and/or write operation in lObetween the memory controller and memory by reducing number of unnecessary clock cycles between the address phase and data phase.

Background Of The Invention

Wrapper circuit is a type of integrated circuit acting as an interfacing means to permit 15communication in between a non-multiplexed (non-muxed) memory controller and a multiplexed memory. The muxed memory possesses only a single shared port and the address or data is transferred in a time-multiplexed fashion through the single shared port. In contrast, the non-muxed memory controller has distinct address port and data port for sending the address and data. With reduce in pin or port number, the muxed 20memory is relatively smaller in size and being the ideal memory type for manufacturing of handheld electronic devices. Nevertheless, fully shifting to the muxed memory controller platform may take some times to complete considering that conventional non-muxed memory controller has been available in the market for many years and muxed type memory controller with desired features may not be 25available especially with higher pricing compared to non-muxed memory controller. Thus, there exists creation of the wrapper circuit to facilitate communication in between the muxed memory and the non-muxed memory controller. For example, United State patent application no. 7818527 describes development of the wrapper circuit.

30

Apart from the basic interfacing, the duration which data can be read from or written to the muxed memory through the wrapper circuit is another major consideration in wrapper circuit fabrication. This particular concern is due to the fact that different muxed type memories of different manufacturers are set to have varied minimum access time. The duration of minimum access time has to be met before data can be read from or written to the muxed memory. In order to match the varied minimum 5access time of different muxed type memories, the wrapper circuit is generally designed to have fixed clock wait-states longer than the required minimum access time. The additional clock waiting state introduces unnecessary latency to the circuit and slows down the overall performance of the system. Consequently, it is preferred to have a wrapper circuit imparted with a mechanism allowing the clock wait-states to lObe adjustable according to the minimum access time of the muxed memory to improve efficiency of the overall system.

Summary Of The Invention

The present invention aims to provide a wrapper circuit which facilitate interfacing 15and communication in between a non-muxed memory controller and a muxed memory.

Another object of the present invention is to disclose a wrapper circuit incorporated with adjustable clock wait-states. Specifically, the wrapper circuit is able to determine 20minimum access time of the muxed memory and formulate thereof a corresponding number of clocks to fulfill the minimum access time followed by instant write operation to avoid introduction of unnecessary latency to the system.

Further object of the present invention is to provide a method for reducing clock 251atency in write and/or read operation of a computing system that a wrapper circuit is used in the system to allow communication in between a non-muxed memory controller and a muxed memory.

At least one of the preceding objects is met, in whole or in part, by the present 30invention, in which one of the embodiments of the present invention is a wrapper circuit capable of reducing clock latency in between address phase and data phase during write operation of interfaced non-muxed memory controller and muxed memory comprising a select circuit (103) configured to multiplex write data and an address received from the memory controller (101), and configured to output either a selected write data or selected address according to an internal control signal; an input/output buffer (104) configured to receive and provide the selected write data or 5the selected address to the memory, and configured to receive read data from the memory and to pass the read data to the memory controller (101); one or more processing circuit configured to receive control signals from the memory controller (101) to generate the internal control signal; and a timing control circuit configured to control a timing between a selection of the address and a selection of the data, and a lOtiming of control signal for controlling the memory; wherein the one or more processing circuit is configured to generate a timing control select (TCS) input based on minimum access time of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the memory controller (101), and the TCS input (100) prompts the one or more processing circuit to generate a data enable

IStiming control signal (1 10) to permit the select circuit (103) to control the write operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.

20In another embodiment, the disclosed wrapper circuit (112) further comprises a logic circuit gate to implement the internal control signal. The decoded internal control signal is important for instructing other circuits integrated in the wrapper circuit (1 12) to perform various tasks according to the predetermined logic. 5In another embodiment of the present invention, the wrapper circuit (1 12) further comprises a select control circuit for providing a select-control signal to determine the select circuit (103) to multiplex the write data or the address.

Further embodiment of the present invention involves a method for a wrapper circuit 30(112) to reduce latency during address and data phases for a write operation of an interfaced non-muxed memory controller (101) and a muxed-memory comprising the steps of determining minimum access time (Ϊ_ΑΗ) of the muxed-memory; acquiring clock frequency and clock running time of the non-muxed memory controller (101); generating a TCS input (100) based on the determined minimum access time, clock frequency and clock running time by one or more processing circuit in the wrapper circuit (1 12); prompting the one or more processing circuit to generate a data enable 5timing control signal (110) based on the TCS input (100) to permit a select circuit (103) in the wrapper circuit (112) to control the write operation and output data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory. OBrief Description Of The Drawings

Figure 1 is a circuit of one embodiment of the disclosed wrapper circuit;

Figure 2 is a timing diagram illustrating a write operation of a conventional wrapper circuit, with fixed clock numbers for fitting the minimum5 access time, in a muxed memory;

Figure 3 is a timing diagram illustrating the principles of the present invention;

Figure 4 is a timing diagram illustrating a write operation of the disclosed0 wrapper circuit that the write operation is carried out instantly right after the minimum access time is fulfilled;

Figure 5 is a timing diagram illustrating a write operation of the disclosed wrapper circuit that the minimum access time is adjusted to be fulfilled5 with greater number of clocks when the wrapper circuit is running at higher frequency; and

Figure 6 is a flowchart showing one embodiment of the method carried out in the disclosed wrapper circuit to avoid circuit latency.

0 Detailed Description Of The Invention

One skilled in the art will readily appreciate that the present invention is well adapted to carry out the objects and obtain the ends and advantages mentioned, as well as those inherent therein. The embodiment describes herein is not intended as limitations 5on the scope of the invention.

One of the embodiments of the present invention, as shown in figure 1 , includes a wrapper circuit (1 12) capable of reducing clock latency in between address phase and data phase during write operation of interfaced non-muxed memory controller (101) lOand muxed memory comprising a select circuit (103) configured to multiplex write data or an address received from the memory controller (101 ), and configured to output either a selected write data or selected address according to an internal control signal; an input/output buffer (104) configured to receive and provide the selected write data or the selected address to the memory, and configured to receive read data

15from the memory and to pass the read data to the memory controller (101); one or more processing circuit configured to receive control signals from the memory controller (101) to generate the internal control signal; and a timing control circuit configured to control a timing between a selection of the address and a selection of the data, and a timing of control signal for controlling the memory; wherein the one or

20more processing circuit is configured to generate a TCS input (100) based on minimum access time (Ϊ_ΑΗ) of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the memory controller (101), and the TCS input (100) prompts the one or more processing circuit to generate a data enable timing control signal (110) to permit the select circuit (103) to control the write

25 operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.

It is important to be noted that the wrapper circuit (1 12) of the present invention 30receives the address or write data from the non-muxed memory controller (101) in the non-multiplexed fashion and transfer the received address or write data as time- multiplexed signal to the shared port (1 1 1) of the muxed memory. On the other hand, the wrapper circuit (112) acquires the read data from the memory followed by delivering the read data to the memory controller (101) via the read data port (READDATA) on the memory controller (101). Accordingly, the wrapper circuit (112) of the present invention accepts various signals from the non-muxed memory 5controller (101 ) to perform different tasks onto the memory. Preferably, a chip select control signal (ChipSelect) is given to enable selection of a specific memory and the signal is active-low enable signal. An address valid control signal (AVD), an active- low enable signal, for verification on address validity. Particularly, the AVD allows delivery of all addresses when it is active in an asynchronous mode, while the AVD lOonly indicates validity of the address and latches all the addresses at the rising edge of the clock signal in synchronous mode. The address destined the location on the memory where the data can be read or written to. In an exemplary embodiment, the read data from the memory is processed as a unit of 16-bit data, while the write data with the addresses are each 16 bits unit transferred via the shared port (1 11). To

15 synchronize read or write operation in the wrapper circuit (1 12) and the muxed memory, a clock signal (CLOCK) is provided from the non-muxed memory controller (101). Other signals includes write control- signal (WriteEnable) and output control signal (OutEnable) which both are active-low enable signal to control input of write data onto the memory and to control output of read data from the memory

20respectively.

As in setting forth, muxed memory produced from different manufacturers tends to have different minimum access time. To improve compatibility of the wrapper circuit (1 12) towards various muxed memory, prolonged wait-state clock cycle is introduced

25into the conventional wrapper circuit (1 12) to fulfill the different setting On minimum access time. Referring to figure 2, the wait-state clock cycle is fixed to four cycles to meet the minimum access time requirement of the muxed memory in between a address phase and data phase for a write or read operation. Nonetheless, the minimum time access time may only requires two cycles to complete that the additional two

30cycles can be considered as unnecessary latency. Such latency reduces overall performance of the system and the delay becomes more apparent if the wrapper circuit (112) functions at slower frequency. The inventors of the present invention offer a solution to the above mentioned problems by devising a wrapper circuit (1 12) as in the foregoing description. The disclosed wrapper circuit (1 12) is able to generate a TCS input (100), based on minimum access time of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the 5memory controller (101), which permits instant write operation in the memory upon complete of the minimum access time without subjected to unnecessary delay as illustrated in figure 3. A better illustration is shown in figure 4 that the disclosed circuit, with a clock frequency of 100MHz or 10ns per clock cycle period, carries out a write operation on a muxed memory with minimum access time of 7ns. OConsequently, the write data as shown can be validated within a clock cycle for meeting the minimum access time therefore a write operation in the present invention can proceed right after the one clock cycle. For embodiment of wrapper circuit (1 12) running at higher frequency, more clock cycles are required to complete same length of minimum access time. More specifically, as in figure 5, a disclosed wrapper circuit5(112) running at the frequency of 200MHz needs two clock cycles instead of one to complete the minimum access time of 7ns.

According to the preferred embodiment, the disclosed wrapper circuit (1 12) preferably comprises different combined functional circuits. As in setting forth, the0select circuit (103) is configured to multiplex write data or the address received from the memory controller (101), and configured to output either a selected write data or selected address according to an internal control signal. More preferably, the disclosed wrapper circuit (1 12) further comprises a select control circuit for providing the internal control signal to determine the select circuit (103) to multiplex either the5write data or the address. In one exemplary embodiment, the select control circuit or the wrapper circuit (1 12) may be coupled to a logic circuit gate to implement the internal control signal. Besides the internal control signal, the write operation to be performed through the select circuit (103) requires enabled write control signal, chip select control signal and address valid control signal. On the other absence of one of0the enabled write control signal, chip select control signal and address valid control signal shall lead to the select circuit (103) to output the address instead of write data. In one embodiment, the select control circuit may form part of the one or more processing circuit for receiving different mentioned control signal from the non- muxed memory controller (101) and generates a signal compatible to the muxed memory to control different operations in the muxed memory. Preferably, the muxed memory is muxed flash memory.

5

Pursuant to another embodiment, an input/output buffer (104) control circuit is incorporated into the disclosed wrapper circuit (1 12) to cater a control signal to enable the input/output buffer (104) to output the address or data. More preferably, the input/ output buffer (104) control circuit is implemented together with combinational circuit Oand only provides the control signal upon receipt of input like /WriteEnable (109),

/OutE (108), /AVD_OUT (107) and ChipSelect from the non-muxed memory controller (101). Further, the timing control circuit configured to control a timing between a selection of the address and a selection of the data especially the timing to transfer the address, the data or the signals in a multiplexing fashion.

5

The one or more processing circuit in the disclosed circuit is crucial in conducting the process to reduce the wait-state latency by identifying the minimum number of clocks to fulfill the minimum access time of the muxed memory without subjecting the system to prolong wait-state. The control signals from the memory controller (101)0are decoded and used to generate the internal control signal for performing various activities of the interfaced muxed memory. Moreover, the generated a TCS input

(100) based on minimum access time of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the memory controller

(101) is an input used to assist the disclosed wrapper circuit (1 12) to fasten the write 5 operation through reducing the wait-state latency. Preferably, the TCS input (100) prompts the one or more processing circuit to generate the data enable timing control signal (110) (DENBTD) to permit the select circuit (103) to control the write operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access0time of the mu ed-memory. In one exemplary embodiment, a "HIGH" enabled "DENB" and inputted enabled value {00,01 ,10,11 } are available for the TCS input (100), thus providing a control signal that enable data enable timing control (DENBTC) signal to provides control for address/data . A "LOW" enabled control signal in the input/output buffer (104) provides control for read/write data inputted to/ from memory.

5The disclosed wrapper circuit (1 12) may further include timing control enable select pin " TCS[1 :0] " which allows user to select timing enable signal. The inputted enable value from the user to "TCS [1 :0]" signal may further fasten the read/write data from input/output buffer (104) inputted to/from memory. The user selectable function control gives user the latitude to define timing read access control for reducing Olatency.

Another embodiment of the present invention is a method for a wrapper circuit (112), as in the setting forth, to reduce latency during address and data phases for a write operation of an interfaced non-muxed memory controller (101) and a muxed-memory5comprising the steps of determining minimum access time (Ϊ_ΑΗ) of the muxed- memory; acquiring clock frequency and clock running time of the non-muxed memory controller (101); generating a TCS input (100) based on the determined minimum access time, clock frequency and clock running time by one or more processing circuit in the wrapper circuit (1 12); prompting the one or more processing0circuit to generate a data enable timing control signal (1 10) based on the TCS input (100) to permit a select circuit (103) in the wrapper circuit (1 12) to control the write operation and output data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.

5

Preferably, the wrapper circuit (1 12) described in the disclosed method may further comprise a select control circuit for providing a select-control signal to determine the select circuit (103) to multiplex the write data or the address. The select control circuit is responsible in deciding the matter to be transferred through. Further, a logic circuit0gate for decoding the internal control signal is available in the wrapper circuit (1 12) of the disclosed method. The present disclosure includes as contained in the appended claims, as well as that of the foregoing description. Although this invention has bee described in its preferred form with a degree of particularity, it is understood that the present disclosure of the preferred form has been made only by way of example and that numerous changes inthe details of construction and the combination and arrangements of parts may be resorted to without departing from the scope of the invention.

Claims

1. A wrapper circuit (1 12) capable of reducing clock latency in between address phase and data phase during write operation of interfaced non-muxed memory controller (101) and muxed memory comprising

a select circuit (103) configured to multiplex write data or an address received from the memory controller (101), and configured to output either a selected write data or selected address according to an internal control signal;

an input/output buffer (104) configured to receive and provide the selected write data or the selected address to the memory, and configured to receive read data from the memory and to pass the read data to the memory controller (101);

one or more processing circuit configured to receive control signals from the memory controller ( 01) to generate the internal control signal; and

a timing control circuit configured to control a timing between a selection of the address and a selection of the data, and a timing of control signal for controlling the memory;

wherein the one or more processing circuit is configured to generate a TCS input (100) based on minimum access time of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the memory controller (101), and

the timing control select (TCS) input prompts the one or more processing circuit to generate a data enable timing control signal (110) to permit the select circuit (103) to control the write operation and output the data, to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.

2. A wrapper circuit (1 12) of claim 1 further comprising a logic circuit gate to decode the internal control signal. A wrapper circuit (1 12) of claim 1 or 2 further comprising a select control circuit for providing the internal control signal to determine the select circuit (103) to multiplex the write data or the address.

A wrapper circuit (112) of claim 1 , wherein the muxed memory is muxed flash memory.

A method for a wrapper circuit (1 12) to reduce latency during address and data phases for a write operation of an interfaced non-muxed memory controller

(101) and a muxed-memory comprising the steps of

determining minimum access time (Ϊ_ΑΗ) of the muxed-memory;

acquiring clock frequency and clock running time of the non-muxed memory controller (101);

generating a timing control select (TCS) input based on the determined minimum access time, clock frequency and clock running time by one or more processing circuit in the wrapper circuit (1 12);

prompting the one or more processing circuit to generate a data enable timing control signal (1 10) based on the timing control select (TCS) input to permit a select circuit (103) in the wrapper circuit (112) to control the write operation and output data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.

A method of claim 5, wherein the wrapper circuit (1 12) further comprising further comprising a logic circuit gate to decode the internal control signal.

A method of claim 5, wherein the wrapper circuit (112) further comprising a select control circuit for providing a select-control signal the internal control signal to determine the select circuit (103) to multiplex the write data or the address.