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WO2013039377A1 - Circuit d'encapsulation capable de réduire la latence de fonctionnement entre un contrôleur de mémoire interfacé et une mémoire - Google Patents

Circuit d'encapsulation capable de réduire la latence de fonctionnement entre un contrôleur de mémoire interfacé et une mémoire Download PDF

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Publication number
WO2013039377A1
WO2013039377A1 PCT/MY2012/000176 MY2012000176W WO2013039377A1 WO 2013039377 A1 WO2013039377 A1 WO 2013039377A1 MY 2012000176 W MY2012000176 W MY 2012000176W WO 2013039377 A1 WO2013039377 A1 WO 2013039377A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
circuit
muxed
data
select
Prior art date
Application number
PCT/MY2012/000176
Other languages
English (en)
Inventor
Leong Son Wee
Bahisham Bin Jusoh @ Yusoff Suhaimi
Original Assignee
Mimos Berhad
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Berhad filed Critical Mimos Berhad
Publication of WO2013039377A1 publication Critical patent/WO2013039377A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Definitions

  • the present invention relates to a wrapper circuit used for interfacing a non-muxed memory controller and a muxed memory. More specifically, the disclosed wrapper circuit is incorporated with a mechanism promote faster read and/or write operation in lObetween the memory controller and memory by reducing number of unnecessary clock cycles between the address phase and data phase.
  • Wrapper circuit is a type of integrated circuit acting as an interfacing means to permit 15communication in between a non-multiplexed (non-muxed) memory controller and a multiplexed memory.
  • the muxed memory possesses only a single shared port and the address or data is transferred in a time-multiplexed fashion through the single shared port.
  • the non-muxed memory controller has distinct address port and data port for sending the address and data.
  • the muxed 20memory is relatively smaller in size and being the ideal memory type for manufacturing of handheld electronic devices.
  • the duration which data can be read from or written to the muxed memory through the wrapper circuit is another major consideration in wrapper circuit fabrication. This particular concern is due to the fact that different muxed type memories of different manufacturers are set to have varied minimum access time. The duration of minimum access time has to be met before data can be read from or written to the muxed memory.
  • the wrapper circuit is generally designed to have fixed clock wait-states longer than the required minimum access time. The additional clock waiting state introduces unnecessary latency to the circuit and slows down the overall performance of the system. Consequently, it is preferred to have a wrapper circuit imparted with a mechanism allowing the clock wait-states to lObe adjustable according to the minimum access time of the muxed memory to improve efficiency of the overall system.
  • the present invention aims to provide a wrapper circuit which facilitate interfacing 15and communication in between a non-muxed memory controller and a muxed memory.
  • Another object of the present invention is to disclose a wrapper circuit incorporated with adjustable clock wait-states.
  • the wrapper circuit is able to determine 20minimum access time of the muxed memory and formulate thereof a corresponding number of clocks to fulfill the minimum access time followed by instant write operation to avoid introduction of unnecessary latency to the system.
  • Further object of the present invention is to provide a method for reducing clock 251atency in write and/or read operation of a computing system that a wrapper circuit is used in the system to allow communication in between a non-muxed memory controller and a muxed memory.
  • one of the embodiments of the present invention is a wrapper circuit capable of reducing clock latency in between address phase and data phase during write operation of interfaced non-muxed memory controller and muxed memory
  • a select circuit (103) configured to multiplex write data and an address received from the memory controller (101), and configured to output either a selected write data or selected address according to an internal control signal
  • an input/output buffer (104) configured to receive and provide the selected write data or 5the selected address to the memory, and configured to receive read data from the memory and to pass the read data to the memory controller (101);
  • one or more processing circuit configured to receive control signals from the memory controller (101) to generate the internal control signal; and a timing control circuit configured to control a timing between a selection of the address and a selection of the data, and a lOtiming of control signal for controlling the memory; wherein the one or more processing circuit is configured to generate a timing control select (TCS)
  • TCS timing control select
  • IStiming control signal (1 10) to permit the select circuit (103) to control the write operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.
  • the disclosed wrapper circuit (112) further comprises a logic circuit gate to implement the internal control signal.
  • the decoded internal control signal is important for instructing other circuits integrated in the wrapper circuit (1 12) to perform various tasks according to the predetermined logic.
  • the wrapper circuit (1 12) further comprises a select control circuit for providing a select-control signal to determine the select circuit (103) to multiplex the write data or the address.
  • Figure 1 is a circuit of one embodiment of the disclosed wrapper circuit
  • Figure 2 is a timing diagram illustrating a write operation of a conventional wrapper circuit, with fixed clock numbers for fitting the minimum5 access time, in a muxed memory;
  • FIG. 3 is a timing diagram illustrating the principles of the present invention.
  • Figure 4 is a timing diagram illustrating a write operation of the disclosed0 wrapper circuit that the write operation is carried out instantly right after the minimum access time is fulfilled;
  • Figure 5 is a timing diagram illustrating a write operation of the disclosed wrapper circuit that the minimum access time is adjusted to be fulfilled5 with greater number of clocks when the wrapper circuit is running at higher frequency;
  • Figure 6 is a flowchart showing one embodiment of the method carried out in the disclosed wrapper circuit to avoid circuit latency.
  • One of the embodiments of the present invention includes a wrapper circuit (1 12) capable of reducing clock latency in between address phase and data phase during write operation of interfaced non-muxed memory controller (101) lOand muxed memory comprising a select circuit (103) configured to multiplex write data or an address received from the memory controller (101 ), and configured to output either a selected write data or selected address according to an internal control signal; an input/output buffer (104) configured to receive and provide the selected write data or the selected address to the memory, and configured to receive read data
  • the memory controller (101); one or more processing circuit configured to receive control signals from the memory controller (101) to generate the internal control signal; and a timing control circuit configured to control a timing between a selection of the address and a selection of the data, and a timing of control signal for controlling the memory; wherein the one or
  • TCS input (100) based on minimum access time ( ⁇ ⁇ ⁇ ) of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the memory controller (101), and the TCS input (100) prompts the one or more processing circuit to generate a data enable timing control signal (110) to permit the select circuit (103) to control the write
  • the wrapper circuit (1 12) of the present invention 30receives the address or write data from the non-muxed memory controller (101) in the non-multiplexed fashion and transfer the received address or write data as time- multiplexed signal to the shared port (1 1 1) of the muxed memory.
  • the wrapper circuit (112) acquires the read data from the memory followed by delivering the read data to the memory controller (101) via the read data port (READDATA) on the memory controller (101).
  • the wrapper circuit (112) of the present invention accepts various signals from the non-muxed memory 5controller (101 ) to perform different tasks onto the memory.
  • a chip select control signal (ChipSelect) is given to enable selection of a specific memory and the signal is active-low enable signal.
  • An address valid control signal (AVD), an active- low enable signal, for verification on address validity.
  • the AVD allows delivery of all addresses when it is active in an asynchronous mode, while the AVD lOonly indicates validity of the address and latches all the addresses at the rising edge of the clock signal in synchronous mode.
  • the read data from the memory is processed as a unit of 16-bit data, while the write data with the addresses are each 16 bits unit transferred via the shared port (1 11).
  • a clock signal (CLOCK) is provided from the non-muxed memory controller (101).
  • Other signals includes write control- signal (WriteEnable) and output control signal (OutEnable) which both are active-low enable signal to control input of write data onto the memory and to control output of read data from the memory
  • the wait-state clock cycle is fixed to four cycles to meet the minimum access time requirement of the muxed memory in between a address phase and data phase for a write or read operation. Nonetheless, the minimum time access time may only requires two cycles to complete that the additional two
  • the inventors of the present invention offer a solution to the above mentioned problems by devising a wrapper circuit (1 12) as in the foregoing description.
  • the disclosed wrapper circuit (1 12) is able to generate a TCS input (100), based on minimum access time of the muxed memory and clock frequency of the memory controller (101) as well as clock running time of the 5memory controller (101), which permits instant write operation in the memory upon complete of the minimum access time without subjected to unnecessary delay as illustrated in figure 3.
  • FIG 4 A better illustration is shown in figure 4 that the disclosed circuit, with a clock frequency of 100MHz or 10ns per clock cycle period, carries out a write operation on a muxed memory with minimum access time of 7ns. OConsequently, the write data as shown can be validated within a clock cycle for meeting the minimum access time therefore a write operation in the present invention can proceed right after the one clock cycle.
  • wrapper circuit (1 12) running at higher frequency more clock cycles are required to complete same length of minimum access time. More specifically, as in figure 5, a disclosed wrapper circuit5(112) running at the frequency of 200MHz needs two clock cycles instead of one to complete the minimum access time of 7ns.
  • the disclosed wrapper circuit (1 12) preferably comprises different combined functional circuits.
  • the0select circuit (103) is configured to multiplex write data or the address received from the memory controller (101), and configured to output either a selected write data or selected address according to an internal control signal.
  • the disclosed wrapper circuit (1 12) further comprises a select control circuit for providing the internal control signal to determine the select circuit (103) to multiplex either the5write data or the address.
  • the select control circuit or the wrapper circuit (1 12) may be coupled to a logic circuit gate to implement the internal control signal. Besides the internal control signal, the write operation to be performed through the select circuit (103) requires enabled write control signal, chip select control signal and address valid control signal.
  • the select control circuit may form part of the one or more processing circuit for receiving different mentioned control signal from the non- muxed memory controller (101) and generates a signal compatible to the muxed memory to control different operations in the muxed memory.
  • the muxed memory is muxed flash memory.
  • an input/output buffer (104) control circuit is incorporated into the disclosed wrapper circuit (1 12) to cater a control signal to enable the input/output buffer (104) to output the address or data. More preferably, the input/ output buffer (104) control circuit is implemented together with combinational circuit Oand only provides the control signal upon receipt of input like /WriteEnable (109),
  • the timing control circuit configured to control a timing between a selection of the address and a selection of the data especially the timing to transfer the address, the data or the signals in a multiplexing fashion.
  • the one or more processing circuit in the disclosed circuit is crucial in conducting the process to reduce the wait-state latency by identifying the minimum number of clocks to fulfill the minimum access time of the muxed memory without subjecting the system to prolong wait-state.
  • the control signals from the memory controller (101)0 are decoded and used to generate the internal control signal for performing various activities of the interfaced muxed memory. Moreover, the generated a TCS input
  • the TCS input (100) prompts the one or more processing circuit to generate the data enable timing control signal (110) (DENBTD) to permit the select circuit (103) to control the write operation and output the data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access0time of the mu ed-memory.
  • DEBTD data enable timing control signal
  • a "HIGH” enabled “DENB” and inputted enabled value ⁇ 00,01 ,10,11 ⁇ are available for the TCS input (100), thus providing a control signal that enable data enable timing control (DENBTC) signal to provides control for address/data .
  • a "LOW" enabled control signal in the input/output buffer (104) provides control for read/write data inputted to/ from memory.
  • the disclosed wrapper circuit (1 12) may further include timing control enable select pin " TCS[1 :0] " which allows user to select timing enable signal.
  • the inputted enable value from the user to "TCS [1 :0]” signal may further fasten the read/write data from input/output buffer (104) inputted to/from memory.
  • the user selectable function control gives user the latitude to define timing read access control for reducing Olatency.
  • Another embodiment of the present invention is a method for a wrapper circuit (112), as in the setting forth, to reduce latency during address and data phases for a write operation of an interfaced non-muxed memory controller (101) and a muxed-memory5comprising the steps of determining minimum access time ( ⁇ ⁇ ⁇ ) of the muxed- memory; acquiring clock frequency and clock running time of the non-muxed memory controller (101); generating a TCS input (100) based on the determined minimum access time, clock frequency and clock running time by one or more processing circuit in the wrapper circuit (1 12); prompting the one or more processing0circuit to generate a data enable timing control signal (1 10) based on the TCS input (100) to permit a select circuit (103) in the wrapper circuit (1 12) to control the write operation and output data to the muxed memory right after end of the address phase and a minimum number of clocks required to complete the minimum access time of the muxed-memory.
  • the wrapper circuit (1 12) described in the disclosed method may further comprise a select control circuit for providing a select-control signal to determine the select circuit (103) to multiplex the write data or the address.
  • the select control circuit is responsible in deciding the matter to be transferred through.
  • a logic circuit0gate for decoding the internal control signal is available in the wrapper circuit (1 12) of the disclosed method.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)

Abstract

La présente invention concerne un circuit d'encapsulation (112) utilisé pour interfacer un contrôleur de mémoire non multiplexée (101) et une mémoire multiplexée. En particulier, le circuit d'encapsulation (112) utilise une entrée de sélection de commande de synchronisation (TCS) invitant un ou plusieurs circuits de traitement de données à générer un signal de commande de synchronisation de validation de données (110) pour permettre au circuit de sélection (103) de commander l'opération d'écriture et transmettre les données à la mémoire multiplexée juste après la fin de la phase d'adressage et un nombre minimum d'horloges nécessaires pour atteindre le temps d'accès minimum de la mémoire multiplexée. Le circuit d'encapsulation divulgué (112) permet d'éviter les cycles d'horloge fixés de manière préalable qui contiennent probablement un plus grand nombre de cycles d'horloge que le nombre minimum requis pour obtenir le temps d'accès minimum. Par conséquent, le circuit décrit ici favorise une opération d'écriture plus rapide entre le contrôleur de mémoire non multiplexée interfacé (101) et la mémoire multiplexée.
PCT/MY2012/000176 2011-09-12 2012-06-29 Circuit d'encapsulation capable de réduire la latence de fonctionnement entre un contrôleur de mémoire interfacé et une mémoire WO2013039377A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2011004287 2011-09-12
MYPI2011004287A MY174430A (en) 2011-09-12 2011-09-12 A wrapper circuit capable of reducing latency in operation between interfaced memory controller and memory

Publications (1)

Publication Number Publication Date
WO2013039377A1 true WO2013039377A1 (fr) 2013-03-21

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WO (1) WO2013039377A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030110363A1 (en) * 1998-10-06 2003-06-12 Jean-Marc Bachot Method and apparatus for accessing a memory core multiple times in a single clock cycle
US7818527B2 (en) 2005-08-11 2010-10-19 Samsung Electronics Co., Ltd. Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030110363A1 (en) * 1998-10-06 2003-06-12 Jean-Marc Bachot Method and apparatus for accessing a memory core multiple times in a single clock cycle
US7818527B2 (en) 2005-08-11 2010-10-19 Samsung Electronics Co., Ltd. Wrapper circuit and method for interfacing between non-muxed type memory controller and muxed type memory

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