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WO2018140842A2 - Transistor à mode hybride à grille isolée - Google Patents

Transistor à mode hybride à grille isolée Download PDF

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Publication number
WO2018140842A2
WO2018140842A2 PCT/US2018/015626 US2018015626W WO2018140842A2 WO 2018140842 A2 WO2018140842 A2 WO 2018140842A2 US 2018015626 W US2018015626 W US 2018015626W WO 2018140842 A2 WO2018140842 A2 WO 2018140842A2
Authority
WO
WIPO (PCT)
Prior art keywords
trench
ighmt
semiconductor
semiconductor layer
schottky junction
Prior art date
Application number
PCT/US2018/015626
Other languages
English (en)
Other versions
WO2018140842A3 (fr
Inventor
Hongjian Wu
Original Assignee
Hongjian Wu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongjian Wu filed Critical Hongjian Wu
Publication of WO2018140842A2 publication Critical patent/WO2018140842A2/fr
Publication of WO2018140842A3 publication Critical patent/WO2018140842A3/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Definitions

  • This invention relates to power semiconductor devices.
  • Power semiconductor devices are widely used to control the flow of current to electronic devices such as motors and inductive heating ovens, typically VDMOS field effect transistors and insulate gate bipolar transistor (IGBT).
  • IGBT the gate voltage turns the device on by inducing a conducting MOS channel to flow the base current of the Bipolar Transistor.
  • a MOSFET that include three layers of alternating conductivity type semiconductors combines a Bipolar Transistor including three alternating layers, with two layers from each device sharing dual functions, i.e., Body and Drain layer of MOSFET become Collector and Base of the Bipolar Transistor.
  • an IGBT needs four layers of alternating conductivity type semiconductors to work.
  • a four-layer device is effectively a thyristor.
  • a thyristor acts exclusively as a bi-stable switch, conducting once the gate being triggered, and continuing to conduct as long as the voltage across the device is not removed or reversed.
  • Latch-up When an IGBT turns into Thyristor mode, called Latch-up, it lost the ability to switch off and becomes malfunction.
  • IGBT designers made years efforts to make an advanced design that is less prone to latch-up in the use, However, a total !atch ⁇ up free IGBT type of device is always in desire.
  • an Insulate Gate Hybrid Mode Transistor (IGHMT) power semiconductor device in accordance with this invention is formed in a
  • a heavy doping layer is formed to serve as Cathode layer.
  • the paired first and second trenches are provided along the surface of the Cathode layer and separated by mesas having parallel sides.
  • a MOS gate electrode is formed via an insulating film coating on the trench sidewall.
  • the Schottky junction is provided on the upper sidewall and connected to Cathode electrode via the metal trench filling that is electrically isolated from the substrate by an insulating film provided on the lower part of the sidewalls.
  • a metal Cathode electrode is connecting the Cathode layer and Schottky junction in the second trench.
  • a second conductivity type Anode layer is forming a PN junction. The metal Anode electrode is provided to electrically connect to the Anode layer.
  • the substrate is generally doped with N-type dopant uniformly except the Cathode layer at top surface of the substrate having a n+-type heavy doping level; the Anode layer is doped with P-type dopant.
  • the poly silicon which forms the gate electrode is doped with P-type dopant.
  • the depletion retreats and accumulation layer forms along the walls of the first trench.
  • the majority carrier current can flow from the Anode layer to the Cathode and minority carrier current can be collected by reverse biased Schottky junction by charge balancing principle.
  • the gate is biased zero or negative, the depletion come back and pinch off the majority carrier current path and cease minority carrier current flow altogether.
  • FIG. 1 is a schematic cross-sectional view of the main part of the semiconductor device IGHMT;
  • FIG. 2 is schematic cross-sectional views of main parts illustrating the first part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 3 is schematic cross-sectional views of main parts illustrating the second part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 4 is schematic cross-sectional views of main parts illustrating the third part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 5 is schematic cross-sectional views of main parts illustrating the fourth part of manufacturing process steps of the semiconductor device IGHMT;
  • FIG. 6 is schematic cross-sectional views of main parts illustrating the fifth part of manufacturing process steps of the semiconductor device IGHMT.
  • FIG. 7 is schematic cross-sectional views of main parts illustrating the sixth part of manufacturing process steps of the semiconductor device IGHMT.
  • the Insulate Gate Hybrid Mode Transistor in accordance with this invention includes a first semiconductor layer of a first conductivity type as substrate, a second semiconductor layer of same conductivity type but having higher doping level provided on the first surface of the substrate, a third semiconductor layer of the second conductivity type on the second surface of the substrate, a first trench having MOS control electrode provided via an insulating film, an second trench having Schottky junction on upper portion sidewalls and insulating film on lower portion sidewalls, a Cathode electrode connecting to second semiconductor layer as well as Schottky junctions in the second trench, a Anode electrode connecting to the third semiconductor layer.
  • the first and second trenches are paired and separated by mesas having parallel sides and
  • FIG. 1 is a schematic cross-sectional view of a main part of the IGHMT according to the invention and illustrates as a device cell portion of the IGHMT.
  • Cathode layer 1 is a heavy dosed n+-type semiconductor layer
  • the substrate 3 is lightly dosed n-type semiconductor substrate or the epitaxial layer.
  • a plurality of trenches 10 is provided penetrating the surface of the Cathode layer 1 into the substrate or epitaxial layer 3 and periodically in a direction substantially parallel to the major surface of the substrate or the epitaxial layer.
  • the trenches 10 are built into two types: the first trench having MOS electrode 12 and the second trench having sidewall Schottky junction 15. These two trenches are paired and separated by mesas 20 in shapes having parallel sides such as rectangle, hexagon, stripe, etc.
  • the first trench is provided with gate insulting film 6 and gate electrode 12.
  • the second trench is provided with a sidewall Schottky barrier junction that is formed by a high work function barrier material 15 in contacting with the upper portion of the mesa sidewall.
  • An insulating film 6 is provided on the bottom portion of the second trench to prevent Cathode electrode metal 16 from contacting the substrate or the epitaxial layer 3.
  • the P-type Anode layer 18 is provided on the lower surface of the substrate by conventional doping technique, or as a top portion of the epitaxial substrate to the epitaxial layer.
  • the metal layer forms Cathode electrode 16 also fills the second trench to make the electrical connection to Schottky barrier junction.
  • a multi-layer metal Anode electrode 19 is formed on the surface of the Anode layer 18 by sputtering or CVD method.
  • a main component of the substrate 3 and the mesa 20 is n-type silicon (Si), for example.
  • a main component of the Anode layer 18 is p-type silicon (Si) from epitaxial substrate or conventional doping, for example.
  • a main component of the gate electrode 12 is P-type doped polysilicon (poly-Si), for example.
  • a main component of the Cathode electrode 16 is aluminum (Al), for example.
  • a main component of the Anode electrode 19 is multi-layer metal (Al-Ti-Ni-Ag), for example.
  • a main component of the insulating film 6 is silicon oxide (Si0 2 ), for example.
  • a main component of the Schottky barrier material 15 is Platinum (Pt), for example.
  • FIGs. 2 to 8 are schematic cross-sectional views of main parts for illustrating manufacturing processes of the semiconductor device.
  • the n-type substrate for example, semiconductor wafer-like
  • an n+-type Cathode layer 1 is formed on the upper surface of the substrate 3 by impurity diffusion (for example, ion implantation Arsenic followed by thermal anneal).
  • a plurality of trenches 10 is formed by using the anisotropic etching (for example, Reactive Ion Etching, RIE) or the like after a etching mask layer such as silicon oxide film, a resist and the like (not shown) is selectively formed on the surface of the Cathode layer 1 .
  • the insulating film 6 is formed in the trenchI O by using the thermal oxidation method, the chemical vapor deposition (CVD) method or the like.
  • a sacrificial film 30 (for example, Silicon Nitride or the like) is deposited in the trench 12 before a etch mask layer such as a resist and the like is selectively formed on the first type trenches.
  • the sacrificial film 30 is selectively etched away in second type trench, but leave insulating film 6 not etched.
  • polysilicon (poly-Si) is deposited and filled in the gate trench.
  • the formation method of polysilicon is, for example, the CVD method.
  • polysilicon is etched back.
  • the polisilicon gate electrode 12 is formed in the second type trench, as shown in FIG. 4.
  • the sacrificial film 30 is globally etched away including those filled in the first type trenches.
  • a silicon nitride film 14 is deposited by CVD method and thereafter an anisotropic nitride etch is performed to remove most of the film 14 except on the sidewalls of the first type trenches, as shown in FIG. 5.
  • a thermal oxidation is performed.
  • a silicon oxide layer 6 is thus formed over the surface exposed, including the bottom of first type trenches, except the sidewall surfaces covered by silicon nitride film 14.
  • an isotropic etching of Nitride such as phosphoric acid submerging method, is performed to strip off silicon nitride film 14 on the sidewall of first type trenches.
  • a Schottky junction is thus formed on the sidewall in first type trenches by Schottky film 15 contacting the semiconductor mesa sidewall.
  • the backside of the substrate is reduced by chemical-mechanical method to reach a pre-determined total thickness.
  • An ion implantation or other method is introducing the second conductivity type impurities into semiconductor layer 3 and followed by a heating anneal.
  • the Anode electrode 19 is then formed by sputter or CVD deposition method as shown in FIG.8.
  • the epitaxial technique can be used to grow n-type EPI layer on top of the P-type substrate initially as the substrate 3 then follow the same process steps described above to reach stage in FIG. 7.
  • the EPI substrate will be treated as Anode layer 18 and Anode electrode 19 is then formed by sputter or CVD deposition method as shown in FIG.8
  • the IGHMT shown in FIG. 1 includes a mesa (patterned area 20) having trench sidewall Schottky junction 15 on one side and trench MOS gate 12 on the opposite side.
  • the Schottky junction 15 and the MOS gate 12 are arranged face to face forming a mesa Schottky junction field effect transistor (mSJFET).
  • mSJFET mesa Schottky junction field effect transistor
  • the on-state of the SJFET can be achieved by applying a voltage to the MOS gate 12.
  • This gate voltage is to induce a majority carrier accumulation layer on the trench sidewall facing the gate electrode.
  • the gate voltage needs to be high enough to attract enough majority carriers out of the depletion region to reverse depletion into accumulation in surface layer.
  • This gate voltage is then the threshold voltage of the IGHMT. This represents the on-state of mSJFET.
  • a positive voltage applies to Anode electrode 19 with respect to Cathode providing a forward bias for the PN junction (Layer 18 and 3) but reverse biases for the Schottky junction.
  • the mesa With zero or negative gate voltage, the mesa is fully depleted and the mSJFET is off so that IGHMT is in its forward blocking status.
  • the accumulation layer With the applying of a gate voltage higher than the threshold voltage, the accumulation layer is established and provides the conducting path for the majority carrier current which is driven by the forward biased PN junction.
  • the forward biased PN junction also drives minority carriers into substrate 3. The minority carriers are subsequently drawn to the reverse biased Schottky junction for charge balance principle and collected by Cathode electrode 16. If the mSJFET is turned off, the majority carrier current in mSJFET will be cut off and the minority carrier current would also stop to flow due to the same principle.
  • IGHMT Similar to an enhance mode MOS transistor the forward conducting of IGHMT will enter the saturation zone at any given gate voltage which is higher than the threshold voltage of IGHMT, where the Anode current will be maintained at a steady level not affected by the changing the Anode-Cathode voltage. This is due to that increasing of Anode voltage will result in increasing PN junction forward current but at same time the Schottky junction reverse bias is enhanced and result in diminishing the current flowing through the accumulation layer. A stalemate will be reached as the field potential established by majority current flow through the resistance of the accumulation layer cancels depletion field potential.
  • a properly chosen Schottky barrier height (Schottky material's work function) is essential to make the IGHMT work. Ideally the mesa is fully depleted even with the Schottky junction is zero biased. This is accomplished by choosing the right mesa width, picking the right Schottky barrier material and MOS electrode material. For example, Platinum is used as Schottky barrier material, P-type polysilicon is used as MOS electrode material.

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  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un transistor à mode hybride à grille isolée (IGHMT) comprenant un substrat ayant un premier type de conductivité ayant une couche supérieure fortement dopée ayant le même type de conductivité sur sa première surface ; une jonction PN formée par une couche inférieure ayant un second type de conductivité disposée sur la seconde surface du substrat ; une pluralité de sillons qui pénètrent dans la surface de la couche supérieure fortement dopée et s'étendent sur une profondeur prédéterminée dans le substrat séparé par les mesas ayant des côtés parallèles. Dans un côté du mesa, la jonction Schottky de paroi latérale est formée sur la partie supérieure du premier sillon tandis que, dans le côté opposé du mesa, l'électrode de commande MOS est formée dans le second sillon. L'électrode de cathode est connectée électriquement à une jonction Schottky dans le premier sillon et une couche supérieure fortement dopée. L'électrode d'anode est connectée électriquement à la surface de la couche inférieure.
PCT/US2018/015626 2017-01-30 2018-01-28 Transistor à mode hybride à grille isolée WO2018140842A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762499558P 2017-01-30 2017-01-30
US62/499,558 2017-01-30

Publications (2)

Publication Number Publication Date
WO2018140842A2 true WO2018140842A2 (fr) 2018-08-02
WO2018140842A3 WO2018140842A3 (fr) 2018-09-27

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Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3216743B2 (ja) * 1993-04-22 2001-10-09 富士電機株式会社 トランジスタ用保護ダイオード
JP3618517B2 (ja) * 1997-06-18 2005-02-09 三菱電機株式会社 半導体装置およびその製造方法
US7157785B2 (en) * 2003-08-29 2007-01-02 Fuji Electric Device Technology Co., Ltd. Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices
US7737522B2 (en) * 2005-02-11 2010-06-15 Alpha & Omega Semiconductor, Ltd. Trench junction barrier controlled Schottky device with top and bottom doped regions for enhancing forward current in a vertical direction
US7285822B2 (en) * 2005-02-11 2007-10-23 Alpha & Omega Semiconductor, Inc. Power MOS device
US9356017B1 (en) * 2015-02-05 2016-05-31 Infineon Technologies Austria Ag Switch circuit and semiconductor device

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WO2018140842A3 (fr) 2018-09-27

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