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WO2018140842A3 - Transistor à mode hybride à grille isolée - Google Patents

Transistor à mode hybride à grille isolée Download PDF

Info

Publication number
WO2018140842A3
WO2018140842A3 PCT/US2018/015626 US2018015626W WO2018140842A3 WO 2018140842 A3 WO2018140842 A3 WO 2018140842A3 US 2018015626 W US2018015626 W US 2018015626W WO 2018140842 A3 WO2018140842 A3 WO 2018140842A3
Authority
WO
WIPO (PCT)
Prior art keywords
trench
conductivity type
substrate
top layer
hybrid mode
Prior art date
Application number
PCT/US2018/015626
Other languages
English (en)
Other versions
WO2018140842A2 (fr
Inventor
Hongjian Wu
Original Assignee
Hongjian Wu
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hongjian Wu filed Critical Hongjian Wu
Publication of WO2018140842A2 publication Critical patent/WO2018140842A2/fr
Publication of WO2018140842A3 publication Critical patent/WO2018140842A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un transistor à mode hybride à grille isolée (IGHMT) comprenant un substrat ayant un premier type de conductivité ayant une couche supérieure fortement dopée ayant le même type de conductivité sur sa première surface ; une jonction PN formée par une couche inférieure ayant un second type de conductivité disposée sur la seconde surface du substrat ; une pluralité de sillons qui pénètrent dans la surface de la couche supérieure fortement dopée et s'étendent sur une profondeur prédéterminée dans le substrat séparé par les mesas ayant des côtés parallèles. Dans un côté du mesa, la jonction Schottky de paroi latérale est formée sur la partie supérieure du premier sillon tandis que, dans le côté opposé du mesa, l'électrode de commande MOS est formée dans le second sillon. L'électrode de cathode est connectée électriquement à une jonction Schottky dans le premier sillon et une couche supérieure fortement dopée. L'électrode d'anode est connectée électriquement à la surface de la couche inférieure.
PCT/US2018/015626 2017-01-30 2018-01-28 Transistor à mode hybride à grille isolée WO2018140842A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762499558P 2017-01-30 2017-01-30
US62/499,558 2017-01-30

Publications (2)

Publication Number Publication Date
WO2018140842A2 WO2018140842A2 (fr) 2018-08-02
WO2018140842A3 true WO2018140842A3 (fr) 2018-09-27

Family

ID=62978008

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2018/015626 WO2018140842A2 (fr) 2017-01-30 2018-01-28 Transistor à mode hybride à grille isolée

Country Status (1)

Country Link
WO (1) WO2018140842A2 (fr)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561313A (en) * 1993-04-22 1996-10-01 Fuji Electric Co., Ltd. Protective diode for transistor
US20030057482A1 (en) * 1997-06-18 2003-03-27 Masana Harada Semiconductor device and method for manufacturing thereof
US20050082640A1 (en) * 2003-08-29 2005-04-21 Manabu Takei Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices
US20060180855A1 (en) * 2005-02-11 2006-08-17 Alpha And Omega Semiconductor, Inc. Power MOS device
US20070034901A1 (en) * 2005-02-11 2007-02-15 Alpha & Omega Semiconductor, Ltd Trench junction barrier controlled Schottky
US9356017B1 (en) * 2015-02-05 2016-05-31 Infineon Technologies Austria Ag Switch circuit and semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5561313A (en) * 1993-04-22 1996-10-01 Fuji Electric Co., Ltd. Protective diode for transistor
US20030057482A1 (en) * 1997-06-18 2003-03-27 Masana Harada Semiconductor device and method for manufacturing thereof
US20050082640A1 (en) * 2003-08-29 2005-04-21 Manabu Takei Semiconductor device, the method of manufacturing the same, and two-way switching device using the semiconductor devices
US20060180855A1 (en) * 2005-02-11 2006-08-17 Alpha And Omega Semiconductor, Inc. Power MOS device
US20070034901A1 (en) * 2005-02-11 2007-02-15 Alpha & Omega Semiconductor, Ltd Trench junction barrier controlled Schottky
US9356017B1 (en) * 2015-02-05 2016-05-31 Infineon Technologies Austria Ag Switch circuit and semiconductor device

Also Published As

Publication number Publication date
WO2018140842A2 (fr) 2018-08-02

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