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WO2018141292A1 - Procédé et dispositif de traitement de données - Google Patents

Procédé et dispositif de traitement de données Download PDF

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Publication number
WO2018141292A1
WO2018141292A1 PCT/CN2018/075290 CN2018075290W WO2018141292A1 WO 2018141292 A1 WO2018141292 A1 WO 2018141292A1 CN 2018075290 W CN2018075290 W CN 2018075290W WO 2018141292 A1 WO2018141292 A1 WO 2018141292A1
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WIPO (PCT)
Prior art keywords
sequence
bit sequence
vector
bit
output bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/075290
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English (en)
Chinese (zh)
Inventor
马亮
郑晨
曾歆
魏岳军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority claimed from CN201710127438.XA external-priority patent/CN108400838B/zh
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP18748349.0A priority Critical patent/EP3573270B1/fr
Publication of WO2018141292A1 publication Critical patent/WO2018141292A1/fr
Priority to US16/531,956 priority patent/US11133832B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0067—Rate matching
    • H04L1/0068—Rate matching by puncturing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving

Definitions

  • the present application relates to the field of wireless communications, and in particular, to a data processing method and device.
  • a quasi cycle low density parity check code (QC-LDPC) is a type of linear block coding with a sparse check matrix. Because QC-LDPC not only has good performance close to the Shannon limit, but also has the characteristics of flexible structure and low decoding complexity, it can be widely used in various communication systems.
  • the application provides a data processing method and device to achieve rate matching of sequences generated by LDPC coding.
  • an embodiment of the present invention provides a data processing method, including: acquiring a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a code block generated by a transport block or a transport block after code block segmentation. Encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; saving all or at least a portion of the first encoded bit sequence to a circular buffer; storing the bit from the circular buffer The first output bit sequence is taken out.
  • acquiring the first bit sequence to be processed includes: acquiring a transport block; generating, according to the transport block, N bit sequences including the first bit sequence to be processed, where N is greater than 0 Integer.
  • the method further includes interleaving the first sequence of output bits.
  • the method further includes: generating a vector sequence based on the first output bit sequence, the vector sequence including Q vectors of the first output bit sequence, each of the first The vector of output bit sequences includes at least one bit of the first output bit sequence, wherein Q is a positive integer; the vector sequence is interleaved.
  • the vector sequence further comprises a vector generated based on the second output bit sequence; each vector of the second output bit sequence comprising at least one bit of the second output bit sequence.
  • interleaving the vector sequence includes interleaving the vectors contained in the vector sequence.
  • the interleaving the vector sequence includes performing inter-sub-interleaving on each sub-vector sequence included in the vector sequence to obtain M inter-subsequence sub-sequences, where the vector sequence Included in the sequence of M sub-vectors, the number of vectors included in each of the sub-vector sequences is a positive integer multiple of a vector included in a time-domain symbol in a channel for transmitting the transport block within a transmission time interval; M interleaved subsequences.
  • an embodiment of the present invention provides a data processing method, including: acquiring a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a code block generated by a transport block or a transport block after code block segmentation. Encoding the first to-be-processed bit sequence to obtain a first coded bit sequence; performing bit-rearrangement on the first coded bit sequence to obtain a first rearranged bit sequence; or all or all of the first rearranged bit sequence At least a portion of the bits are saved to a circular buffer; a first output bit sequence is fetched from the saved bits in the circular buffer.
  • performing bit rearrangement on the first encoded bit sequence includes at least one operation of: changing a position of the first subsequence in the first encoded bit sequence, the first subsequence The length is a positive integer multiple of the spreading factor; or, the second subsequence in the first encoded bit sequence is deleted, and the length of the second subsequence is a positive integer multiple of the spreading factor.
  • the first coded bit sequence is bit-rearranged to obtain a first rearranged bit sequence, including: the second sub-sequence includes at least one information bit; or the first sub-sequence includes At least one check bit.
  • performing bit rearrangement on the first encoded bit sequence includes: obtaining a punctured sequence and a redundant interleaving sequence, wherein the punctured sequence is a sequence obtained by puncturing the information bit sequence
  • the redundant interleaving sequence is a sequence obtained by performing bit rearrangement on the first redundant sequence; cascading the punctured sequence, the redundant interleaving sequence, and the second redundant sequence, thereby obtaining a bit first rearranged bit sequence;
  • the information bit sequence is composed of information bits included in the first to-be-processed bit sequence, and the first redundant bit sequence is generated by encoding a first to-be-processed bit sequence using a core matrix of an LDPC check matrix.
  • the remaining bits are constructed, and the second redundant sequence is composed of redundant bits generated by encoding the first to-be-processed bit sequence using the spreading matrix of the LDPC check matrix.
  • performing bit rearrangement on the first redundant sequence includes: rearranging the subsequences included in the first redundant sequence according to the selected interleaving pattern, wherein each subsequence is included in the core matrix A column of check bits is formed by redundant bits generated by encoding the information bit sequence.
  • the embodiment of the present invention provides a data processing device, which has the function of implementing the data processing method in each embodiment of the first aspect.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the data processing device includes: an acquiring unit, configured to acquire a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a block generated after the code block is split. a coding unit, configured to: encode a first to-be-processed bit sequence to obtain a first encoded bit sequence; and a saving unit, configured to save all or at least part of the first encoded bit sequence to a circular buffer; a unit for extracting a first output bit sequence from the circular buffer.
  • the acquiring unit includes: an obtaining subunit for acquiring a transport block, and a generating subunit, configured to generate, according to the transport block, a N including the first to-be-processed bit sequence a sequence of bits, N being an integer greater than zero.
  • the device further includes: a first interleaving unit, configured to interleave the first output bit sequence.
  • the device further includes: a second interleaving unit, configured to generate a vector sequence based on the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence And each of said first output bit sequence vectors includes at least one bit of said first output bit sequence, wherein Q is a positive integer; said vector sequence is interleaved.
  • a second interleaving unit configured to generate a vector sequence based on the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence And each of said first output bit sequence vectors includes at least one bit of said first output bit sequence, wherein Q is a positive integer; said vector sequence is interleaved.
  • the vector sequence further comprises a vector generated based on the second output bit sequence; each vector of the second output bit sequence comprising at least one bit of the second output bit sequence.
  • the second interleaving unit is specifically configured to interleave vectors included in the vector sequence.
  • the second interleaving unit is specifically configured to perform intra-sub-interleaving on each sub-vector sequence included in the vector sequence to obtain M inter-subsequence sub-sequences, where the vector The sequence includes M sub-vector sequences, and the number of vectors included in each of the sub-vector sequences is a positive integer multiple of a vector included in a time-domain symbol in a channel for transmitting the transport block within one transmission time interval; M interleaved subsequences are described.
  • the embodiment of the present invention provides a data processing device, which has the function of implementing the data processing method in each embodiment of the second aspect.
  • the functions may be implemented by hardware or by corresponding software implemented by hardware.
  • the hardware or software includes one or more modules corresponding to the functions described above.
  • the data processing device includes: an acquiring unit, configured to acquire a first to-be-processed bit sequence, where the first to-be-processed bit sequence is generated after a transport block or a transport block is code-blocked. a code block, configured to encode the first to-be-processed bit sequence to obtain a first coded bit sequence, and a rearrangement unit to perform bit-rearrangement on the first coded bit sequence to obtain a first rearranged bit a sequence; a saving unit, configured to save all or at least part of the first reordered bit sequence to a circular buffer; and an output unit, configured to extract the first output bit sequence from the saved bits in the circular buffer .
  • an acquiring unit configured to acquire a first to-be-processed bit sequence, where the first to-be-processed bit sequence is generated after a transport block or a transport block is code-blocked.
  • a code block configured to encode the first to-be-processed bit sequence to obtain a first coded bit sequence
  • the rearrangement unit is specifically configured to change a position of the first sub-sequence in the first encoded bit sequence, where the length of the first sub-sequence is a positive integer multiple of the spreading factor; Or deleting a second subsequence in the first encoded bit sequence, the length of the second subsequence being a positive integer multiple of the spreading factor.
  • the second subsequence includes at least one information bit; or the first subsequence includes at least one parity bit.
  • the rearrangement unit is specifically configured to obtain a post-punch sequence and a redundant interleaving sequence, where the post-punch sequence is a sequence obtained by puncturing the information bit sequence; the redundant interleaving sequence a sequence obtained by performing bit rearrangement on the first redundant sequence; cascading the punctured sequence, the redundant interleaving sequence, and the second redundant sequence, thereby obtaining a bit first rearranged bit sequence; wherein the information bit sequence Forming, by the information bits included in the first to-be-processed bit sequence, the first redundant bit sequence is composed of redundant bits generated by encoding a first to-be-processed bit sequence using a core matrix of an LDPC check matrix, The two redundant sequences are composed of redundant bits generated by encoding the first to-be-processed bit sequence using an spreading matrix of the LDPC check matrix.
  • the rearrangement unit is further configured to rearrange sub-sequences included in the first redundant sequence according to the selected interleaving pattern, wherein each sub-sequence is represented by a column of check bits in the core matrix.
  • the redundant bits formed by encoding the information bit sequence are constructed.
  • an embodiment of the present invention further provides a data processing device, including: a processor, a memory, and a transceiver; the processor may execute a program or an instruction stored in the memory, thereby implementing the first Aspects and the data processing method of various implementations of the second aspect.
  • an embodiment of the present invention provides a storage medium, where the computer storage medium may store a program, and when the program is executed, the first aspect and the part of the second aspect provided by the embodiment of the present invention may be implemented. Or all steps.
  • the data processing method and device provided by the embodiments of the present invention can implement rate matching of sequences generated by LDPC coding.
  • FIG. 1 is a schematic flow chart of an embodiment of a data processing method according to the present application.
  • FIG. 2 is a schematic flowchart of another embodiment of a data processing method according to the present application.
  • FIG. 3 is a schematic flowchart of another embodiment of a data processing method according to the present application.
  • FIG. 4 is a schematic flowchart of another embodiment of a data processing method according to the present application.
  • FIG. 5 is a schematic flowchart diagram of another embodiment of a data processing method according to the present application.
  • FIG. 6 is a schematic structural diagram of an embodiment of a data processing device according to the present application.
  • FIG. 7 is a schematic structural diagram of an embodiment of a data processing device according to the present application.
  • FIG. 8 is a schematic structural diagram of an embodiment of a data processing device according to the present application.
  • FIG. 9 is a schematic structural diagram of a system for transmitting data processing systems for uplinks according to the present application.
  • FIG. 10 is another schematic structural diagram of a system for transmitting a data processing system for uplink in the present application.
  • FIG. 11 is another schematic structural diagram of a system for transmitting data processing systems for uplinks according to the present application.
  • FIG. 12 is a schematic structural diagram of a receiving side data processing system system for an uplink according to the present application.
  • FIG. 13 is another schematic structural diagram of a receiving side data processing system system for an uplink according to the present application.
  • FIG. 14 is another schematic structural diagram of a receiving side data processing system system for an uplink according to the present application.
  • 15 is a schematic structural diagram of a system for transmitting data on a downlink side of the present application.
  • 16 is another schematic structural diagram of a system for transmitting data on a downlink side of the present application.
  • 17 is another schematic structural diagram of a system for transmitting data on a downlink side of the present application.
  • FIG. 18 is a schematic structural diagram of a receiving side data processing system system for a downlink according to the present application.
  • FIG. 19 is another schematic structural diagram of a receiving side data processing system system for a downlink according to the present application.
  • FIG. 20 is another schematic structural diagram of a receiving side data processing system system for a downlink according to the present application.
  • FIG. 1 a flow chart of an embodiment of a data processing method of the present application is shown.
  • step 101 the data processing device acquires a transport block.
  • the data processing device may first acquire data to be transmitted, and generate a transport block (TB) corresponding to the data to be transmitted.
  • the length of the transport block may be a predetermined value.
  • the data processing device may add check information to the data to be transmitted, thereby obtaining a transport block. If the check information is already included in the data to be transmitted, the data processing device may directly use the acquired data to be transmitted as a transport block. For example, if the data to be transmitted does not include the check information, the data processing device may attach a corresponding cyclical redundancy check (CRC) check bit after the data to be transmitted, thereby obtaining a transport block.
  • CRC cyclical redundancy check
  • Step 102 Generate N bit sequences based on the transport block.
  • the transport block can be directly used as the first pending bit sequence. If the length of the transport block is greater than the data length that the encoder can encode each time, after acquiring the transport block, the data processing device can generate N bit sequences based on the transport block. Wherein, the length of each of the bit sequences may also be a predetermined value. Wherein, the value of N is a positive integer, and the length of the data block may be less than or equal to the length that the encoder can encode each time. When the value of N is greater than 1, each data block may be of a predetermined length. In general, the length of the data block, the length of the bit sequence, and the value of N can all be preset by the wireless communication system.
  • the data processing device may perform data block (CB) segmentation on the transport block according to a preset parameter and a split mode, and the data block may also be called a code block, thereby obtaining N data blocks.
  • CB data block
  • the data processing device may directly use each of the data blocks obtained by the segmentation as a bit sequence; or, after each of the data blocks, a corresponding CRC check bit may be attached, and then A data block to which a CRC check bit is attached is used as a bit sequence, thereby obtaining N bit sequences. It is also possible to divide the data blocks into groups, and attach corresponding CRC check bits after each group of data blocks.
  • a set of data blocks may include a plurality of data blocks, which may also be referred to as a code block group, and may transmit feedback according to a code block group when transmitting.
  • Step 103 Encode the first to-be-processed bit sequence to obtain a first encoded bit sequence.
  • the first to-be-processed bit sequence may be any one of the N bit sequences.
  • the data processing device may perform LDPC encoding on the first to-be-processed bit sequence to obtain a first encoded bit sequence.
  • the LDPC check matrix may be obtained by the data processing device based on the base matrix or saved by the data processing device, or obtained from other devices. The specific process of encoding the first to-be-processed bit sequence by using the LDPC check matrix will not be repeated here.
  • Step 104 Save all or at least part of the first encoded bit sequence to a circular buffer.
  • the data processing device performs rate matching on the first encoded bit sequence.
  • the data processing device may perform rate matching on the first encoded bit sequence using a circular buffer to generate a first output bit sequence.
  • the data processing device may first determine the size N CB of the data processing device circular buffer based on the processing capabilities of the receiving device. If the size of the circular buffer is greater than or equal to the length of the first encoded bit sequence, the first encoded bit sequence may be directly saved to the circular buffer if the circular buffer is smaller than the first encoded bit sequence Then, after deleting the portion of the bit sequence larger than N CB after the first encoding, the remaining portion is placed in the virtual cache.
  • the N CB value is determined differently depending on the application scenario.
  • the maximum transport block size supported by the soft buffer of the receiving device is calculated according to the decoding capability of the receiving device (transport) Block size) is N IR , and the number of data blocks at this time is C, then
  • the value of N IR receiving apparatus according to the different decoding capabilities preset by the system may have a plurality of different levels.
  • the first encoded bit sequence size in the data processing device is K W
  • the lowest LDPC mother code rate supported by the receiving device is R t
  • the current to be transmitted The transport block size information bit size is K IR, send , and the number of data blocks at this time is C
  • the formula can be expressed as: or If the receiving device is not limited to the transport block buffer and the circular buffer of each code block is limited, then the formula can be expressed as:
  • N CB min(K W , N CB , t ), where the value of N CB,t is preset by the system according to the decoding capability of the receiving device, and may have multiple different levels.
  • the circular buffer in the data processing device can be used to save all or part of the bits in the first encoded bit sequence in step 103, so that rate matching can be performed.
  • Step 105 Extract a first output bit sequence from the circular buffer.
  • the data processing device may extract a bit segment of a predetermined length from a selected starting position in the circular buffer, thereby obtaining a first output.
  • Bit sequence The selected starting location may be a redundancy version starting location in the virtual cache, and the predetermined length may be a redundancy version length indicated by system control information.
  • the header may be returned to the loop buffer until the bit segment is The length reaches the predetermined length, resulting in output bit segments e 0 , e 1 , ..., e E-1 , where E represents the length of the output bit segment.
  • the value can be directly preset by the system or calculated according to the preset formula. Assume that the block lengths of the redundancy versions RV 0 , RV 1 , ..., RV j are respectively The number of redundancy versions currently transmitted is j, then the equivalent code rate of the first output bit sequence can be expressed as:
  • steps from 103 to 105 are only described by taking the value of N as 1, for example, a bit sequence to be processed is taken as an example. If the value of N is greater than 1, the bit sequence to be processed is When there is more than one, the data processing device may respectively generate the output bit sequence corresponding to each bit sequence to be processed in the manner shown in steps 103 to 105.
  • the data processing device may generate an output bit sequence corresponding to each bit sequence to be processed in parallel, or may generate an output bit sequence corresponding to each bit sequence to be processed one by one in a serial manner.
  • the data processing device may further perform bit rearrangement on the first encoded bit sequence to obtain a first rearranged bit sequence, and then save all or at least part of the second bit sequence to the circular buffer.
  • step 104 can also be replaced by the following steps 106 to 107:
  • Step 106 Perform bit rearrangement on the first encoded bit sequence to obtain a first rearranged bit sequence.
  • the data processing device may perform bit rearrangement on the first encoded bit sequence by using a bit rearrangement method, thereby obtaining a bit first rearranged bit sequence.
  • the performing the bit rearrangement on the first encoded bit sequence includes at least one operation of: changing a position of the first subsequence in the first encoded bit sequence, where the length of the first subsequence is a spreading factor A positive integer multiple; or, deleting the second subsequence in the first encoded bit sequence, the length of the second subsequence being a positive integer multiple of the spreading factor. That is, the first rearranged bit sequence is obtained by changing the position of the first subsequence in the first encoded bit sequence, or the first rearranged bit sequence is the second of deleting the first encoded bit sequence. Subsequence obtained.
  • the first encoded bit sequence L is sequentially leveld by the information bit sequence L 0 , the first redundant sequence L 1 and the second redundant sequence L 2 .
  • L 0 is composed of information bits included in the first to-be-processed bit sequence
  • L 1 is composed of redundant bits generated by encoding the first to-be-processed bit sequence using a core matrix of the LDPC check matrix
  • L 2 is composed of The redundancy matrix generated by encoding the first to-be-processed bit sequence is constructed using an extension matrix of the LDPC parity check matrix.
  • the core matrix refers to a matrix in which the check portion of the LDPC check matrix includes at least a complete double-diagonal or lower triangular structure
  • the extended matrix refers to other than the core matrix in the LDPC check matrix. matrix.
  • performing bit rearrangement on the first encoded bit sequence may include the following steps:
  • the data processing apparatus may be made to punch L 0, L 0 will be deleted in one or more information bits, the puncturing resulting sequence L '0. Number of information bits may be deleted as an integer multiple spreading factors, these may be removed as a second information bit sequence, such as L 3.
  • the data processing device may also change the position of the sub-sequence of L 1, to generate a redundancy interleaving sequence L '1.
  • the data processing apparatus may sequentially cascaded L '0, L' 1 and L 2, thereby obtaining a first rearranged bit sequence L ';
  • the data processing device may also be sequentially cascaded L '0, L' 1, L 2 and L 3 are perforated by a sequence of bits to be punctured bits configured to obtain bits of the first bit sequence rearranged L '. It should be noted here that the present application does not perform the puncturing of the data processing device L 0 and the order in which the data processing device performs bit rearrangement on L 1 .
  • the data processing device When L 0 of the puncturing, the data processing device first uses the predetermined puncturing rule, puncturing of L 0.
  • the sequence formed by the bits remaining after puncturing L 0 is the post-punch sequence L' 0 ; and the sequence formed by the punctured bits contiguously is the punctured bit sequence L 3 .
  • the data processing apparatus in accordance with the selected interleaving pattern of the sub-sequence comprises a first sequence of redundancy rearrangement, wherein each sub-sequence consists of a core matrix of the first parity bit to be processed
  • the bit sequence is composed of redundant bits generated by encoding.
  • the data processing device may first determine an interleaving pattern corresponding to the core matrix; then perform column rearranging on the core matrix by using the interleaving pattern; and then interpolate according to each column in the core matrix.
  • the order in the front matrix is arranged for the subsequences corresponding to the columns in the core matrix to obtain L' 1 .
  • Each of the sub-sequences is composed of redundant bits generated by encoding a first to-be-processed bit sequence using a column of parity bits of the core matrix.
  • the subsequence corresponding to a column in the core matrix refers to a sequence composed of redundant bits generated by encoding the first to-be-processed bit sequence using the column check bits in the column.
  • the data processing device may cascade the k b +1 subsequence, the k b + 2 subsequence and the k b subsequence in sequence.
  • the k b sub-sequence is composed of redundant bits generated by encoding the first to-be-processed bit sequence using the k- th column parity of the core matrix, and the k b +1 sub-sequence is obtained by using the k b of the core matrix.
  • the +1 column check bit is formed by the redundant bits generated by encoding the first bit sequence to be processed, and the k b + 2 subsequence is performed on the first output bit sequence by using the k b + 2 column check bits of the core matrix.
  • the coding consists of a redundant bit structure that encodes the first to-be-processed bit sequence.
  • the data processing device can cascade the k b +3 subsequence, the k b +1 subsequence, k b +2 subsequence and k b subsequence.
  • the k b sub-sequence is composed of redundant bits generated by encoding the first to-be-processed bit sequence using the k- th column parity of the core matrix, and the k b +1 sub-sequence is obtained by using the k b of the core matrix.
  • the +1 column check bit is composed of redundant bits generated by encoding the first to-be-processed bit sequence, and the k b + 2 sub-sequence is used by using the k b + 2 column check bit of the core matrix to the first to-be-processed bit sequence
  • the redundant bits formed by the encoding are constructed, and the k b +3 subsequence is composed of redundant bits generated by encoding the first to-be-processed bit sequence using the k b + 3 column parity bits of the core matrix.
  • the possible interleaving patterns also include:
  • the pattern after interleaving can be,
  • the pattern after interleaving can be,
  • L 1 in the sequence corresponding to the sequence number is even preferred that all of the puncturing sequences, or preferentially selects all odd numbered sequences of puncturing.
  • Step 107 Save all or at least part of the first rearranged bit sequence to a circular buffer.
  • the bit sequence may be directly saved to a circular buffer, if the circular buffer is smaller than the first rearranged bit sequence, then The remaining portion may be placed in the virtual cache after the portion of the first rearranged bit sequence greater than N CB is deleted.
  • the manner of determining the value of N CB can be referred to the foregoing, and is not described herein.
  • the first coded bit sequence is bit-rearranged, and when the first output bit sequence is generated, the punctured bits are preferentially discarded, or the order of selecting the first redundant sequence is changed, so as to avoid hitting the wrong one.
  • the hole sequence selects the encoded bit sequence, thereby improving the decoding performance of the LDPC code.
  • the first encoded bit sequence may be bit rearranged in other manners.
  • the circular buffer in the data processing device can also be used to save all or part of the bits in the first reordered bit sequence in step 106 so that rate matching can be performed.
  • steps 106 to 107 are only described by one encoded bit sequence. If the encoded bit sequence is multiple, the methods shown in steps 106 to 107 and step 105 may be used to generate and An output bit sequence corresponding to each encoded bit sequence.
  • the data processing device After the output bit sequence is generated, the data processing device also needs to interleave the output bit sequence to facilitate gain during signal transmission.
  • the data processing device may perform intra-sequence interleaving on each output bit segment, or may interleave between two or more output bit segments.
  • the inter-bit interleaving may further include frequency domain interleaving or channel interleaving.
  • bit sequence is sometimes referred to as a bit segment
  • bit subsequence generally refers to a subset of a bit sequence.
  • the bit subsequence, the bit sequence, and the bit segment are all formally composed of one or more bits. Interleaving a bit sequence, or a bit subsequence, or a bit segment is performed at a bit granularity.
  • FIG. 3 it is a schematic flowchart of an embodiment of an interleaving method according to the present application.
  • step 301 an intra-sequence interlace matrix is determined.
  • the data processing device may first determine an intra-sequence interleaving matrix.
  • the number of columns of the interleaving matrix in the sequence is The number of rows is E is the length of the first output bit sequence. usually, Can be a predetermined value, and Can be satisfied The minimum value.
  • the numbers of the columns in the interleaving matrix in the sequence are from left to right. Each row in the interleaving matrix in the sequence is numbered sequentially from top to bottom.
  • Step 302 Generate a first sequence to be interleaved.
  • the data processing device In addition to determining the interleaving matrix within the sequence, the data processing device also needs to generate a first sequence to be interleaved.
  • the data processing device can Add dummy bits before the first output bit sequence to generate a first sequence to be interleaved
  • the data processing device can directly use the first output bit sequence as the first to-be-interleaved sequence.
  • the first sequence to be interleaved is a sequence generated by adding N D elements having a value of ⁇ NULL> at the front end of the first output bit sequence;
  • the first output bit sequence is the first sequence to be interleaved.
  • Step 303 Fill the first to-be-interleaved sequence into the intra-sequence interleave matrix in a row-by-row manner.
  • the data processing device may fill the first inter-interleaved sequence into the intra-sequence interleave matrix in a row-by-row manner.
  • Step 304 Perform column switching on the intra-sequence interleaving matrix filled in the first to-be-interleaved sequence, thereby generating a column switching matrix.
  • the data processing device may perform an intra-sequence interleaving matrix filled with the first to-be-interleaved sequence according to a preset column exchange pattern. Column exchange is performed to generate a column exchange matrix.
  • the column exchange pattern can be obtained by looking up a table.
  • the column exchange pattern can be expressed as ⁇ p(j)> j ⁇ 0,1,...,N-1 ⁇ , where p(j) is the original column number of the jth column after the column exchange.
  • Table 1 is an example of an interlaced pattern:
  • the matrix before the column exchange can be expressed as:
  • the matrix after column exchange can be expressed as:
  • Step 305 reading all the matrix elements in the column switching matrix in column order.
  • the output bit sequences of the respective code blocks in the at least one code block group may be cascaded.
  • the interleaved input bit sequence for example, is input to bit sequence A, and then interleaved with the input bit sequence A.
  • Each code block in a code block group passes through steps 103-105 or through steps 103, 106, 107 and 105 to obtain corresponding output bit sequences, which may also be referred to as a set of output bit sequences.
  • each output bit sequence is obtained from a circular buffer, where the circular buffer is used to save all or part of the bits obtained by encoding the code block corresponding to each of the output bit sequences, or the circular buffer is used. And storing all or part of the bits obtained after the code block corresponding to each of the output bit sequences is encoded and rearranged.
  • it can be:
  • A01 Acquire an input bit sequence A, wherein the input bit sequence A can be obtained based on at least one set of output bit sequences, each set of output bit sequences includes at least one output bit sequence, and each output bit sequence in each set of output bit sequences is based on Generated by each code block in the same code block group;
  • A02 Interleaving the input bit sequence A.
  • code blocks 0 to 4 belong to code block group 0
  • code blocks 5 to 9 belong to code block group 1
  • code blocks. 10 to 14 belong to code block group 2.
  • the input bit sequence A can be obtained by cascading the output bit sequences of the code blocks in the code block group 0, that is, the output bit sequences corresponding to the code blocks 0 to 4 are cascaded.
  • the input bit sequence A can be obtained by cascading the output bit sequence of each code block in the code block groups 1 and 2, that is, the code block
  • the output bit sequences corresponding to 5 to 14 are obtained by cascading.
  • FIG. 4 it is a schematic flowchart of another embodiment of the interleaving method of the present application.
  • step 401 a vector sequence is generated.
  • the vector sequence is composed of at least one vector, the vector sequence including at least a vector generated based on the first output bit sequence.
  • the vector generated based on the first output bit sequence is Q, where Q is a positive integer.
  • Each of the vectors generated based on the first output bit sequence includes at least one bit of the first output bit sequence, and the bits included in each vector may not overlap each other.
  • Each vector may contain a predetermined number of bits, number of bits contained in the vector may be a modulation order mapped layers and Q m N L product Q m ⁇ N L.
  • a vector sequence is sometimes referred to as a vector segment.
  • a sub-vector sequence generally refers to a subset of a vector sequence, and sometimes a sub-vector sequence is also referred to as a vector segment.
  • Vector sequences, vector segments, sub-vector sequences, and vector segments are all formed by one or more vectors. Each vector includes one or more bits.
  • Vector sequences, vector segments, sub-vector sequences, and vector segments are interleaved in a vector-based granularity.
  • each vector contains 4 bits
  • the number of vectors generated based on the first output bit sequence is 4, and each of the vectors includes the number The four bits in an output bit sequence, the bits contained in each vector are combined to form the first output bit sequence.
  • the generated vector may also include the generated vector based on the second output bit sequence.
  • a vector of each of said second output bit sequences includes at least one bit of said second output bit sequence.
  • the data processing device may first acquire a second sequence of bits to be processed.
  • the second to-be-processed bit sequence may be a transport block different from the first to-be-processed sequence; or, when the first to-be-processed sequence is the N-bits In one of the sequences, the second transmission bit may be another one of the N bit sequences different from the first to-be-processed sequence.
  • the data processing device may encode the second to-be-processed bit sequence to obtain a second encoded bit sequence; and then save all or at least part of the second encoded bit sequence to Cycling the buffer; and then extracting the second output bit sequence from the circular buffer.
  • the generation process of the second output bit sequence is similar to the process of generating the first output bit sequence, and will not be described herein.
  • the second output bit sequence may be one or more.
  • the second output bit sequence may be N-1, and each second output bit sequence may correspond to a to-be-processed bit sequence other than the first to-be-processed bit sequence.
  • the manner in which the vector is generated based on the second output bit sequence is the same as the manner in which the vector is generated based on the first bit, and will not be described herein.
  • the vector sequence when the transport block downlink data, may only include a vector generated based on the N output bit sequences; and when the transport block is uplink data, the vector sequence may further include The vector generated by the information required by the road signaling.
  • a vector generated based on the N output bit sequences may be represented as a first vector subsequence g 0 , g 1 , . . . , g H′-1 , where H′ represents for The total number of vectors generated by the output bit sequence.
  • the associated channel signaling may be represented as a second vector subsequence
  • the data processing device can have g 0 , g 1 ,..., g H'-1 and Interleaving and mixing to obtain a vector sequence
  • Step 402 Interleave each sub-vector sequence in the vector sequence to obtain M inter-subsequence sub-sequences.
  • M is a positive integer.
  • the vector sequence includes M vector segments, wherein each vector segment includes a vector number that is a positive integer multiple of a vector number corresponding to a time domain symbol in a channel for transmitting the transport block.
  • the time domain symbol may be an OFDM symbol, an SC-FDMA symbol, or a time domain symbol in other multiple access modes.
  • the data processing device may respectively interleave each sub-vector sequence in the vector sequence to obtain M inter-subsequence sub-sequences;
  • the data processing device may first determine a matrix before the frequency domain interleaving; wherein, the number of columns of the matrix before the frequency domain interleaving is The number of rows is For the length of the sub-vector sequence, each vector segment in the embodiment includes only one vector contained in one time domain symbol, and N symb is a time-domain symbol in the intra-channel for transmitting the transport block in one subframe. number usually, Can be a predetermined value, and Can be satisfied The minimum value.
  • the numbers of the columns in the matrix before the frequency domain interleaving are from left to right.
  • Each row in the matrix before the frequency domain interleaving is numbered sequentially from top to bottom.
  • the data processing device may Y' 2 is filled in a progressive manner to fill the front column exchange matrix, wherein, Y 'in each of 2 symbols occupy the front row exchange An element position in the matrix; then performing column exchange on the column pre-exchange matrix according to a preset column exchange pattern, thereby generating a column-switched matrix, where the column pre-exchange matrix and the column-switched matrix are relative to the column exchange
  • the matrix before the column exchange is the matrix before the frequency domain interleaving; then all the matrix elements in the matrix after the column exchange are read in column order.
  • the sequence formed by reading all the matrix elements in the column after the column switching in the column order is the frequency domain interleaved vector sequence.
  • the data processing device may perform column switching on the frequency domain interleaving matrix according to a preset interleaving pattern, thereby obtaining a frequency domain interleaved matrix.
  • the interleaving pattern can be expressed as ⁇ p(j)> j ⁇ 0,1,...,N-1 ⁇ , where p(j) is the original column number of the jth column after the column exchange.
  • the matrix after frequency domain interleaving is expressed as follows:
  • the interleaved sub-sequence may be mapped, or the sub-vector sequences may be interleaved and concatenated before being mapped and transmitted.
  • the method may further include:
  • Step 403 Cascading the M interleaved subsequences.
  • the data processing device may cascade the M interleaved sub-sequences to complete the frequency domain interleaving of the output sequence to obtain an inter-interleaved sequence.
  • the data processing device may also interleave the vector sequence by channel interleaving. As shown in the figure, the foregoing steps 402 to 403 can also be replaced by the following step 404.
  • FIG. 5 it is a schematic flowchart of another implementation manner of the interleaving method of the present application.
  • Step 404 performing channel interleaving on the vector sequence.
  • the data processing device first obtains the number of columns as The channel interleaving matrix, where Is a positive integer greater than one.
  • the number of rows of the matrix before channel interleaving is calculated in bits. By symbol The numbers of the columns in the matrix before the channel interleaving are from left to right. The number of each row in the matrix before the channel interleaving is from top to bottom.
  • Value equal to Indicates the number of SC-FDMA symbols in each subframe in the uplink data channel. Since the SC-FDMA may not be used in the wireless communication system, and channel downlink may also be used in the downlink, the present application is not correct. The specific value is limited.
  • the MIMO rank number symbol sequence can be expressed as Then proceed line by line from the last line of the matrix, Write to the specified column one by one.
  • the specified column referred to herein may be the column indicated by the table 5.2.2.7-1 in the LTE protocol.
  • the data processing device may assign symbols corresponding to the information symbol sequence g 0 , g 1 , . . . , g H′-1 from the upper left corner of the matrix. Write to the matrix.
  • each element in the matrix represents a symbol, and if a symbol that has already been written is encountered during writing, it is skipped directly.
  • the sequence of HARQ-ACK information symbols to be transmitted may be expressed as
  • the data processing device can write the HARQ-ACK information symbol sequence one by one from the last row of the matrix to the specified column one by one. This step rewrites some symbols in the information symbol sequence that have been written into the matrix before the channel interleaving.
  • the specified column may be the column indicated by the table 5.2.2.8-2 in the LTE protocol.
  • the data processing device may perform bit rearrangement on the matrix before channel interleaving according to a preset interleaving pattern, thereby obtaining a matrix after channel interleaving.
  • the symbols in the matrix after channel interleaving are then read column by column in column order.
  • the sequence of symbols after channel interleaving is expressed as Here, N L represents the number of layers corresponding to the corresponding transport block.
  • the interleaving may be performed by one or more code block groups after generating the vector sequence.
  • each sub-vector sequence includes a vector generated by an output bit sequence corresponding to each code block in at least one code block group.
  • code blocks 0 to 2 belong to code block group 0, and code blocks 3 to 4 belong to code block group 1.
  • code blocks 0 to 2 belong to code block group 0
  • code blocks 3 to 4 belong to code block group 1.
  • the number of bits included in each vector is 4 bits
  • the length of the output bit sequence corresponding to each code block is 16 bits
  • four vectors g 0 , g 1 , g 2 may be generated based on the output bit sequence corresponding to the code block 0.
  • G 3 based on the code block output bit sequence corresponding to the can generates four vectors g 4 ⁇ g 7, may generate four vectors g 8 ⁇ g 11 based on an output bit sequence of the code block 2 corresponding to the code block 3 corresponding to the output based on The bit sequence can generate four vectors g 12 to g 15 , and four vectors g 16 to g 19 can be generated based on the output bit sequence corresponding to the code block 4.
  • the interleaving may be performed according to a code block group, and the vector sequence may include two sub-vector sequences, where each sub-vector sequence includes an output bit sequence corresponding to each code block in a code block group. Vector.
  • the sub-vector sequence A includes vectors g 0 to g 11 generated by the output bit sequences corresponding to the code blocks 0 to 2 in the code block group 0, and has a length of 12, and the sub-vector sequence B includes each code block 3 in the code block group 1 4
  • the vector g 12 to g 19 generated by the corresponding output bit sequence has a length of 8.
  • the interleaving may be performed according to multiple code block groups, and the vector sequence includes a sub-vector sequence including vectors g 0 to g 19 generated by the output bit sequences corresponding to the code blocks in the two code block groups. It should be noted that the embodiments are convenient for illustration, and the embodiments of the present invention are not limited thereto.
  • the method may include:
  • P and Q are integers greater than zero.
  • the input vector sequence A includes Q vectors, which are obtained based on P output bit sequences.
  • Each of the output bit sequences is obtained from a circular buffer, where the circular buffer is used to store all or part of the bits obtained by encoding the code blocks corresponding to each of the output bit sequences, or the circular buffer is used. And storing all or part of the bits obtained after the code block corresponding to each of the output bit sequences is encoded and rearranged.
  • each output bit sequence may be obtained by transmitting block partitions, respectively, via steps 103-105 or via steps 103, 106, 107 and 105.
  • the Q vectors are obtained based on the P output bit sequences, and each output bit sequence is divided into at least one vector, and the P output bit sequences may generate Q vectors; or, the P output bit sequences are respectively performed in the sequence.
  • Interleaving obtains P interleaved bit sequences, and divides each interleaved bit sequence into at least one vector, thereby obtaining Q vectors.
  • the method for performing intra-sequence interleaving for each output bit sequence may refer to the foregoing method steps 301 to 305, or A01 to A02.
  • Q is a positive integer multiple of the vector contained in the intra-channel time domain symbol used to transmit the transport block within a transmission time interval.
  • P is the number of code blocks obtained after the code block is divided by the code block.
  • P is the number of code blocks included in at least one code block group of the G code block groups obtained after the code block is divided by the code block.
  • FIG. 6 is a schematic structural diagram of an embodiment of a data processing device according to the present application.
  • the data processing device may include: an obtaining unit 601, configured to acquire a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a code generated after the code block is split. a coding unit 602, configured to encode a first to-be-processed bit sequence to obtain a first coded bit sequence, and a saving unit 603, configured to save all or at least part of the first coded bit sequence to a circular buffer; The output unit 604 is configured to extract the first output bit sequence from the circular buffer.
  • the circular buffer in the data processing device can be used to save all or part of the bits in the first encoded bit sequence obtained by the encoding unit 602, so that rate matching can be performed.
  • the obtaining unit 601 includes: an obtaining subunit, configured to acquire a transport block, and a generating subunit, configured to generate, according to the transport block, N bit sequences including the first to-be-processed bit sequence , N is an integer greater than one.
  • the first interleaving unit is configured to interleave the first output bit sequence.
  • the method further includes: a second interleaving unit, configured to generate a vector sequence according to the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence, each of the first The vector of output bit sequences includes at least one bit of the first output bit sequence, wherein Q is a positive integer; the vector sequence is interleaved.
  • a second interleaving unit configured to generate a vector sequence according to the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence, each of the first The vector of output bit sequences includes at least one bit of the first output bit sequence, wherein Q is a positive integer; the vector sequence is interleaved.
  • the vector sequence further includes a vector generated based on the second output bit sequence; each vector of the second output bit sequence includes at least one bit of the second output bit sequence.
  • the second interleaving unit is specifically configured to interleave a vector included in the vector sequence.
  • the second interleaving unit is specifically configured to perform intra-sub-interleaving on each sub-vector sequence included in the vector sequence to obtain M inter-subsequence sub-sequences, where the vector sequence includes M sub-sequences. a sequence of vectors, each of the number of vectors included in the sub-vector sequence being a positive integer multiple of a vector included in a time-domain symbol for transmitting the transport block in a transmission time interval; cascading the M interlaces Post subsequence.
  • the data processing device can be used to implement the foregoing method embodiments.
  • the data processing device shown in FIG. 7 may further include: a rearrangement unit 605.
  • the acquiring unit 601 is configured to acquire a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a code block generated by the transport block or the transport block after the code block is divided;
  • the coding unit 602 For encoding the first to-be-processed bit sequence to obtain a first coded bit sequence, and a rearranging unit 605, configured to perform bit-rearrangement on the first coded bit sequence to obtain a first rearranged bit sequence;
  • the saving unit 603 And for saving all or at least part of the first reordered bit sequence to a circular buffer; and outputting unit 604, for extracting the first output bit sequence from the saved bits in the circular buffer.
  • the rearranging unit 605 is specifically configured to change a position of the first sub-sequence in the first encoded bit sequence, where the length of the first sub-sequence is a positive integer multiple of the spreading factor; or, delete a second subsequence in the first encoded bit sequence, the length of the second subsequence being a positive integer multiple of the spreading factor. That is, the first rearranged bit sequence is obtained by changing the position of the first subsequence in the first encoded bit sequence, or the first rearranged bit sequence is the second of deleting the first encoded bit sequence. Subsequence obtained.
  • the circular buffer in the data processing device can also be used to rearrange all or part of the bits in the first reordered bit sequence obtained by unit 605, so that rate matching can be performed.
  • the second subsequence includes at least one information bit.
  • the rearrangement unit 605 is specifically configured to obtain a post-punch sequence and a redundant interleaving sequence, where the post-punch sequence is a sequence obtained by puncturing the information bit sequence; the redundant interleaving sequence is a pair a sequence obtained by bit rearrangement of a redundant sequence; cascading a post-punch sequence, a redundant interleaving sequence, and a second redundancy sequence, thereby obtaining a bit first rearranged bit sequence; wherein the information bit sequence is
  • the information bits included in the first to-be-processed bit sequence are formed by the redundant bits generated by encoding the first to-be-processed bit sequence using the core matrix of the LDPC check matrix, and the second redundancy
  • the sequence consists of redundant bits generated by encoding the first to-be-processed bit sequence using an spreading matrix of the LDPC check matrix.
  • the rearranging unit 605 is further configured to rearrange the sub-sequences included in the first redundant sequence according to the selected interleaving pattern, where each sub-sequence is represented by a column of parity bits in the core matrix.
  • the sequence is composed of redundant bits generated by encoding.
  • the data processing device can be used to implement the foregoing method embodiments.
  • the method may include:
  • the obtaining unit 601 is configured to obtain a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a transport block or a code block generated after the code block is divided.
  • the encoding unit 602 is configured to encode the first to-be-processed bit sequence to obtain a first encoded bit sequence.
  • An output unit 604 configured to extract a first output bit sequence from a circular buffer
  • the loop buffer is configured to save all bits or partial bits of the first encoded bit sequence, or the loop buffer is used to save all bits or partial bits of the first rearranged bit sequence, the first The rearranged bit sequence is obtained by bit rearranging the first encoded bit sequence.
  • the method further includes a first interleaving unit, configured to interleave the first output bit sequence.
  • the method further includes: a second interleaving unit, configured to generate a vector sequence according to the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence, each of the first The vector of output bit sequences includes at least one bit of the first output bit sequence, wherein Q is a positive integer; the vector sequence is interleaved.
  • a second interleaving unit configured to generate a vector sequence according to the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence, each of the first The vector of output bit sequences includes at least one bit of the first output bit sequence, wherein Q is a positive integer; the vector sequence is interleaved.
  • the data processing device can be used to implement the foregoing method embodiments.
  • the data processing device may be used to implement the method in the foregoing method embodiments.
  • the data processing device can include:
  • An obtaining unit configured to obtain an input bit sequence A, the input bit sequence A being obtained based on at least one set of output bit sequences, wherein each set of output bit sequences includes at least one output bit sequence, each set of output bit sequence groups Each of the output bit sequences is generated based on each code block in the same code block group;
  • An interleaving unit is configured to interleave the input bit sequence A.
  • the data processing device may be used to implement the method in the foregoing method embodiments.
  • the data processing device can include:
  • Generating unit configured to obtain M vectors based on the N output bit sequences
  • An obtaining unit configured to acquire an input vector sequence A, where the input vector sequence A includes the M vectors;
  • An interleaving unit configured to interleave the sequence of input vectors A
  • N is an integer greater than 0, and M is an integer greater than 0, and each of the output bit sequences corresponds to one code block obtained by the code block partitioning of the transport block.
  • FIG. 8 is a schematic structural diagram of another embodiment of a data processing device according to the present application.
  • the data processing device shown in FIG. 8 may include: a processor 801, a memory 802, and a transceiver 803.
  • the transceiver 803 is configured to acquire a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a code block generated by a transport block or a transport block after code block segmentation; Encoding the first to-be-processed bit sequence to obtain a first encoded bit sequence; saving all or at least a portion of the first encoded bit sequence to a circular buffer; and storing the bit from the circular buffer The first output bit sequence is taken out.
  • the transceiver 803 can also be configured to output the first output bit sequence.
  • the transceiver 803 is further configured to obtain a transport block, where the processor 801 is further configured to generate, according to the transport block, N bit sequences including the first to-be-processed bit sequence. , N is an integer greater than one.
  • the processor 801 is further configured to perform interleaving on the first output bit sequence.
  • the processor 801 is further configured to generate a vector sequence based on the first output bit sequence, where the vector sequence includes Q vectors of the first output bit sequence, each of the first The vector of output bit sequences includes at least one bit of the first output bit sequence, wherein Q is a positive integer; the vector sequence is interleaved.
  • the processor 801 is further configured to interleave a vector included in the vector sequence.
  • the processor 801 is further configured to perform inter-sub-interleaving on each sub-vector sequence included in the vector sequence to obtain M inter-subsequence sub-sequences, where the vector sequence includes M sub-sequences. a sequence of vectors, each of the number of vectors included in the sub-vector sequence being a positive integer multiple of a vector included in a time-domain symbol for transmitting the transport block in a transmission time interval; cascading the M interlaces Post subsequence.
  • the transceiver 803 is further configured to obtain a first to-be-processed bit sequence, where the first to-be-processed bit sequence is a code block generated by the transport block or the transport block after the code block is divided;
  • the 801 may be further configured to: encode the first to-be-processed bit sequence to obtain a first coded bit sequence; perform bit-reordering on the first coded bit sequence to obtain a first rearranged bit sequence; All or at least some of the bits of the bit sequence are saved to a circular buffer; the first output bit sequence is fetched from the saved bits in the circular buffer.
  • the performing the bit rearrangement on the first encoded bit sequence includes at least one operation of: changing a position of the first subsequence in the first encoded bit sequence, where the length of the first subsequence is a spreading factor A positive integer multiple; or, deleting the second subsequence in the first encoded bit sequence, the length of the second subsequence being a positive integer multiple of the spreading factor.
  • the second subsequence includes at least one information bit.
  • the processor 801 may be further configured to obtain a post-punch sequence and a redundant interleaving sequence, where the post-punch sequence is a sequence obtained by puncturing the information bit sequence; the redundant interleaving sequence is to the first redundant sequence Performing a sequence of bit rearrangement; cascading the punctured sequence, the redundant interleaving sequence, and the second redundant sequence, thereby obtaining a bit first reordering bit sequence; wherein the information bit sequence is processed by the first to be processed
  • the information bits included in the bit sequence are composed of redundant bits generated by encoding the first to-be-processed bit sequence using a core matrix of the LDPC check matrix, and the second redundant sequence is used by using LDPC
  • the spreading matrix of the check matrix is composed of redundant bits generated by encoding the first bit sequence to be processed.
  • the processor 801 is further configured to reorder the sub-sequences included in the first redundancy sequence according to the selected interleaving pattern, where each sub-sequence encodes the information bit sequence by a column of check bits in the core matrix.
  • the redundant bits are formed.
  • the data processing device can include one or more memories, and one or more processors, the memory storing instructions coupled to the memory for retrieving instructions in the memory to The various steps described in the various method embodiments above are performed.
  • the present application is used for a system architecture of a transmitting side data processing system of an uplink.
  • the system may include: a transport block CRC attachment module for performing CRC attachment on a transport block; a code block segmentation code block CRC attachment module, for Performing CRC attachment on the code block; wherein the code block may be generated by the code block by code block segmentation; an encoder module for encoding the code block, for example, may be used to implement the coding step in the foregoing embodiment. a bit re-ordering module for performing bit rearrangement on a sequence output by the encoding module.
  • the step of performing bit rearrangement on the encoded bit sequence in the foregoing embodiment may be implemented; rate matching a module for implementing the process of rate matching in the foregoing embodiments; for example, for implementing the foregoing embodiments, saving all or at least some bits of the encoded bit sequence to a circular buffer; saving from the circular buffer Steps of extracting an output bit sequence from the bits; a block interleaver module for matching rate after rate
  • the bit sequence is interleaved may be used to implement the step of interleaving the output bit sequence in the foregoing embodiment; a code block concatenation module for cascading output bit sequence modules of each code block; for example, The first output bit sequence, the second output bit sequence, and the like may be outputted in the foregoing embodiment, and the data and control multiplexing module is added to the sequence of the code block cascade output. Data information or control information.
  • the code block CRC attaching module and the column switching module are optional modules, and the system may not include the code block CRC
  • the sub-block interleaving module, the code block cascading module, and the data and control information may also be added by the code block cascading module, the data and control information adding module, and the frequency domain interleaving as shown in FIG. The module is replaced.
  • the block interleaving module, the code block cascading module, and the data and control information adding module may also be a code block cascading module, a data and control information adding module, and a channel interleaving module as shown in FIG. Replaced.
  • the code block cascading module can be used to cascade the bit sequence output by the rate matching module. For example, the step of generating a vector sequence can be implemented.
  • the data and control information adding module can then implement the step of adding path-dependent signaling in the vector sequence.
  • the frequency domain interleaving module may be configured to perform frequency domain interleaving on a sequence output by the code block cascading mode; for example, performing the step of interleaving the vector sequence in the foregoing embodiment.
  • the channel interleaving module can be used to perform frequency domain interleaving on the sequence output by the code block concatenation module; for example, the step of interleaving the vector sequence in the foregoing embodiment is implemented.
  • the uplink receiving data processing system system architecture can be as shown in FIG.
  • the system may include: a control signaling detection module; a code block segmentation module; a de-block interleaver module; and a rate matching (de-) Rate matching module; HARQ combine module; decoder module; code block concatenation module; TB CRC caculation module.
  • control information detecting module, the code block combining module, and the deblocking interleaving module may also be replaced by a frequency domain interleaving module, a control information detecting module and a code block dividing module as shown in FIG. 13; or, as shown in FIG. Decoding frequency domain interleaving module, control information detection module and code block segmentation module
  • the transmission side data processing system system architecture for the downlink is similar to the transmission side data processing system system shelf for the uplink. However, since it is not necessary to transmit the associated channel signaling in the downlink, the transmitting side data processing system system for the downlink may not include the data and control information adding module.
  • the system architecture of the receiving side data processing system for downlink is used in this application.
  • the transmission side data processing system system for the downlink may not include the control information detecting module.
  • the present application further provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments of the data processing method provided by the application.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (English: read-only memory, abbreviated as: ROM) or a random access memory (English: random access memory, abbreviation: RAM).
  • the technology in the embodiments of the present application can be implemented by means of software plus a necessary general hardware platform.
  • the technical solution in the embodiments of the present application may be embodied in the form of a software product in essence or in the form of a software product, and the computer software product may be stored in a storage medium such as a ROM/RAM. , a diskette, an optical disk, etc., including instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform the methods described in various embodiments of the present application or portions of the embodiments.
  • a computer device which may be a personal computer, server, or network device, etc.

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Abstract

Des modes de réalisation de la présente invention concernent un procédé de traitement de données et un dispositif procédé de traitement de données. Le procédé comprend les étapes suivantes : acquisition d'une première séquence de bits à traiter, la première séquence de bits à traiter étant un bloc de transmission ou un bloc de code généré par le bloc de transmission après avoir subi une segmentation de bloc de code ; codage de la première séquence de bits à traiter afin d'obtenir une première séquence de bits codée ; enregistrement de la totalité ou d'au moins une partie de la première séquence de bits codée dans une mémoire cache circulaire ; et extraction d'une première séquence de bits de sortie à partir des bits enregistrés dans la mémoire cache circulaire. L'utilisation du procédé et du dispositif selon la présente invention permet d'obtenir une adaptation de débit des séquences générées par un codage de contrôle de parité à faible densité (LDPC).
PCT/CN2018/075290 2017-02-06 2018-02-05 Procédé et dispositif de traitement de données Ceased WO2018141292A1 (fr)

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EP18748349.0A EP3573270B1 (fr) 2017-02-06 2018-02-05 Procédé et dispositif de traitement de données
US16/531,956 US11133832B2 (en) 2017-02-06 2019-08-05 Data processing method and device

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CN201710065944 2017-02-06
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