WO2018145746A1

WO2018145746A1 - High-voltage power electronic building block design

Info

Publication number: WO2018145746A1
Application number: PCT/EP2017/052838
Authority: WO
Inventors: Nan Chen; Jan Svensson; Mikael Davidsson
Original assignee: Rabb Schweiz Ag
Priority date: 2017-02-09
Filing date: 2017-02-09
Publication date: 2018-08-16
Also published as: WO2018145746A8

Abstract

The present disclosure relates to a Power Electronic Building Block (PEBB) 1 for a power converter. The PEBB comprises a semiconductor switch arrangement S comprising a plurality of semiconductor switches S1-S4, a capacitor arrangement C, and a busbar arrangement B, connecting the capacitor arrangement with the semiconductor switch arrangement. The busbar arrangement comprises a first laminated busbar B1 connecting a first plurality of capacitor elements C11-C14 of the capacitor arrangement to the semiconductor switch arrangement, and a second laminated busbar B2 connecting a second plurality of capacitor elements C21-C24 of the capacitor arrangement to the semiconductor switch arrangement. Each of the first and second laminated busbar comprises a positive conductor B1+ or B2+ laminated to a negative conductor B1- or B2-, each connected to each of the plurality of capacitor elements C11-C14 or C21-C24.

Description

HIGH-VOLTAGE POWER ELECTRONIC BUILDING BLOCK

DESIGN

TECHNICAL FIELD

The present disclosure relates to a High Voltage (HV) PEBB design with busbars connecting semiconductor switches with capacitor elements for power converters.

BACKGROUND

Power converters such as Modular Multilevel Converters (MMC), which can be used for e.g. Static Synchronous Compensators (STATCOM), are configured for higher voltages and switching frequencies e.g. by using silicon carbide (SiC) semiconductor switches such as in Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFET) or other semiconductor switches, e.g. for voltage ratings above 10 kV. However, such configurations generally lead to rather high detrimental loop inductances in the MMC cell or like converter building block (also called module or Power Electronic

Building Block, PEBB) comprising semiconductor switches and capacitor elements.

SUMMARY

It is an objective of the present invention to provide a PEBB design with reduced loop inductance, especially for higher voltage ratings and switching frequencies such as with SiC semiconductor devices/switches.

To implement SiC devices into e.g. a STATCOM application, the PEBB should preferably be designed with regard to the special features of SiC devices such as high-speed and low-loss switching. The following features may be preferred in some embodiments of the PEBB design utilizing SiC devices:

- Low loop-inductance (consider challenge from using large capacitor bank);

- Parallel operation of SiC devices in a semiconductor switch (consider high di/dt, i.e. change in current over time). For example, SiC devices may require reduced commutation-loop inductance in their design to reduce the switching losses and to reduce the transient over-voltages. In addition, parallel operation of semiconductor devices in each semiconductor switch may be considered in PEBB design to increase the current rating.

The technical property of high voltage devices (e.g. >io kV), and large capacitor banks are imposing additional design challenges on energy levels and protection. Therefore, new designs may be useful for high-power converter modules (PEBB). Although the invention may be particularly useful when using SiC devices in PEBB, embodiments of the present invention may also be useful with any other type of semiconductor material, e.g. regular silicon (Si).

According to an aspect of the present invention, there is provided a PEBB for a power converter. The PEBB comprises a semiconductor switch

arrangement comprising a plurality of semiconductor switches, a capacitor arrangement, and a busbar arrangement connecting the capacitor

arrangement with the semiconductor switch arrangement. The busbar arrangement comprises a first laminated busbar connecting a first plurality of capacitor elements of the capacitor arrangement to the semiconductor switch arrangement, and a second laminated busbar connecting a second plurality of capacitor elements of the capacitor arrangement to the semiconductor switch arrangement. Each of the first and second laminated busbar comprises a positive conductor Bi+ or B2+ laminated to a negative conductor Bi- or B2-, each connected to each of the plurality of capacitor elements C11-C14 or C21-C24.

According to another aspect of the present invention, there is provided an MMC comprising an embodiment of the PEBB of the present disclosure.

According to another aspect of the present invention, there is provided a STATCOM comprising an embodiment of the PEBB of the present disclosure. By using a busbar which is split into a first and second part, typically extending in different directions from the semiconductor switch

arrangement, the capacitor elements can on average be connected closer to the semiconductor switch arrangement, reducing loop inductance in the busbar. The loop inductance is further reduced by laminating the busbar and by using a plurality of parallel connected capacitor elements, each with a relatively low capacitance, instead of a single capacitor element with a high capacitance.

It is to be noted that any feature of any of the aspects may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any of the other aspects. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following detailed disclosure, from the attached dependent claims as well as from the drawings. Generally, all terms used in the claims are to be interpreted according to their ordinary meaning in the technical field, unless explicitly defined otherwise herein. All references to "a/an/the element, apparatus, component, means, step, etc." are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any method disclosed herein do not have to be performed in the exact order disclosed, unless explicitly stated. The use of "first", "second" etc. for different features/components of the present disclosure are only intended to distinguish the features/components from other similar features/components and not to impart any order or hierarchy to the features/components.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments will be described, by way of example, with reference to the accompanying drawings, in which:

Fig la is a schematic circuit diagram of an embodiment of a PEBB, in accordance with the present invention. Fig lb is a schematic design diagram of another embodiment of a PEBB, in accordance with the present invention.

Fig 2 is a schematic circuit diagram of an embodiment of a semiconductor switch comprising a plurality of parallel connected modules, in accordance with the present invention.

DETAILED DESCRIPTION

Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which certain embodiments are shown.

However, other embodiments in many different forms are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout the description.

Figures la and lb illustrate embodiments of the inventive PEBB l, where figure la illustrates the circuit of a PEBB embodiment, while figure lb more attempts to illustrate an example of an actual design of another PEBB embodiment. The PEBB may e.g. form a cell in an MMC and/or a STATCOM. A semiconductor switch arrangement S, which may be mounted on a cooler 2, is connected to a capacitor arrangement C via a busbar arrangement B. A first busbar Bi connects a first plurality of parallel connected capacitor elements C11-C14/C16, and a second busbar B2 connects a second plurality of parallel connected capacitor elements C21-C24/26. It is noted that the embodiments of figure la and lb differ from each other in the number of capacitor elements connected to each busbar, where figure la shows six capacitor elements C11-C16 and C21-C26, respectively, connected to each of the two busbars Bi and B2, while figure lb shows four capacitor elements C11-C14 and C21-C24, respectively, connected to each of the two busbars Bi and B2. However, any number of parallel connected capacitor elements may be used in the first and second plurality depending on the desired use of the PEBB. By parallel connecting capacitor elements, instead of using a single/fewer, but larger, capacitor element, the total equivalent series inductance (ESL) of the capacitor arrangement C can be reduced while still providing the desired total capacitance. It may thus be preferred to use more, but weaker, capacitor elements, e.g. each having a capacitance within the range of 100-500 μΡ. The semiconductor switch arrangement S comprises a plurality of

semiconductor switches S1-S4, in the example of figure la with four semiconductor switches forming a full-bridge configuration, but any other configuration (with any number of at least two semiconductor switches) may be used with embodiments of the present invention, such as with two semiconductor switches forming a half-bridge configuration, or a three-level converter. In a preferred embodiment, at least one SiC semiconductor device may be used in each semiconductor switch. As discussed herein, the PEBB, and thus the semiconductor switches, may be designed for HV applications, e.g. using SiC devices, while the semiconductor switches may have a voltage rating of at least 1.7 kV, 3.3 kV or 5 kV, but more preferably of at least 10 kV, but embodiments of the present invention may also be useful for lower voltage ratings. As also discussed herein, each semiconductor switch may comprise a plurality of semiconductor devices in order to increase the current rating, e.g. to at least 300 A, at least 1 kA or at least 1.5 kA or 2 kA. The semiconductor switch may be in the form of, or comprise as one or more semiconductor devices, any type of switch design, e.g. a MOSFET.

The PEBB 1 comprises any number of at least two busbars Bi and B2, herein called the first busbar Bi and the second busbar B2, e.g. three or four busbars, each connecting a plurality of parallel connected capacitor elements Ci or C2 to the semiconductor switch arrangement S. Each busbar Bi or B2 comprises a two conductors, wherein one is connected to a first terminal of each capacitor element and the other is connected to a second terminal of each capacitor element of the plurality of capacitor elements. Herein, the two conductors are called the positive conductor Bi+ or B2+, which is connected to the positive terminal of the capacitor elements, and the negative conductor Bi- or B2-, connected to the negative terminal of the capacitor element, when the PEBB is in use. In figure lb, the negative conductors Bi- and B2- are striped to make the figure more clear. In accordance with the present invention, the busbars Bi and B2 are laminated, meaning that in each busbar the positive conductor is laminated to the negative conductor, with an electrically insulating layer there between. This to reduce the loop inductance compared with non-laminated busbars. In the example of figure lb, the negative conductors Bi- and B2- are facing the capacitor elements and the positive conductors Bi+ and B2+ are laminated on the outside (each having the negative conductor between itself and the capacitor elements) but in other embodiments it may be the other way around with the positive conductors facing the capacitor elements and the negative conductors on the outside. It should also be noted that instead of designing the PEBB with the first and second plurality of capacitor elements Ci and C2 facing each other and being surrounded by the busbars on the outside, any other design with laminated busbars is also possible, e.g. with the busbars extending in the middle with each of the first and second pluralities of capacitor elements facing outwards, away from each other. Since also the outer conductor (the positive conductor in figure lb) is connected to each capacitor element in the plurality of capacitor elements, holes may be provided in the inner conductor (the negative conductor in figure lb) for allowing the outer conductor access to the capacitor elements. Typically, the first and second busbars Bi and B2, as connected to the first and second pluralities of capacitor elements Ci and C2, are arranged to be mirror-symmetrical in the PEBB 1.

By selecting more numerous capacitor elements each with lower capacitance and thus lower equivalent series inductance (ESL) than larger capacitor elements, the total equivalent series inductance of the capacitor arrangement C may be reduced. Parallel connected capacitor elements may be used to obtain the required total capacitance of the capacitor arrangement.

By using a plurality of busbars Bi and B2, and by using busbars which are laminated, the loop inductance contribution from the busbar arrangement B is further reduced. By using two or more busbars, the design of the PEBB may also be made more compact (see figure lb), compared with if only one (longer) busbar was used. The above-mentioned features help to provide optimized parasitic condition for the switching operation of e.g. SiC devices, especially for switching loss reduction and transient overvoltage stress mitigation. It may also important to be able to avoid overvoltage during short-circuit protection utilizing soft- turn-off.

Figure 2 illustrates an embodiment of a semiconductor switch Si. As mentioned above, each switch, e.g. of S1-S4 of figure la, may comprise a plurality of parallel connected semiconductor devices, e.g. MOSFETs, (one of which is marked with reference D in figure 2) whereby an increased current rating may be achieved. In some embodiments, the semiconductor devices may be provided in modules, e.g. the three parallel connected semiconductor modules Sia, Sib and Sic in figure 2. In the example of figure 2, each semiconductor module comprises a full-bridge configuration of

semiconductor devices D, and any number of such modules may be connected in parallel depending on the intended use of the semiconductor switch Si. In other embodiments, the semiconductor modules may comprise other configurations of semiconductor devices than full-bridge, e.g. half- bridge or three-level.

Parallel connection of e.g. SiC modules Sia-c may be a scenario for SiC PEBBs 1 in order to increase the rated PEBB current. Current stress balancing for each parallel-connected SiC module, as well as for the semiconductor devices inside each SiC module may be more challenging considering the high di/dt capability of the SiC devices. Current balancing improvements may be achieved with more evenly balanced loop-inductance between SiC devices and the capacitor elements.

The use of multiple laminated busbars help in providing each module Sia-c similar total equivalent loop-inductance considering the capacitor elements. Further reduction and equalization of the loop inductance experienced by each semiconductor device may be achieved by limiting the difference in physical location of the SiC module terminals (one of which is marked as reference T in figure 2). Thus, the modules Sia-c are preferably located close together and at substantially the same (reduced) distance from the capacitor elements to provide equal/balanced and reduced parasitic conditions, e.g. commutation loop inductance, experienced by the semiconductor devices D.

In some embodiments of the present invention, each of the semiconductor switches S1-S4 comprises a plurality of identical parallel connected semiconductor modules Sia-Sic, e.g. each comprising semiconductor devices D in half-bridge or full-bridge configuration.

In some embodiments of the present invention, each of the semiconductor switches S1-S4 comprises a SiC device D. In some embodiments of the present invention, the semiconductor switches S1-S4 are in half-bridge or full-bridge configuration.

In some embodiments of the present invention, each of the semiconductor switches S1-S4 comprises a MOSFET D.

In some embodiments of the present invention, the PEBB 1 has a voltage rating of at least 10 kV. In some embodiments of the present invention, the PEBB 1 has a current rating of at least 1 kA.

In some embodiments of the present invention, each capacitor element C11-C16 and C21-C26 has a capacitance within the range of 100-500 μΕ.

In some embodiments of the present invention, the PEBB 1 is for an MMC. In some embodiments of the present invention, the PEBB 1 is for a

STATCOM.

The present disclosure has mainly been described above with reference to a few embodiments. However, as is readily appreciated by a person skilled in the art, other embodiments than the ones disclosed above are equally possible within the scope of the present disclosure, as defined by the appended claims.

Claims

1. A Power Electronic Building Block, PEBB, (l) for a power converter, the PEBB comprising: a semiconductor switch arrangement (S) comprising a plurality of

semiconductor switches (S1-S4); a capacitor arrangement (C); and a busbar arrangement (B), connecting the capacitor arrangement with the semiconductor switch arrangement; wherein the busbar arrangement comprises a first laminated busbar (Bi) connecting a first plurality of capacitor elements (C11-C16) of the capacitor arrangement to the semiconductor switch arrangement, and a second laminated busbar (B2) connecting a second plurality of capacitor elements (C21-C26) of the capacitor arrangement to the semiconductor switch arrangement; wherein each of the first and second laminated busbar comprises a positive conductor (Βι+; B2+) laminated to a negative conductor (Bi-; B2-), each connected to each of the plurality of capacitor elements (C11-C16; C21-C26).

2. The PEBB of claim 1, wherein each of the semiconductor switches (Si- S4) comprises a plurality of identical parallel connected semiconductor modules (Sia-Sic), e.g. each comprising semiconductor devices (D) in half- bridge or full-bridge configuration.

3. The PEBB of claim 1 or 2, wherein each of the semiconductor switches (S1-S4) comprises a silicon carbide, SiC, device.

4. The PEBB of any preceding claim, wherein the semiconductor switches (S1-S4) are in half-bridge or full-bridge configuration.

5. The PEBB of any preceding claim, wherein each of the semiconductor switches (S1-S4) comprises a Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET.

6. The PEBB of any preceding claim, wherein the PEBB (1) has a voltage rating of at least 3.3 kV.

7. The PEBB of any preceding claim, wherein the PEBB (1) has a current rating of at least 300 A.

8. The PEBB of any preceding claim, wherein each capacitor element (C11-C16, C21-C26) has a capacitance within the range of 100-500 μΡ.

9. The PEBB of any preceding claim, wherein the PEBB (1) is for a Modular Multilevel Converter, MMC.

10. The PEBB of any preceding claim, wherein the PEBB (1) is for a Static Synchronous Compensator, STATCOM.

11. An MMC comprising a PEBB of any preceding claim.

12. A STATCOM comprising a PEBB of any claim 1-10.