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WO2018145746A1 - Conception de bloc de construction d'électronique de puissance à haute tension - Google Patents

Conception de bloc de construction d'électronique de puissance à haute tension Download PDF

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Publication number
WO2018145746A1
WO2018145746A1 PCT/EP2017/052838 EP2017052838W WO2018145746A1 WO 2018145746 A1 WO2018145746 A1 WO 2018145746A1 EP 2017052838 W EP2017052838 W EP 2017052838W WO 2018145746 A1 WO2018145746 A1 WO 2018145746A1
Authority
WO
WIPO (PCT)
Prior art keywords
pebb
arrangement
capacitor
semiconductor
busbar
Prior art date
Application number
PCT/EP2017/052838
Other languages
English (en)
Other versions
WO2018145746A8 (fr
Inventor
Nan Chen
Jan Svensson
Mikael Davidsson
Original Assignee
Rabb Schweiz Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rabb Schweiz Ag filed Critical Rabb Schweiz Ag
Priority to PCT/EP2017/052838 priority Critical patent/WO2018145746A1/fr
Publication of WO2018145746A1 publication Critical patent/WO2018145746A1/fr
Publication of WO2018145746A8 publication Critical patent/WO2018145746A8/fr

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4835—Converters with outputs that each can have more than two voltages levels comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage

Definitions

  • the present disclosure relates to a High Voltage (HV) PEBB design with busbars connecting semiconductor switches with capacitor elements for power converters.
  • HV High Voltage
  • Modular Multilevel Converters such as Modular Multilevel Converters (MMC), which can be used for e.g. Static Synchronous Compensators (STATCOM), are configured for higher voltages and switching frequencies e.g. by using silicon carbide (SiC) semiconductor switches such as in Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFET) or other semiconductor switches, e.g. for voltage ratings above 10 kV.
  • SiC silicon carbide
  • MOSFET Metal-Oxide- Semiconductor Field-Effect Transistors
  • Such configurations generally lead to rather high detrimental loop inductances in the MMC cell or like converter building block (also called module or Power Electronic
  • PEBB Building Block, PEBB comprising semiconductor switches and capacitor elements.
  • the PEBB should preferably be designed with regard to the special features of SiC devices such as high-speed and low-loss switching.
  • the following features may be preferred in some embodiments of the PEBB design utilizing SiC devices:
  • SiC devices may require reduced commutation-loop inductance in their design to reduce the switching losses and to reduce the transient over-voltages.
  • parallel operation of semiconductor devices in each semiconductor switch may be considered in PEBB design to increase the current rating.
  • PEBB high-power converter modules
  • a PEBB for a power converter.
  • the PEBB comprises a semiconductor switch
  • the busbar arrangement comprises a first laminated busbar connecting a first plurality of capacitor elements of the capacitor arrangement to the semiconductor switch arrangement, and a second laminated busbar connecting a second plurality of capacitor elements of the capacitor arrangement to the semiconductor switch arrangement.
  • Each of the first and second laminated busbar comprises a positive conductor Bi+ or B2+ laminated to a negative conductor Bi- or B2-, each connected to each of the plurality of capacitor elements C11-C14 or C21-C24.
  • an MMC comprising an embodiment of the PEBB of the present disclosure.
  • a STATCOM comprising an embodiment of the PEBB of the present disclosure.
  • the capacitor elements can on average be connected closer to the semiconductor switch arrangement, reducing loop inductance in the busbar.
  • the loop inductance is further reduced by laminating the busbar and by using a plurality of parallel connected capacitor elements, each with a relatively low capacitance, instead of a single capacitor element with a high capacitance.
  • Fig la is a schematic circuit diagram of an embodiment of a PEBB, in accordance with the present invention.
  • Fig lb is a schematic design diagram of another embodiment of a PEBB, in accordance with the present invention.
  • Fig 2 is a schematic circuit diagram of an embodiment of a semiconductor switch comprising a plurality of parallel connected modules, in accordance with the present invention.
  • FIGS la and lb illustrate embodiments of the inventive PEBB l, where figure la illustrates the circuit of a PEBB embodiment, while figure lb more attempts to illustrate an example of an actual design of another PEBB embodiment.
  • the PEBB may e.g. form a cell in an MMC and/or a STATCOM.
  • a semiconductor switch arrangement S which may be mounted on a cooler 2, is connected to a capacitor arrangement C via a busbar arrangement B.
  • a first busbar Bi connects a first plurality of parallel connected capacitor elements C11-C14/C16, and a second busbar B2 connects a second plurality of parallel connected capacitor elements C21-C24/26.
  • figure la and lb differ from each other in the number of capacitor elements connected to each busbar, where figure la shows six capacitor elements C11-C16 and C21-C26, respectively, connected to each of the two busbars Bi and B2, while figure lb shows four capacitor elements C11-C14 and C21-C24, respectively, connected to each of the two busbars Bi and B2.
  • any number of parallel connected capacitor elements may be used in the first and second plurality depending on the desired use of the PEBB.
  • parallel connecting capacitor elements instead of using a single/fewer, but larger, capacitor element, the total equivalent series inductance (ESL) of the capacitor arrangement C can be reduced while still providing the desired total capacitance. It may thus be preferred to use more, but weaker, capacitor elements, e.g. each having a capacitance within the range of 100-500 ⁇ .
  • the semiconductor switch arrangement S comprises a plurality of
  • semiconductor switches S1-S4 in the example of figure la with four semiconductor switches forming a full-bridge configuration, but any other configuration (with any number of at least two semiconductor switches) may be used with embodiments of the present invention, such as with two semiconductor switches forming a half-bridge configuration, or a three-level converter.
  • at least one SiC semiconductor device may be used in each semiconductor switch.
  • the PEBB and thus the semiconductor switches, may be designed for HV applications, e.g. using SiC devices, while the semiconductor switches may have a voltage rating of at least 1.7 kV, 3.3 kV or 5 kV, but more preferably of at least 10 kV, but embodiments of the present invention may also be useful for lower voltage ratings.
  • each semiconductor switch may comprise a plurality of semiconductor devices in order to increase the current rating, e.g. to at least 300 A, at least 1 kA or at least 1.5 kA or 2 kA.
  • the semiconductor switch may be in the form of, or comprise as one or more semiconductor devices, any type of switch design, e.g. a MOSFET.
  • the PEBB 1 comprises any number of at least two busbars Bi and B2, herein called the first busbar Bi and the second busbar B2, e.g. three or four busbars, each connecting a plurality of parallel connected capacitor elements Ci or C2 to the semiconductor switch arrangement S.
  • Each busbar Bi or B2 comprises a two conductors, wherein one is connected to a first terminal of each capacitor element and the other is connected to a second terminal of each capacitor element of the plurality of capacitor elements.
  • the two conductors are called the positive conductor Bi+ or B2+, which is connected to the positive terminal of the capacitor elements, and the negative conductor Bi- or B2-, connected to the negative terminal of the capacitor element, when the PEBB is in use.
  • the negative conductors Bi- and B2- are striped to make the figure more clear.
  • the busbars Bi and B2 are laminated, meaning that in each busbar the positive conductor is laminated to the negative conductor, with an electrically insulating layer there between. This to reduce the loop inductance compared with non-laminated busbars.
  • the negative conductors Bi- and B2- are facing the capacitor elements and the positive conductors Bi+ and B2+ are laminated on the outside (each having the negative conductor between itself and the capacitor elements) but in other embodiments it may be the other way around with the positive conductors facing the capacitor elements and the negative conductors on the outside.
  • any other design with laminated busbars is also possible, e.g. with the busbars extending in the middle with each of the first and second pluralities of capacitor elements facing outwards, away from each other. Since also the outer conductor (the positive conductor in figure lb) is connected to each capacitor element in the plurality of capacitor elements, holes may be provided in the inner conductor (the negative conductor in figure lb) for allowing the outer conductor access to the capacitor elements.
  • the first and second busbars Bi and B2, as connected to the first and second pluralities of capacitor elements Ci and C2 are arranged to be mirror-symmetrical in the PEBB 1.
  • the total equivalent series inductance of the capacitor arrangement C may be reduced.
  • Parallel connected capacitor elements may be used to obtain the required total capacitance of the capacitor arrangement.
  • the design of the PEBB may also be made more compact (see figure lb), compared with if only one (longer) busbar was used.
  • FIG. 2 illustrates an embodiment of a semiconductor switch Si.
  • each switch e.g. of S1-S4 of figure la
  • the semiconductor devices may be provided in modules, e.g. the three parallel connected semiconductor modules Sia, Sib and Sic in figure 2.
  • each semiconductor module comprises a full-bridge configuration of
  • semiconductor devices D and any number of such modules may be connected in parallel depending on the intended use of the semiconductor switch Si.
  • the semiconductor modules may comprise other configurations of semiconductor devices than full-bridge, e.g. half- bridge or three-level.
  • Parallel connection of e.g. SiC modules Sia-c may be a scenario for SiC PEBBs 1 in order to increase the rated PEBB current.
  • Current stress balancing for each parallel-connected SiC module, as well as for the semiconductor devices inside each SiC module may be more challenging considering the high di/dt capability of the SiC devices.
  • Current balancing improvements may be achieved with more evenly balanced loop-inductance between SiC devices and the capacitor elements.
  • each module Sia-c similar total equivalent loop-inductance considering the capacitor elements. Further reduction and equalization of the loop inductance experienced by each semiconductor device may be achieved by limiting the difference in physical location of the SiC module terminals (one of which is marked as reference T in figure 2).
  • the modules Sia-c are preferably located close together and at substantially the same (reduced) distance from the capacitor elements to provide equal/balanced and reduced parasitic conditions, e.g. commutation loop inductance, experienced by the semiconductor devices D.
  • each of the semiconductor switches S1-S4 comprises a plurality of identical parallel connected semiconductor modules Sia-Sic, e.g. each comprising semiconductor devices D in half-bridge or full-bridge configuration.
  • each of the semiconductor switches S1-S4 comprises a SiC device D.
  • the semiconductor switches S1-S4 are in half-bridge or full-bridge configuration.
  • each of the semiconductor switches S1-S4 comprises a MOSFET D.
  • the PEBB 1 has a voltage rating of at least 10 kV. In some embodiments of the present invention, the PEBB 1 has a current rating of at least 1 kA.
  • each capacitor element C11-C16 and C21-C26 has a capacitance within the range of 100-500 ⁇ .
  • the PEBB 1 is for an MMC. In some embodiments of the present invention, the PEBB 1 is for a

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)

Abstract

La présente invention concerne un bloc de construction d'électronique de puissance (PEBB) (1) destiné à un convertisseur de courant. Le PEBB comprend un agencement de commutateurs à semi-conducteurs (S) comprenant une pluralité de commutateurs à semi-conducteurs (S1-S4), un agencement de condensateurs (C), et un agencement de barres omnibus (B), connectant l'agencement de condensateurs à l'agencement de commutateurs à semi-conducteurs. L'agencement de barres omnibus comprend une première barre omnibus stratifiée (B1) connectant une première pluralité d'éléments de condensateur (C11-C14) de l'agencement de condensateurs à l'agencement de commutateurs à semi-conducteurs, et une seconde barre omnibus stratifiée (B2) connectant une seconde pluralité d'éléments de condensateur (C21-C24) de l'agencement de condensateurs à l'agencement de commutateurs à semi-conducteurs. Chacune des première et seconde barres omnibus stratifiées comprend un conducteur positif B1 + ou B2 + stratifié sur un conducteur négatif B1 - ou B2 -, chacun étant connecté à chaque élément de la pluralité d'éléments de condensateur (C11-C14) ou (C21-C24).
PCT/EP2017/052838 2017-02-09 2017-02-09 Conception de bloc de construction d'électronique de puissance à haute tension WO2018145746A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/EP2017/052838 WO2018145746A1 (fr) 2017-02-09 2017-02-09 Conception de bloc de construction d'électronique de puissance à haute tension

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2017/052838 WO2018145746A1 (fr) 2017-02-09 2017-02-09 Conception de bloc de construction d'électronique de puissance à haute tension

Publications (2)

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WO2018145746A1 true WO2018145746A1 (fr) 2018-08-16
WO2018145746A8 WO2018145746A8 (fr) 2018-10-11

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109193581A (zh) * 2018-09-18 2019-01-11 国网天津市电力公司 考虑静止同步串联补偿器接入的输电线路距离保护方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020034089A1 (en) * 2000-09-06 2002-03-21 Hitachi, Ltd. Semiconductor electric power conversion device
DE102015223002A1 (de) * 2014-11-28 2016-06-02 Hitachi, Ltd. Leistungsumsetzungsvorrichtung und Eisenbahnfahrzeug mit derselben

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020034089A1 (en) * 2000-09-06 2002-03-21 Hitachi, Ltd. Semiconductor electric power conversion device
DE102015223002A1 (de) * 2014-11-28 2016-06-02 Hitachi, Ltd. Leistungsumsetzungsvorrichtung und Eisenbahnfahrzeug mit derselben

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109193581A (zh) * 2018-09-18 2019-01-11 国网天津市电力公司 考虑静止同步串联补偿器接入的输电线路距离保护方法

Also Published As

Publication number Publication date
WO2018145746A8 (fr) 2018-10-11

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