[go: up one dir, main page]

WO2018152819A1 - Cmos image sensor with dual sensitivity pixel - Google Patents

Cmos image sensor with dual sensitivity pixel Download PDF

Info

Publication number
WO2018152819A1
WO2018152819A1 PCT/CN2017/074890 CN2017074890W WO2018152819A1 WO 2018152819 A1 WO2018152819 A1 WO 2018152819A1 CN 2017074890 W CN2017074890 W CN 2017074890W WO 2018152819 A1 WO2018152819 A1 WO 2018152819A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
image sensor
cmos image
sensor according
sequence unit
Prior art date
Application number
PCT/CN2017/074890
Other languages
French (fr)
Inventor
Makoto Monoi
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/CN2017/074890 priority Critical patent/WO2018152819A1/en
Priority to CN201780004997.XA priority patent/CN108476298B/en
Publication of WO2018152819A1 publication Critical patent/WO2018152819A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/813—Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/58—Control of the dynamic range involving two or more exposures
    • H04N25/581—Control of the dynamic range involving two or more exposures acquired simultaneously
    • H04N25/585—Control of the dynamic range involving two or more exposures acquired simultaneously with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H10F39/8023—Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/805—Coatings
    • H10F39/8053—Colour filters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/806—Optical elements or arrangements associated with the image sensors
    • H10F39/8063—Microlenses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors

Definitions

  • the present invention relates to the field of an image sensor, in particular, a high dynamic range complementary metal oxide semiconductor (CMOS) image sensor.
  • CMOS complementary metal oxide semiconductor
  • Fig. 1 shows a circuit diagram of a pixel circuit of the prior art.
  • Fig. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate, and Fig. 3 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2.
  • PD a photodiode where light is converted to signal electron
  • PD-L a high sensitivity photodiode
  • PD-S a low sensitivity photodiode
  • TG a transfer gate that transfers signal charge to FD
  • FD a floating diffusion where signal charge is converted to signal voltage
  • Cfd capacitance of FD
  • RS a reset gate that sets the voltage of FD
  • AMP an amplifier transistor that converts signal voltage of FD to a low impedance output signal
  • SL a selector transistor
  • ADC an analog digital converter
  • G-L a large micro lens for Green PD-L
  • G-S a small micro lens for Green PD-S
  • B-L a large micro lens for Blue PD-L
  • B-S a small micro lens for Blue PD-S
  • R-L a large micro lens for Red PD-L
  • R-S a small micro lens for Red PD-S
  • the PD converts light into an electrical signal.
  • the electrical signal is selectively transmitted to the FD via the TG.
  • the FD is connected to a gate of the AMP, and an output signal is transmitted to the signal line via the SL. Accordingly, if gates of the TG and the SL are turned on, the output signal corresponding to the electrical signal from the PD is obtained on the signal line.
  • the RS selectively resets an electrical charge accumulated in the FD.
  • Fig. 2 shows four pairs of PD-L and PD-S.
  • the FD is shown as a small black square between PD-L and PD-S which are paired.
  • PD-S paired with PD-L is located at the lower right of PD-L, they have filters with the same color, and PD-L and PD-S have large micro lens and small micro lens on the filters, respectively, as shown in Fig. 3.
  • the arrangement of colors is based on a Bayer arrangement.
  • Fig. 4 shows a circuit diagram of a pixel circuit of a general single sensitivity pixel
  • Fig. 5 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • PD-1 and PD-2 share an output circuit (Fig. 4) , and they have filters with different colors, such as G and R, or B and G (Fig. 5) .
  • Pixel structures of high dynamic range CMOS image sensors having dual sensitivity is provided.
  • CMOS image sensor includes:
  • pixel units each of which includes a photodiode (PD) and a transfer gate (TG) ;
  • a pixel sequence unit including two pixel sequences which are adjacent and arranged at an angle of 45 degrees;
  • an output circuit sequence including a plurality of output circuits which are arranged at an angle of 45 degrees on a line
  • the PD1 and PD2 have the same spectral sensitivity characteristic, and the sensitivities of the PD1 and PD2 are not the same, and
  • the pixel sequence unit and the output circuit sequence are alternately arranged.
  • the CMOS image sensor includes color filters with the same spectral sensitivity characteristic on the PD1 and PD2.
  • the CMOS image sensor includes micro lens with different light collection rates on the PD1 and PD2.
  • the CMOS image sensor includes a floating diffusion which is connected to the TG and accumulates charge generated at the PD and transferred via the TG, wherein the PD1 and PD2 share one FD.
  • a pixel pair adjacent to a pixel pair PD1n and PD2n in a pixel sequence unit comprises a pixel pair PD1m and PD2m located at the upper side of the PD1n and PD2n in the oblique direction in the pixel sequence unit.
  • a pixel pair adjacent to a pixel pair PD1n and PD2n in a pixel sequence unit comprises a pixel pair PD1k and PD2k located in the horizontal direction of the PD1n and PD2n in the pixel sequence unit.
  • the PD1n, PD2n, PD1m, and PD2m share one FD.
  • the PD1n and PD2n share one FDn
  • the PD1k and PD2k share one FDk
  • the FDn and FDk are electrically connected.
  • the deep trench isolation is used for the insulators between the PDs from the entrance plane of the substrate to at least part of the way toward the opposite side.
  • the element isolation regions between the PDs become wide from the entrance plane of the substrate toward the opposite side.
  • a CMOS image sensor is provided according to the various implementation manners to shrink the pixel pitch of dual sensitivity pixel while keeping enough amount of signal and small crosstalk.
  • FIG. 1 shows a circuit diagram of a pixel circuit of the prior art
  • FIG. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 3 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2;
  • FIG. 4 shows a circuit diagram of a pixel circuit of a general single sensitivity pixel
  • FIG. 5 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 6 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 8A shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 7;
  • FIG. 8B shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2;
  • FIG. 9 shows another embodiment having insulator isolation between PDs
  • FIG. 10 shows a view of the micro lens and DTI from the back of the substrate
  • FIG. 11 shows another embodiment having another layout of insulator isolation
  • FIG. 12 shows a view of the micro lens and DTI from the back of the substrate
  • FIG. 13 shows another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6;
  • FIG. 14 shows yet another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6;
  • FIG. 15 shows an example in which photodiode layout is same as Fig. 6 and micro lens and color filter layout are same as Fig. 2;
  • FIG. 16 shows a circuit diagram of a four photodiode shared pixel circuit according to an embodiment
  • FIG. 17 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • Fig. 6 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention
  • Fig. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • a CMOS image sensor includes pixel units, each of which includes a PD and a TG; pixel sequences in which the pixel units are arranged on a line; a pixel sequence unit including two pixel sequences which are adjacent and arranged at an angle of 45 degrees; output circuits which convert charge generated at the PD into an output signal; and an output circuit sequence including a plurality of output circuits which are arranged at an angle of 45 degrees on a line.
  • the pixel sequence unit and the output circuit sequence are alternately arranged.
  • PDs in a thick line area share one output circuit that consists of RS, FD, AMP, and SL.
  • Four (2x2) PDs and TGs share one FD (a small black square shown in Fig. 7) .
  • the upper four PDs in the thick line area in Fig. 7 can be said to be a pixel pair PD1n and PD2n in a pixel sequence unit, and an adjacent pixel pair PD1m and PD2m located at the upper side of the PD1n and PD2n in the oblique direction in the pixel sequence unit.
  • the PD1n, PD2n, PD1m, and PD2m correspond to the PDs with G-L, G-S, R-S, and R-L, respectively, in the upper four PDs in the thick line area.
  • the PD1n, PD2n, PD1m, and PD2m share one FD.
  • Two FDs in the thick line area are connected to one AMP. Namely, skewed two photodiode rows and skewed one transistor row is repeated in a CMOS image sensor.
  • Adjacent PD-L and PD-Sin a pixel sequence unit form a pixel pair.
  • one of PD-L and PD-S generates photoelectronic conversion electron 1a for light with a predetermined wave length a
  • photoelectronic conversion electron 1b for light with a predetermined wave length b
  • the other of PD-L and PD-S generates photoelectronic conversion electron 2a for light with a predetermined wave length a
  • photoelectronic conversion electron 2b for light with a predetermined wave length b the PDs used herein have the characteristic such that 1a/1b is approximately identical to 2a/2b, and 1a is not equal to 2a and 1b is not equal to 2b.
  • the PD-L and PD-S have the same spectral sensitivity characteristic, and the sensitivities of the PD-L and PD-S are not the same.
  • the right PD has a red color filter and a large micro lens (R-L)
  • the left PD has a green color filter and a large micro lens (G-L)
  • the upper PD has a red color filter and a small micro lens (R-S)
  • the lower PD has a green color filter and a small micro lens (G-S)
  • the right PD has a red color filter and a large micro lens (R-L)
  • the left PD has a green color filter and a large micro lens (G-L)
  • the upper PD has a red color filter and a small micro lens (R-S)
  • the lower PD has a green color filter and a small micro lens (G-S) .
  • the arrangement of colors is not limited to a Bayer arrangement. Color filters with the same spectral sensitivity characteristic and micro lens with different light collection rates are provided on a Bayer arrangement.
  • the number of pixel transistors per color is 2.75 (11 transistors for 4 colors) in the constitution shown in Figs. 6 and 7, while that in the prior art (Fig. 1) is 5 (5 transistors for 1 color) . So pixel pitch becomes smaller. Assuming that the pixel pitch is 1 in the single sensitivity (Fig. 4) , the pixel pitch in the prior art of dual sensitivity (Fig. 2) is approximately 1.4 (square root of 2) , and the pixel pitch in the embodiment of the present invention (Fig. 7) is approximately 1.15 (an actual measurement) .
  • R-Sand B-Sare located at the upper left of R-L and B-L, respectively, while in Fig. 2, R-S and B-S are located at the lower right of R-L and B-L. This is to add charge signals of R-S and R-L to those of G-L and G-S at the shared FD, and add charge signals of B-S and B-L to those of G-L and G-S at the shared FD.
  • Fig. 8A shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 7.
  • Back side illumination (BSI) is adopted to increase sensitivity and decrease crosstalk.
  • the color filters and the micro lens are located on the back of a substrate.
  • Fig. 8B shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2. Comparing Figs. 8A and 8B, light comes from the upper side in Fig. 8B while from the bottom side in Fig. 8A. In Fig. 8B, light is reflected at the gates and metal wires (not shown) between the color filters and the surface of the silicon substrate. So sensitivity decrease or crosstalk increase.
  • the width of ISO can be narrower at the entrance plane in Fig. 8A, because at the entrance plane side, there is no gate or metal wire.
  • the width of insulators between PDs on the back of the substrate is narrower than that of transistors. This also makes crosstalk smaller. Thus, in these embodiments, pixel pitch can be reduced.
  • Fig. 9 shows another embodiment having insulator isolation between PDs.
  • Deep trench isolation DTI
  • the deep trench isolation is used for the insulators between the PDs from the entrance plane of the substrate to at least part of the way toward the opposite side. This decreases crosstalk between photodiodes.
  • Fig. 10 shows a view of the micro lens and DTI (black area) from the back of the substrate.
  • the DTI layout is repetition of a simple square shape.
  • Fig. 11 shows another embodiment having another layout of insulator isolation.
  • the element isolation regions between the PDs become wide from the entrance plane of the substrate toward the opposite side.
  • Fig. 12 shows a view of the micro lens and DTI (black area) from the back of the substrate. DTI area is different according to micro lens area. Because aperture of DTI and micro lens are substantially the same, crosstalk is smaller.
  • Fig. 13 shows another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6.
  • PD-L and PD-S face each other, and share one FD.
  • Eight PDs in a thick line area share one output circuit.
  • the faced pixels are paired, and have color filters with the same color.
  • PD-L has a large micro lens
  • PD-S has a small micro lens. Every four pairs in the vertical direction are grouped, and share an output circuit.
  • a transistor area is provided along a side of a pair of pixels for each two pairs in a group.
  • the number of pairs in each group is not limited to four, and the pairs in the horizontal direction may be grouped.
  • FIG. 14 shows yet another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6.
  • Eight PDs in a thick line area share one output circuit.
  • every four pairs in the vertical direction are grouped, and a transistor area is provided along a side of a pair of pixels for each two pairs in a group.
  • FDs are located in line in the oblique direction.
  • the FD is arranged at one end of the side where the pixels are adjacent
  • the FD is arranged at another end of the side where the pixels are adjacent. Comparing the areas of PDs in Figs. 7, 13, and 14, the area of PD in Fig. 7 > the area of PD in Fig. 14 > the area of PD in Fig. 13.
  • Fig. 15 shows an example in which photodiode layout is same as Fig. 6 and micro lens and color filter layout are same as Fig. 2.
  • Eight PDs in a thick line area share one output circuit.
  • charge binning of PD-L and PD-S is not available, because PD-S with R-S is located at the lower right of PD-L with R-L instead of the upper left, and PD-S with B-S is located at the lower right of PD-L with B-L instead of the upper left.
  • Fig. 16 shows a circuit diagram of a four photodiode shared pixel circuit according to an embodiment.
  • Fig. 17 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • Four PDs in a thick line area share one output circuit.
  • Four PDs in the thick line area can be said to be a pixel pair PD1n and PD2n in a pixel sequence unit, and an adjacent pixel pair PD1k and PD2k located in the horizontal direction of the PD1n and PD2n in the pixel sequence unit.
  • the PD1n, PD2n, PD1k, and PD2k correspond to the PDs with G-L, G-S, R-L, and R-S, respectively, in the thick line area.
  • the PD1n and PD2n share one FDn (a small black square between the PD1n and PD2n)
  • the PD1k and PD2k share one FDk (a small black square between the PD1k and PD2k)
  • the FDn and FDk are electrically connected.
  • every two pairs in the horizontal direction are grouped.
  • a transistor area is provided along a side of a pair of pixels for said each two pairs. This pixel pitch is smaller than that of the prior art, but bigger than the eight photodiode shared pixel circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

The present invention provides a CMOS image sensor includes: pixel units, each of which includes a PD and a TG; pixel sequences in which the pixel units are arranged on a line; a pixel sequence unit including two pixel sequences which are adjacent and arranged at an angle of 45 degrees; output circuits which convert charge generated at the PD into an output signal; and an output circuit sequence including a plurality of output circuits which are arranged at an angle of 45 degrees on a line, wherein adjacent PD1 and PD2 in a pixel sequence unit form a pixel pair, the PD1 and PD2 have the same spectral sensitivity characteristic, and the sensitivities of the PD1 and PD2 are not the same, and the pixel sequence unit and the output circuit sequence are alternately arranged. The present invention achieves to shrink the pixel pitch of dual sensitivity pixel while keeping enough amount of signal and small crosstalk.

Description

CMOS IMAGE SENSOR WITH DUAL SENSITIVITY PIXEL TECHNICAL FIELD
The present invention relates to the field of an image sensor, in particular, a high dynamic range complementary metal oxide semiconductor (CMOS) image sensor.
BACKGROUND
Dual sensitivity pixels increase dynamic range of an image sensor, as can be seen from, for example, Japanese Unexamined Patent Application, First Publication No. 2008-99073. Fig. 1 shows a circuit diagram of a pixel circuit of the prior art. Fig. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate, and Fig. 3 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2. The meaning of the abbreviations are as follows: PD: a photodiode where light is converted to signal electron, PD-L: a high sensitivity photodiode, PD-Sa low sensitivity photodiode, TG: a transfer gate that transfers signal charge to FD, FD: a floating diffusion where signal charge is converted to signal voltage, Cfd: capacitance of FD, RS: a reset gate that sets the voltage of FD, AMP: an amplifier transistor that converts signal voltage of FD to a low impedance output signal, SL: a selector transistor, ADC: an analog digital converter, G-L: a large micro lens for Green PD-L, G-S: a small micro lens for Green PD-S, B-L: a large micro lens for Blue PD-L, B-S: a small micro lens for Blue PD-S, R-L: a large micro lens for Red PD-L, R-S: a small micro lens for Red PD-S, ISO: pixel isolation by implant.
Referring to Figs. 1, PD-L and PD-Sare paired, and share an output circuit that consists of RS, FD, AMP, and SL. The PD converts light into an electrical signal. The electrical signal is selectively transmitted to the FD via the TG. The FD is connected to a gate of the AMP, and an output signal is transmitted to the signal line via the SL. Accordingly, if gates of the TG and the SL are turned on, the output signal corresponding to the electrical signal from the PD is obtained on the signal line. The RS selectively resets an electrical charge accumulated in the FD. Fig. 2 shows four pairs of PD-L and PD-S. The FD is shown as a small black square between PD-L and PD-S which are paired. PD-S paired with PD-L is located at the lower right of PD-L, they have filters with the same color, and PD-L and PD-S have large micro lens and small micro lens on the filters, respectively, as shown in Fig. 3. In Fig. 2, the arrangement of colors is based on a Bayer arrangement.
Fig. 4 shows a circuit diagram of a pixel circuit of a general single sensitivity pixel, and Fig. 5 shows a top view of the pixel circuit arranged on a surface of a silicon substrate. PD-1 and PD-2 share an output circuit (Fig. 4) , and they have filters with different colors, such as G and R, or B and G (Fig. 5) .
Comparing Fig. 5 and Fig. 2, because a dual sensitivity pixel requires two PDs for one color, so the pixel pitch between different colors becomes about 1.4 (square root of 2) times as long as that of a single sensitivity pixel. This bigger pixel pitch is problem.
SUMMARY
Pixel structures of high dynamic range CMOS image sensors having dual sensitivity is provided.
According to a first aspect, a CMOS image sensor is provided, where the CMOS image sensor includes:
pixel units, each of which includes a photodiode (PD) and a transfer gate (TG) ；
pixel sequences in which the pixel units are arranged on a line；
a pixel sequence unit including two pixel sequences which are adjacent and arranged at an angle of 45 degrees；
output circuits which convert charge generated at the PD into an output signal； and
an output circuit sequence including a plurality of output circuits which are arranged at an angle of 45 degrees on a line,
wherein adjacent PD1 and PD2 in a pixel sequence unit form a pixel pair,
the PD1 and PD2 have the same spectral sensitivity characteristic, and the sensitivities of the PD1 and PD2 are not the same, and
the pixel sequence unit and the output circuit sequence are alternately arranged.
In a first possible implementation manner of the first aspect, the CMOS image sensor includes color filters with the same spectral sensitivity characteristic on the PD1 and PD2.
With reference to the first aspect, in a second possible implementation manner of the first aspect, the CMOS image sensor includes micro lens with different light collection rates on the PD1 and PD2.
With reference to the first aspect, in a third possible implementation manner of the first aspect, the CMOS image sensor includes a floating diffusion which is connected to the TG and accumulates charge generated at the PD and transferred via the TG, wherein the PD1 and PD2 share one FD.
With reference to the first aspect, in a fourth possible implementation manner of the first  aspect, a pixel pair adjacent to a pixel pair PD1n and PD2n in a pixel sequence unit comprises a pixel pair PD1m and PD2m located at the upper side of the PD1n and PD2n in the oblique direction in the pixel sequence unit.
With reference to the first aspect, in a fifth possible implementation manner of the first aspect, a pixel pair adjacent to a pixel pair PD1n and PD2n in a pixel sequence unit comprises a pixel pair PD1k and PD2k located in the horizontal direction of the PD1n and PD2n in the pixel sequence unit.
With reference to fourth possible implementation manner of the first aspect, in a sixth possible implementation manner of the first aspect, the PD1n, PD2n, PD1m, and PD2m share one FD.
With reference to the fifth possible implementation manner of the first aspect, in a seventh possible implementation manner of the third aspect, the PD1n and PD2n share one FDn, the PD1k and PD2k share one FDk, and the FDn and FDk are electrically connected.
With reference to the first aspect, in an eighth possible implementation manner of the first aspect, the deep trench isolation is used for the insulators between the PDs from the entrance plane of the substrate to at least part of the way toward the opposite side.
With reference to the first aspect or the eighth possible implementation manner of the first aspect, in a ninth possible implementation manner of the third aspect, the element isolation regions between the PDs become wide from the entrance plane of the substrate toward the opposite side.
A CMOS image sensor is provided according to the various implementation manners to shrink the pixel pitch of dual sensitivity pixel while keeping enough amount of signal and small crosstalk.
BRIEF DESCRIPTION OF DRAWINGS
To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
FIG. 1 shows a circuit diagram of a pixel circuit of the prior art；
FIG. 2 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；
FIG. 3 shows a cross sectional view of the pixel circuit arranged on the silicon substrate  along an arrow in Fig. 2；
FIG. 4 shows a circuit diagram of a pixel circuit of a general single sensitivity pixel；
FIG. 5 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；
FIG. 6 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention；
FIG. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；
FIG. 8A shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 7；
FIG. 8B shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2；
FIG. 9 shows another embodiment having insulator isolation between PDs；
FIG. 10 shows a view of the micro lens and DTI from the back of the substrate；
FIG. 11 shows another embodiment having another layout of insulator isolation；
FIG. 12 shows a view of the micro lens and DTI from the back of the substrate；
FIG. 13 shows another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6；
FIG. 14 shows yet another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6；
FIG. 15 shows an example in which photodiode layout is same as Fig. 6 and micro lens and color filter layout are same as Fig. 2；
FIG. 16 shows a circuit diagram of a four photodiode shared pixel circuit according to an embodiment； and
FIG. 17 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
DESCRIPTION OF EMBODIMENTS
The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
Fig. 6 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention, and Fig. 7 shows a top view of the pixel circuit arranged on a surface of a silicon substrate. A CMOS image sensor includes pixel units, each of which includes a PD and a TG； pixel  sequences in which the pixel units are arranged on a line； a pixel sequence unit including two pixel sequences which are adjacent and arranged at an angle of 45 degrees； output circuits which convert charge generated at the PD into an output signal； and an output circuit sequence including a plurality of output circuits which are arranged at an angle of 45 degrees on a line. The pixel sequence unit and the output circuit sequence are alternately arranged. In Fig. 7, eight PDs in a thick line area share one output circuit that consists of RS, FD, AMP, and SL. Four (2x2) PDs and TGs share one FD (a small black square shown in Fig. 7) . The upper four PDs in the thick line area in Fig. 7 can be said to be a pixel pair PD1n and PD2n in a pixel sequence unit, and an adjacent pixel pair PD1m and PD2m located at the upper side of the PD1n and PD2n in the oblique direction in the pixel sequence unit. The PD1n, PD2n, PD1m, and PD2m correspond to the PDs with G-L, G-S, R-S, and R-L, respectively, in the upper four PDs in the thick line area. The PD1n, PD2n, PD1m, and PD2m share one FD. Two FDs in the thick line area are connected to one AMP. Namely, skewed two photodiode rows and skewed one transistor row is repeated in a CMOS image sensor.
Adjacent PD-L and PD-Sin a pixel sequence unit form a pixel pair. Assuming that one of PD-L and PD-S generates photoelectronic conversion electron 1a for light with a predetermined wave length a, and photoelectronic conversion electron 1b for light with a predetermined wave length b, and the other of PD-L and PD-S generates photoelectronic conversion electron 2a for light with a predetermined wave length a, and photoelectronic conversion electron 2b for light with a predetermined wave length b, the PDs used herein have the characteristic such that 1a/1b is approximately identical to 2a/2b, and 1a is not equal to 2a and 1b is not equal to 2b. Namely, the PD-L and PD-S have the same spectral sensitivity characteristic, and the sensitivities of the PD-L and PD-S are not the same.
In Fig. 7, in the upper four PDs in the thick line area, the right PD has a red color filter and a large micro lens (R-L) , the left PD has a green color filter and a large micro lens (G-L) , the upper PD has a red color filter and a small micro lens (R-S) , and the lower PD has a green color filter and a small micro lens (G-S) , and in the lower four PDs in the thick line area, the right PD has a red color filter and a large micro lens (R-L) , the left PD has a green color filter and a large micro lens (G-L) , the upper PD has a red color filter and a small micro lens (R-S) , and the lower PD has a green color filter and a small micro lens (G-S) . The arrangement of colors is not limited to a Bayer arrangement. Color filters with the same spectral sensitivity characteristic and micro lens with different light collection rates are provided on PD-L and PD-S in a pixel pair.
The number of pixel transistors per color is 2.75 (11 transistors for 4 colors) in the constitution shown in Figs. 6 and 7, while that in the prior art (Fig. 1) is 5 (5 transistors for 1 color) . So pixel pitch becomes smaller. Assuming that the pixel pitch is 1 in the single sensitivity (Fig. 4) ,  the pixel pitch in the prior art of dual sensitivity (Fig. 2) is approximately 1.4 (square root of 2) , and the pixel pitch in the embodiment of the present invention (Fig. 7) is approximately 1.15 (an actual measurement) .
In Fig. 7, R-Sand B-Sare located at the upper left of R-L and B-L, respectively, while in Fig. 2, R-S and B-S are located at the lower right of R-L and B-L. This is to add charge signals of R-S and R-L to those of G-L and G-S at the shared FD, and add charge signals of B-S and B-L to those of G-L and G-S at the shared FD.
Fig. 8A shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 7. Back side illumination (BSI) is adopted to increase sensitivity and decrease crosstalk. The color filters and the micro lens are located on the back of a substrate. Fig. 8B shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 2. Comparing Figs. 8A and 8B, light comes from the upper side in Fig. 8B while from the bottom side in Fig. 8A. In Fig. 8B, light is reflected at the gates and metal wires (not shown) between the color filters and the surface of the silicon substrate. So sensitivity decrease or crosstalk increase. The width of ISO can be narrower at the entrance plane in Fig. 8A, because at the entrance plane side, there is no gate or metal wire. As can be seen from Fig. 8A, the width of insulators between PDs on the back of the substrate is narrower than that of transistors. This also makes crosstalk smaller. Thus, in these embodiments, pixel pitch can be reduced.
Fig. 9 shows another embodiment having insulator isolation between PDs. Deep trench isolation (DTI) is adopted. The deep trench isolation is used for the insulators between the PDs from the entrance plane of the substrate to at least part of the way toward the opposite side. This decreases crosstalk between photodiodes.
Fig. 10 shows a view of the micro lens and DTI (black area) from the back of the substrate. The DTI layout is repetition of a simple square shape.
Fig. 11 shows another embodiment having another layout of insulator isolation. The element isolation regions between the PDs become wide from the entrance plane of the substrate toward the opposite side. Fig. 12 shows a view of the micro lens and DTI (black area) from the back of the substrate. DTI area is different according to micro lens area. Because aperture of DTI and micro lens are substantially the same, crosstalk is smaller.
Fig. 13 shows another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6. PD-L and PD-S face each other, and share one FD. Eight PDs in a thick line area share one output circuit. The faced pixels are paired, and have color filters with the same color. PD-L has a large micro lens, and PD-S has a small micro lens. Every four pairs in the vertical direction are grouped, and share an output circuit. In Fig. 13, a transistor area is provided along a side of a pair of  pixels for each two pairs in a group. The number of pairs in each group is not limited to four, and the pairs in the horizontal direction may be grouped. Fig. 14 shows yet another embodiment of an eight photodiode shared pixel circuit shown in Fig. 6. Eight PDs in a thick line area share one output circuit. In the same way as Fig. 13, every four pairs in the vertical direction are grouped, and a transistor area is provided along a side of a pair of pixels for each two pairs in a group. In Fig. 14, FDs are located in line in the oblique direction. Compared with the pixel circuit in Fig. 13, for the first and the third pairs of pixels in each group, the FD is arranged at one end of the side where the pixels are adjacent, and for the second and the fourth pairs of pixels in each group, the FD is arranged at another end of the side where the pixels are adjacent. Comparing the areas of PDs in Figs. 7, 13, and 14, the area of PD in Fig. 7 > the area of PD in Fig. 14 > the area of PD in Fig. 13.
Fig. 15 shows an example in which photodiode layout is same as Fig. 6 and micro lens and color filter layout are same as Fig. 2. Eight PDs in a thick line area share one output circuit. In this case, charge binning of PD-L and PD-S is not available, because PD-S with R-S is located at the lower right of PD-L with R-L instead of the upper left, and PD-S with B-S is located at the lower right of PD-L with B-L instead of the upper left.
Fig. 16 shows a circuit diagram of a four photodiode shared pixel circuit according to an embodiment. Fig. 17 shows a top view of the pixel circuit arranged on a surface of a silicon substrate. Four PDs in a thick line area share one output circuit. Four PDs in the thick line area can be said to be a pixel pair PD1n and PD2n in a pixel sequence unit, and an adjacent pixel pair PD1k and PD2k located in the horizontal direction of the PD1n and PD2n in the pixel sequence unit. The PD1n, PD2n, PD1k, and PD2k correspond to the PDs with G-L, G-S, R-L, and R-S, respectively, in the thick line area. The PD1n and PD2n share one FDn (a small black square between the PD1n and PD2n) , the PD1k and PD2k share one FDk (a small black square between the PD1k and PD2k) , and the FDn and FDk are electrically connected. Different from Fig. 13, every two pairs in the horizontal direction are grouped. A transistor area is provided along a side of a pair of pixels for said each two pairs. This pixel pitch is smaller than that of the prior art, but bigger than the eight photodiode shared pixel circuit.
What is disclosed above is merely exemplary embodiments of the present invention, and certainly is not intended to limit the scope of protection of the present invention. A person of ordinary skill in the art may understand that all or some of the processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims (10)

  1. A complementary metal oxide semiconductor (CMOS) image sensor, comprising:
    pixel units, each of which includes a photodiode (PD) and a transfer gate (TG) ；
    pixel sequences in which the pixel units are arranged on a line；
    a pixel sequence unit including two pixel sequences which are adjacent and arranged at an angle of 45 degrees；
    output circuits which convert charge generated at the PD into an output signal； and
    an output circuit sequence including a plurality of output circuits which are arranged at an angle of 45 degrees on a line,
    wherein adjacent PD1 and PD2 in a pixel sequence unit form a pixel pair,
    the PD1 and PD2 have the same spectral sensitivity characteristic, and the sensitivities of the PD1 and PD2 are not the same, and
    the pixel sequence unit and the output circuit sequence are alternately arranged.
  2. The CMOS image sensor according to claim 1, comprising color filters with the same spectral sensitivity characteristic on the PD1 and PD2.
  3. The CMOS image sensor according to claim 1, comprising micro lens with different light collection rates on the PD1 and PD2.
  4. The CMOS image sensor according to claim 1, comprising a floating diffusion which is connected to the TG and accumulates charge generated at the PD and transferred via the TG, wherein the PD1 and PD2 share one FD.
  5. The CMOS image sensor according to claim 1, wherein a pixel pair adjacent to a pixel pair PD1n and PD2n in a pixel sequence unit comprises a pixel pair PD1m and PD2m located at the upper side of the PD1n and PD2n in the oblique direction in the pixel sequence unit.
  6. The CMOS image sensor according to claim 1, wherein a pixel pair adjacent to a pixel pair PD1n and PD2n in a pixel sequence unit comprises a pixel pair PD1k and PD2k located in the horizontal direction of the PD1n and PD2n in the pixel sequence unit.
  7. The CMOS image sensor according to claim 5, wherein the PD1n, PD2n, PD1m, and PD2m share one FD.
  8. The CMOS image sensor according to claim 6, the PD1n and PD2n share one FDn, the PD1k and PD2k share one FDk, and the FDn and FDk are electrically connected.
  9. The CMOS image sensor according to claim 1, wherein the deep trench isolation is used for the insulators between the PDs from the entrance plane of the substrate to at least part of the way  toward the opposite side.
  10. The CMOS image sensor according to claim 1 or 9, wherein the element isolation regions between the PDs become wide from the entrance plane of the substrate toward the opposite side.
PCT/CN2017/074890 2017-02-25 2017-02-25 Cmos image sensor with dual sensitivity pixel WO2018152819A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/074890 WO2018152819A1 (en) 2017-02-25 2017-02-25 Cmos image sensor with dual sensitivity pixel
CN201780004997.XA CN108476298B (en) 2017-02-25 2017-02-25 Dual sensitive pixel CMOS image sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/074890 WO2018152819A1 (en) 2017-02-25 2017-02-25 Cmos image sensor with dual sensitivity pixel

Publications (1)

Publication Number Publication Date
WO2018152819A1 true WO2018152819A1 (en) 2018-08-30

Family

ID=63254119

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/074890 WO2018152819A1 (en) 2017-02-25 2017-02-25 Cmos image sensor with dual sensitivity pixel

Country Status (2)

Country Link
CN (1) CN108476298B (en)
WO (1) WO2018152819A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109659329A (en) * 2019-01-25 2019-04-19 上海晔芯电子科技有限公司 Imaging sensor with shared structure pixel layout

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008099073A (en) * 2006-10-13 2008-04-24 Sony Corp Solid imaging device and imaging device
CN102098456A (en) * 2009-12-15 2011-06-15 株式会社东芝 Solid-state imaging device which can expand dynamic range
CN102157536A (en) * 2010-01-28 2011-08-17 索尼公司 Solid-state imaging device and electronic apparatus

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1225897C (en) * 2002-08-21 2005-11-02 佳能株式会社 camera device
KR100619396B1 (en) * 2003-12-31 2006-09-11 동부일렉트로닉스 주식회사 CMOS Image sensor and its fabricating method
JP2008060380A (en) * 2006-08-31 2008-03-13 Matsushita Electric Ind Co Ltd Solid-state imaging device and manufacturing method thereof
JP2009272596A (en) * 2008-04-09 2009-11-19 Sony Corp Solid-state imaging device, method of manufacturing the same, and electronic instrument
JP2010283145A (en) * 2009-06-04 2010-12-16 Sony Corp Solid-state imaging device, manufacturing method thereof, and electronic apparatus
JP2012028459A (en) * 2010-07-21 2012-02-09 Sony Corp Semiconductor device, solid state imaging device, manufacturing method of semiconductor device, manufacturing method of solid state imaging device, and electronic apparatus
JP5606961B2 (en) * 2011-02-25 2014-10-15 ルネサスエレクトロニクス株式会社 Semiconductor device
CN103337507B (en) * 2013-06-27 2017-04-26 上海华虹宏力半导体制造有限公司 Image sensor and forming method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008099073A (en) * 2006-10-13 2008-04-24 Sony Corp Solid imaging device and imaging device
CN102098456A (en) * 2009-12-15 2011-06-15 株式会社东芝 Solid-state imaging device which can expand dynamic range
CN102157536A (en) * 2010-01-28 2011-08-17 索尼公司 Solid-state imaging device and electronic apparatus

Also Published As

Publication number Publication date
CN108476298B (en) 2020-06-09
CN108476298A (en) 2018-08-31

Similar Documents

Publication Publication Date Title
US12302654B2 (en) Image sensors
US11843886B2 (en) Solid-state imaging device and manufacturing method therefor
KR102545845B1 (en) Semiconductor device and electronic apparatus
US7218347B2 (en) Photoelectric conversion element and solid-state image sensing device using the same
US6137100A (en) CMOS image sensor with different pixel sizes for different colors
US5070380A (en) Transfer gate for photodiode to CCD image sensor
EP1026747A2 (en) Image sensor
KR102507474B1 (en) Image sensor
US7679159B2 (en) Solid state imaging device and solid state imaging element
US10616513B2 (en) Image sensors including shielding structures
JP2010212288A (en) Image pickup device
US20090045415A1 (en) Backside-illuminated imaging device
KR102785834B1 (en) Image sensing device
KR100674923B1 (en) CMOS image sensor shares output circuits between adjacent pixels
WO2018152819A1 (en) Cmos image sensor with dual sensitivity pixel
KR20240176285A (en) Image Sensor
US20240321923A1 (en) Image sensor
JP6876109B2 (en) Solid-state image sensor and image sensor
KR20250035382A (en) Image sensing device
KR20240171914A (en) Semiconductor Apparatus
JP2025129053A (en) Image Sensor
JP2024023149A (en) image sensor
KR19990018939A (en) Charge Coupled Image Sensor
KR19990049053A (en) Solid-state imaging device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17898100

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17898100

Country of ref document: EP

Kind code of ref document: A1