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WO2018157547A1 - Procédé de mise sous boîtier pour boîtier intégré à un système de transmission de puissance - Google Patents

Procédé de mise sous boîtier pour boîtier intégré à un système de transmission de puissance Download PDF

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Publication number
WO2018157547A1
WO2018157547A1 PCT/CN2017/095403 CN2017095403W WO2018157547A1 WO 2018157547 A1 WO2018157547 A1 WO 2018157547A1 CN 2017095403 W CN2017095403 W CN 2017095403W WO 2018157547 A1 WO2018157547 A1 WO 2018157547A1
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WIPO (PCT)
Prior art keywords
metal
module
power transmission
carrier
transmission system
Prior art date
Application number
PCT/CN2017/095403
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English (en)
Chinese (zh)
Inventor
林章申
林正忠
何志宏
周祖源
Original Assignee
中芯长电半导体（江阴）有限公司
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Publication of WO2018157547A1 publication Critical patent/WO2018157547A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D
    • H01L25/071—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group subclass H10D the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Definitions

  • the present invention relates to the field of semiconductor packaging technologies, and in particular, to a packaging method of a package integrated with a power transmission system.
  • the power transmission system converts the high voltage of the power supply into many different low voltages required for discrete devices in the system.
  • the efficiency of the power transmission system determines the power loss of the down conversion, and the number of power rails determines the number of discrete voltage supplies or devices that can be supported.
  • adding more power rails requires copying more power components, such as increasing component count, increasing board size, increasing the number of boards, increasing system size, cost, and weight.
  • the present invention provides a package method for the above package integrated with a power transmission system, the package method comprising the following steps:
  • the active module and the passive module are disposed on the surface of the carrier formed with the metal lead, and form a metal connection column on the surface of the active module and the passive module;
  • the active module, the passive module and the rewiring layer together constitute a power transmission system; the power transmission system is adapted to convert a high voltage provided by an external power source into a plurality of different Low voltage and provide multiple low voltage power rails;
  • the power chip is disposed on the surface of the rewiring layer, and the power chip realizes docking with the low voltage power supply track via a plurality of micro bumps;
  • the metal wire on the surface of the carrier by a wire bonding process includes the following steps:
  • step 3 the back surface of the active module and the back surface of the passive module are bonding surfaces combined with the carrier.
  • the active module includes a controller and a buck converter;
  • the passive module includes a capacitor, an inductor, and a resistor.
  • the method for molding the metal lead, the active module, the passive module and the metal connecting post by using a molding material comprises: compression molding, transfer molding, hydroforming , vacuum lamination or spin coating.
  • the rewiring layer formed in step 5) includes: a metal wiring, a metal plug, and a dielectric layer disposed around the metal wiring and the metal plug, wherein the metal wiring is used to implement An electrical connection of the metal lead, the active module, and the passive module, the metal plug being used to achieve an interlayer connection between the metal lines between layers.
  • the method of forming the metal wiring includes at least one of electroplating, electroless plating, and screen printing.
  • the surface of the rewiring layer is provided with a bump metal layer electrically connected to the metal wiring, and the metal lead, the active module, the passive module, and the power chip pass through The bump metal layer is connected to the rewiring layer.
  • step 6 a step of performing underfill on a region between the micro bumps at the bottom of the power chip to fix the power chip to the On the wiring layer.
  • a step of forming a layer of molding material around the underfill material filled around the bottom and bottom of the electrical chip is performed.
  • the packaging method of the package incorporating the power transmission system of the present invention has the following beneficial effects:
  • the power-on chip may be an Application Specific Integrated Circuit (ASIC).
  • ASIC Application Specific Integrated Circuit
  • the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the power transmission chip which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the buck converter in the power transfer chip can generate thousands of low voltage power transmission tracks (power supply tracks) that are connected to the power chips through the micro bumps.
  • the package structure of the present invention can eliminate parasitic resistance on a package substrate such as a PCB due to integration of a power transfer chip including passive components, thereby improving power transmission efficiency and improving response time of power control.
  • FIG. 1 is a flow chart showing a packaging method of a package integrated with a power transmission system according to the present invention.
  • FIGS. 2 to 12 are schematic structural views showing steps in a packaging method of a package integrated with a power transmission system according to the present invention.
  • the present invention provides a packaging method for a package integrated with a power transmission system, the packaging method comprising the following steps:
  • the active module and the passive module are disposed on the surface of the carrier formed with the metal lead, and form a metal connection column on the surface of the active module and the passive module;
  • the power transmission system is adapted to convert a high voltage provided by an external power source into a plurality of different low voltages, and provide a plurality of low voltage power supply rails;
  • the power chip is disposed on the surface of the rewiring layer, and the power chip realizes docking with the low voltage power supply track via a plurality of micro bumps;
  • step 1) referring to step S1 in FIG. 1 and FIG. 2, a carrier 11 is provided.
  • the material of the carrier 11 may be selected from one or more of glass, stainless steel, silicon, silicon oxide, metal or ceramic, or the like.
  • the carrier 11 may be of a flat type.
  • the carrier 11 can be, but is not limited to, a glass circular plate having a certain thickness.
  • step 1) a step of forming a peeling layer 13 on the surface of the carrier 11 is further included.
  • the release layer 13 is used to adhere to a structure to be subsequently formed.
  • the release layer 13 may be a glue layer or a tape.
  • the release layer 13 is also removed.
  • the peeling layer 13 may be a double-sided tape which is heated or UV-debonded. When peeling off, one side may be UV-debonded on the other side, and the other side may be heated and de-bonded, or one side may be directly peeled off by heat-dissolving on the other side, and the double-sided tape is used to release the adhesive. The method is different.
  • the peeling layer 13 may also be a sacrificial layer of laser debonding.
  • the glue layer on the sacrificial layer may adhere to the structure to be formed subsequently; when peeling off, the sacrificial layer may be removed by laser, and then removed. glue.
  • the sacrificial layer may be deposited by CVD on the carrier 11, or may be coated with LTHC (light to heat) material, and the glue may be removed by chemical reagents.
  • step 2) referring to step S2 in FIG. 1 and FIG. 4, a metal bond 12 is formed on the surface of the carrier 11 by a wire bond process.
  • the peeling layer 13 is formed on the surface of the carrier 11, the metal lead 12 and the subsequent structures formed on the surface of the carrier 11 are formed on the surface of the peeling layer 13.
  • the metal lead 12 on the surface of the carrier 11 by a wire bonding process includes the following steps:
  • the metal lead 12 is formed on the dummy pad corresponding to the need to form the metal lead 12 by a wire bonding process.
  • step 2-1 a position where the metal lead 12 needs to be formed on the surface of the carrier 11 or a position where the metal lead 12 needs to be formed on the surface of the carrier 11 and an active module and a passive need to be disposed are required.
  • Forming the virtual pad by the position of the module includes the following steps:
  • the exposed metal layer is removed by an etching process, and the dummy pad is obtained by removing the photoresist layer.
  • the active module 14 and the passive module 15 involved in the step 3) may be of two types, one being the front and back sides of the active module 14 and the passive module 15
  • the front surface and the back surface are respectively provided with metal pads connected to the internal structure thereof, and the other is only the front surface of the active module 14 and the front surface of the passive module 15 are provided with metal pads connected to the internal structure thereof.
  • a metal pad is not disposed on the back surface of the active module 14 and the back surface of the passive module 15.
  • step 2-1 When the front and back sides of the active module 14 of the active module 14 and the front and back sides of the passive module 15 are provided with metal pads connected to the internal structure thereof, in step 2-1), The surface of the carrier 11 needs to form the position of the metal lead 12 and the position where the active module and the passive module need to be disposed simultaneously to form a dummy pad; when only the front surface of the active module 14 and the passive module 15 are The front surface is provided with a metal pad connected to the inner structure, that is, when the back surface of the active module 14 and the back surface of the passive module 15 are not provided with a metal pad, only the carrier is required in step 2-1) The surface of the surface 11 needs to form the metal lead 12 to form the dummy pad.
  • the material of the metal lead 12 may include one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the material of the dummy pad may also include one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the material of the metal lead 12 may be Cu, and the material of the dummy pad may be Ti/Cu.
  • the metal lead 12 may be a vertical column, and the metal lead 12 may be a plurality of. Due to the wire bonding method using wire bonding, each time the wire is relatively thin, it is necessary to apply a plurality of wires as one of the metal wires 12 so as to be connected to the subsequent rewiring layer, that is, each of the above
  • the metal lead 12 may include a plurality of wires which may be bonded to the carrier 11 by a wire bonding process; for example, a plurality of gold wires, copper wires or copper-gold alloy wires may be used as one at one place.
  • the metal lead 12 is.
  • step 3 referring to step S1 in FIG. 1 and FIG. 5, the active module 14 and the passive module 15 are disposed on the surface of the carrier 11 on which the metal lead 12 is formed, and The source module 14 and the surface of the passive module 15 form a metal connection pillar 16 .
  • the active module 14 can include a controller and a buck converter
  • the passive module 15 can include a capacitor 151, an inductor 152, and a resistor (not shown)
  • the active module 14 and the capacitor 151, the inductor 152 level of the passive module 15 such as the resistor can be laterally arranged in the same leveling layer, facilitating electrical connection and layout design with the subsequently formed rewiring layer, of course, the active module 14
  • the specific arrangement position of the passive module 15 can be designed according to actual needs, and the present invention does not limit this.
  • the back surface of the active module 14 and the back surface of the passive module 15 are combined surfaces of the carrier 11 , that is, the active module 14 and the passive
  • the module 15 is placed face up, and the metal connection post 16 is connected to the active module 14 and the pads on the front side of the passive module 15 to facilitate electrical connection with a subsequently formed rewiring layer.
  • the alloy layer may be formed by using a flux and using a high temperature reflow process to achieve the Soldering the metal pad of the back surface of the active module 14 and the back surface of the passive module 15 to the dummy pad to fix the active module 14 and the passive module 15 to the On the carrier 11; when there is no metal pad on the back surface of the active module 14 and the back surface of the passive module 15, the active module 14 and the above may be adhered by means of glue or double-sided tape or the like.
  • the passive module 15 is fixed to the carrier 11.
  • step 4 referring to step S4 in FIG. 1 and FIGS. 6 and 7, the metal lead 12, the active module 14, the passive module 15, and the metal are connected using a molding material 17.
  • the post 16 is packaged and a portion of the molding compound 17 is removed to expose the metal lead 12 and the metal post 16 .
  • the metal lead 12, the active module 14, the passive module 15, and the metal connection post 16 may be formed by processes such as compression molding, transfer molding, hydroforming, vacuum lamination, or spin coating.
  • the molding material 17 may be an epoxy resin, a liquid type thermosetting epoxy resin, a plastic molding compound or the like.
  • a portion of the molding material 17 may be removed using one or more of mechanical grinding, chemical polishing, or etching.
  • step 5 referring to the step S5 in FIG. 1 and FIG. 8, a rewiring layer 18 is formed on the surface of the molding material 17, and the rewiring layer 18 places the metal lead 12 and the active module 14
  • the passive module 15 is electrically connected; the active module 14, the passive module 15 and the rewiring layer 18 together constitute a power transmission system; the power transmission system is adapted to supply a high voltage from an external power source Convert to multiple different low voltages and provide multiple low voltage supply rails.
  • high voltage refers to a voltage higher than the voltage required for the later-mentioned power chip
  • low voltage as used herein means lower than the “high voltage”.
  • the voltage that is, the voltage required for the powered chip.
  • the rewiring layer 18 includes: a metal wiring 182, a metal plug, and a dielectric layer 181 disposed around the metal wiring 182 and the metal plug, wherein the metal wiring 182 is used to implement the Electrical connection of the metal lead 12, the active module 14 and the passive module 15, the metal plug being used to achieve an interlayer connection between the metal lines 182 between the layers.
  • the material of the metal wiring 182 includes one or more of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta, or other suitable conductive metal materials.
  • the metal wire 182 may be a Cu wire to make a Cu wire.
  • the seed layer can be a Ti/Cu layer.
  • the method of forming the metal wiring 182 may include one or more of electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process.
  • a through hole may be formed in the dielectric layer 181 by laser drilling, mechanical drilling, reactive ion etching, nanoimprinting or other suitable opening method, and then the through hole is filled with a metal material.
  • the metal plug is formed; the material of the metal plug may be solder or Cu, and the filling method may be electrolytic plating, electroless plating, screen printing, wire bonding or other method suitable for filling a conductive material in a through hole.
  • the surface of the rewiring layer 18 is provided with a bump metal layer (not shown) electrically connected to the metal wiring 182, the metal lead 12, the active module 14, the passive module 15 and subsequent use of the power chip are connected to the rewiring layer 18 via the bump metal layer, specifically, the metal lead 12, the active module 14, the passive module 15 and The power chips are all connected to the metal wires 182 in the rewiring layer 18 via the bump metal layer.
  • step 6 referring to step S6 in FIG. 1 and FIG. 9, a power chip 19 is provided, and the power chip 19 is disposed on the surface of the rewiring layer 18, and the power chip 19 is provided through multiple The microbumps 20 achieve abutment with the low voltage supply rail.
  • the power chip 19 may be soldered to the rewiring layer 18 via a plurality of microbumps 20 using processes such as ultrasonic bonding, thermocompression bonding, or conventional reflow soldering.
  • the powered chip 19 can be, but is not limited to, an ASIC Die.
  • a step of underfilling the region between the microbumps 20 at the bottom of the power chip 19 is further included to fix the power chip 19 to the rewiring.
  • the power chip 19 is fixed on the rewiring layer 18 by filling an underfill material 21 with a region between the micro bumps 20 at the bottom of the power chip 19, and the filling material may be For, but not limited to, underfill.
  • the underfill may be a CUF (Capillary Underfill) or a molding underfill (MUF, Molding UnderFill).
  • the method further includes forming a layer of the molding material 22 around the underfill material 21 around the underfill and the underfill. A step of.
  • step 7 referring to step S7 in FIG. 1 and FIGS. 11 and 12, the carrier 11 is peeled off to form solder bumps 23 connected to the metal leads 12.
  • the carrier 11 may be peeled off by one or more of mechanical grinding, chemical polishing, etching, ultraviolet peeling, mechanical peeling; preferably, in the present embodiment, the peeling layer 13 may be removed by peeling off The carrier 11.
  • the structure after peeling off the carrier 11 is as shown in FIG.
  • the solder bumps 23 may be solder balls.
  • the solder bumps 23 are taken.
  • Ball Grid Array (BGA) is used.
  • the package is connected to an external power source through the solder bumps 23.
  • the structure in which the solder bumps 23 connected to the metal leads 12 are formed is as shown in FIG.
  • the present invention provides a package method for a package integrated with a power transmission system, the package method comprising the steps of: 1) providing a carrier; 2) using a plating process on the surface of the carrier; Providing an active module and a passive module on a surface of the carrier on which the metal lead is formed, and forming a metal connection post on the surface of the active module and the passive module; 4) using a plastic sealing material Metal lead, the active module, the passive module and the metal connecting post are packaged, and part of the molding material is removed to expose the metal lead and the metal connecting post; 5) Forming a rewiring layer on the surface of the molding material, the rewiring layer electrically connecting the metal lead, the active module and the passive module; the active module, the passive module and the rewiring layer Cooperating to form a power transmission system; the power transmission system is adapted to convert a high voltage provided by an external power source into a plurality of different low voltages, and provide a plurality of low voltage power supply tracks; 6) providing a power
  • the invention has the following beneficial effects: (1) forming an active 2.5D interposer by using existing active components and passive components, and then integrating the electric chip into the active 2.5D intermediation through microbumps or other bump structures. On the board, a three-dimensional stack structure is obtained; wherein the power chip can be an Application Specific Integrated Circuit (ASIC); (2) in a three-dimensional stack structure, an active 2.5D interposer is used as a power transmission power chip.
  • ASIC Application Specific Integrated Circuit
  • the power transmission system of the entire system circuit board is realized by the power transmission chip, and the power transmission chip includes a controller and a buck converter ( Buck converter), capacitor (CAP(3T)), inductor (L(2T)) and resistor, thus eliminating all passive components on the system board;
  • buck converter in the power transfer chip can be generated Thousands of low-voltage power transmission tracks (power supply tracks) that are connected to the power chip by microbumps;
  • the package structure of the present invention integrates work including passive components
  • the transmission chip can eliminate the parasitic resistance on the package substrate such as the PCB board, thereby improving the power transmission efficiency and improving the response time of the power control; (6) improving the fidelity by reducing the voltage drop and noise, thereby improving the response time. . Better fidelity performance improvements are achieved due to the need for less design margin.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

L'invention concerne un procédé de mise sous boîtier pour un boîtier intégré à un système de transmission de puissance, comprenant les étapes suivantes consistant à : 1) fournir un support (11) ; 2) former, à l'aide d'un procédé de connexion des puces, des fils métalliques (12) sur la surface du support ; 3) fournir un module actif (14) et un module passif (15) sur la surface, formés avec les fils métalliques, du support (11), et former des bornes de connexion métalliques (16) sur les surfaces du module actif et du module passif ; 4) mettre sous boîtier et mouler les fils métalliques, le module actif, le module passif et les bornes de connexion métalliques ; 5) former une couche de recâblage (18) sur la surface du matériau de mise sous boîtier en plastique (17) ; 6) fournir une puce électrique (19) sur la surface de la couche de recâblage, la puce électrique venant en butée contre un rail d'alimentation basse tension au moyen d'une pluralité de microbosses (20) ; et 7) peler le support, pour former des bosses de soudure (23) connectées aux premiers fils métalliques. En utilisant une technologie d'empilement de puce tridimensionnelle, l'efficacité de transmission d'énergie est améliorée et le nombre de différents rails de tension disponibles est augmenté.
PCT/CN2017/095403 2017-03-03 2017-08-01 Procédé de mise sous boîtier pour boîtier intégré à un système de transmission de puissance WO2018157547A1 (fr)

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CN112243317B (zh) * 2019-07-18 2022-01-18 欣兴电子股份有限公司 线路板结构及其制造方法
CN115274461B (zh) * 2022-05-31 2024-10-11 浙江禾芯集成电路有限公司 一种应用于平面型功率器件的封装结构的封装方法

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