WO2018165815A1

WO2018165815A1 - Chip fanning out method

Info

Publication number: WO2018165815A1
Application number: PCT/CN2017/076431
Authority: WO
Inventors: 胡川; 刘俊军
Original assignee: 深圳修远电子科技有限公司
Priority date: 2017-03-13
Filing date: 2017-03-13
Publication date: 2018-09-20

Abstract

The present invention relates to a chip fanning out method, comprising: chips being provided with reference marks, and packaging and fixing at least two chips with packaging layers; after packaging, according to the reference marks of the two chips, designing a fine line pattern between the chips, wherein the width of a fine line is less than 10 micrometers; and using a micro-electro-mechanical system to manufacture the fine line, wherein the micro-electro-mechanical system comprises a light source, a controller, and an optical switching device butt-jointed with the controller; arranging a photoresist on surfaces of the chips and/or the packaging layers, the controller controlling an optical switching system to etch the fine line pattern on the photoresist, and manufacturing the fine line according to the fine line pattern, wherein the at least two chips are directly connected by means of the fine line electrically. A high-density fine line is obtained, and a high transmission speed can be obtained by connecting the chips by means of the high-density fine connecting line.

Description

Chip fanout method

Technical field

The invention belongs to the field of electronics, and in particular relates to a chip fanout method.

Background technique

When manufacturing a circuit board, it is necessary to fabricate a circuit layer on the insulating substrate, and mount the chip on the substrate, electrically connect the chip and the circuit layer to realize the circuit function, and then cover the chip with a protective layer to protect the chip. However, in the conventional process, the process of temperature change due to soldering, packaging, etc. is liable to cause thermal imbalance and deformation misalignment, and the connection of the circuit is broken. At present, the deformation and dislocation can be compensated for by increasing the line width and thickness of the connection. The wiring pattern is coarse and the connection density is low.

Summary of the invention

Based on this, the present invention overcomes the deficiencies of the prior art and provides a chip fan-out method for obtaining high-density fine wiring, and high-speed speed transmission speed can be obtained by connecting high-density fine connection lines between chips.

Its technical solutions are as follows:

A chip fanout method includes: a chip is provided with a fiducial mark, and at least two of the chip packages are fixed by an encapsulation layer; after packaging, a fine connection pattern between the chips is designed according to reference marks of two of the chips The fine line has a line width of less than 10 micrometers; the fine wiring is fabricated by a microelectromechanical system including a light source, a controller, and an optical switching device that interfaces with the controller, on the chip or/and a photoresist is disposed on the surface of the encapsulation layer, and the controller controls the optical switch system to engrave the fine wiring pattern on the photoresist, and the fine connection is made according to the fine wiring pattern, and at least two chips pass through the Fine wiring is directly connected.

In one embodiment, a basic connection is made on the chip or/and the encapsulation layer, the line width of the basic connection is greater than or equal to the line width of the fine connection, or the basic connection The thickness is greater than or equal to the thickness of the fine line.

In one embodiment, the base line has a line width greater than 10 microns or the base line has a thickness greater than 10 microns.

In one of the embodiments, the chip is electrically connected to the base wire.

In one embodiment, the chip is disposed on a carrier, and the package layer is disposed such that the chip is located between the package layer and the carrier, and after the package layer fixes the chip package, The carrier is removed from the chip.

In one embodiment, the chip is provided with a chip lead, the chip pin is facing the carrier, and after the carrier is removed from the chip, the chip pin is exposed, and the chip leads The foot is electrically connected to the fine wire.

In one embodiment, after the carrier is removed from the chip, a basic connection is made on the chip or/and the package layer, and the line width of the basic connection is greater than or equal to The line width of the fine line or the thickness of the base line is greater than or equal to the thickness of the fine line.

In one embodiment, the line width of the base wire is greater than 10 microns, or the thickness of the base wire is greater than 10 microns.

In one of the embodiments, the chip is electrically connected to the base wire.

In one embodiment, a dielectric layer is disposed on the carrier, the chip is disposed on the dielectric layer, and the encapsulation layer is disposed such that the chip is located between the encapsulation layer and the dielectric layer, After the encapsulation layer secures the chip package, the carrier or/and the dielectric layer are removed from the chip.

In one embodiment, a base line is formed on the medium layer, a line width of the base line is greater than or equal to a line width of the fine line, or a thickness of the base line is greater than or equal to Depicting the thickness of the fine wiring, the encapsulation layer is disposed such that the chip and the basic connection are located between the encapsulation layer and the dielectric layer, and the encapsulation layer shares the basic connection with the chip After the package is secured, the carrier or/and the media layer are removed from the chip and the base wire.

In one embodiment, the chip is provided with a chip lead that faces the carrier, after the carrier or/and the dielectric layer are removed from the chip, The chip pins are bare, and the chip pins are electrically connected to the fine wires.

In one embodiment, after the carrier or/and the dielectric layer are removed from the chip, Making a basic connection on the chip or/and the encapsulation layer, the line width of the basic connection is greater than the line width of the fine connection or the thickness of the basic connection is greater than the thickness of the fine connection, The basic connection is electrically connected to the chip.

In one of the embodiments, the chip is electrically connected to the base wire.

In one of the embodiments, the encapsulation layer is a resin.

In one embodiment, the fine wiring has a thickness of less than 10 microns, or the fine wiring has a gap of less than 10 microns.

In one of the embodiments, the chip fanout method further includes disposing an electronic component that encapsulates the electronic component with the chip.

In one of these embodiments, the electronic component includes a passive device or crystal.

In one of the embodiments, the optical switching device comprises a DMD chip.

In one embodiment, the controller includes a pattern system that detects location information of the fiducial marker and designs the fine connection according to position information of the fiducial marker measured by the position sensor pattern.

In one embodiment, the pattern system includes a docking position sensor and a pattern design system, the position sensor detecting position information of the fiducial marker, the pattern design system being responsive to the position sensor The fine line pattern is designed by the position information of the fiducial mark.

In one embodiment, the chip electrically connected to the fine winding is provided with a chip pin, the chip pin is electrically connected to the fine wire, the controller includes a pattern system, and the pattern system detects Position information of each of the chip pins, and designing the fine wiring pattern according to position information of the chip pins.

In one of the embodiments, the two chip pitches electrically connected to each other by the fine winding are less than or equal to 100 micrometers.

The beneficial effects of the invention are:

1. The chip fanout method includes: the chip is provided with a fiducial mark, and the chip may be provided with a fiducial mark. It is also possible to set a reference on the chip. The at least two chip packages are fixed by the encapsulation layer, the relative positions of the chips are limited, and the relative movement between the chips is limited; after the encapsulation, the fine wiring patterns between the chips are designed according to the reference marks of the two chips. During the encapsulation process of the encapsulation layer, the relative displacement between the chips may be caused. At this time, the relative displacement information between the chips and the current position information of the chip may be obtained according to the reference mark on the chip, and the displacement information includes the translation information and the rotation information. According to the displacement information between the chips or the current position information of the chip, the orientation and layout of the fine lines between the chips can be designed to obtain a fine connection pattern.

Wherein, the line width of the fine connection is less than 10 micrometers, and the line width of the fine connection is reduced, so as to set as many connections as possible in the same space, and increase the transmission channel between the chips to increase the transmission speed. The line width of the fine line is shown with reference to mark D2 in FIG. The conventional manufacturing process can only compensate for the misalignment caused by the chip displacement by increasing the line width of the connection, limits the width of the connection, and cannot obtain the fine connection with the line width of less than 10 micrometers in the present invention. In the present invention, the micro-electromechanical system is used to make a fine connection, and a fine connection with a line width of less than 10 micrometers can be obtained, thereby increasing the connection density and increasing the transmission speed between the chips. The MEMS system includes a light source, a controller, and an optical switching device that interfaces with the controller. The photoresist is disposed on the surface of the chip or/and the encapsulation layer, and the controller controls the optical switch system to engrave the fine wiring pattern on the photoresist. The fine connection is made according to the fine connection pattern, and at least two chips are directly electrically connected through the fine connection. Specifically, the controller controls the optical switching device to embody the fine wiring pattern information, so that the light emitted by the light source passes through the optical switching device, and then exposes the fine wiring pattern on the photoresist, and then the fine wiring is made according to the obtained pattern. The fine wiring may be fabricated on the encapsulation layer, or a fine connection may be made together on the chip and the encapsulation layer. The method of the present invention has a line width of less than 10 micrometers, and since the optical switching device can control the optical channel on the micrometer or nanometer level, thereby exhibiting a fine wiring pattern on the micrometer level,

The traditional method is to use a set of templates with fixed specifications to make the connection between the chips. It is not possible to accurately calculate the wiring of the wiring of the chip holder. Only by increasing the line width of the connection can ensure that the connection can be Electrically connected to the chip. However, in the present invention, the fine wiring pattern between the chips is re-corrected to accurately calculate the layout of the fine wiring, so that the fine wiring and the chip are precisely connected, so that a fine connection with a narrow line width can be produced, thereby improving The density of the wires, without the need to increase the line width. And, The conventional method is to install a circuit layer on a substrate, mount a chip on the circuit layer, and finally package the chip on the substrate with an insulating material, so that the chip displacement caused by the final packaging step cannot be avoided and cannot be compensated. However, in the present invention, the chip package is first fixed by the encapsulation layer, and the displacement of the chip caused by the encapsulation process can be compensated for in the subsequent design fine connection pattern, so that the line width can be designed to be narrow and fine, and the connection can be further improved. density.

2. Making a basic connection on the chip or/and the encapsulation layer, the basic connection may be made on the encapsulation layer, or the basic connection may be made on the chip and the encapsulation layer, and the line width of the basic connection is greater than or equal to the fine The line width of the wire, or the thickness of the base wire is greater than or equal to the thickness of the fine wire. Referring to the line D1 in Fig. 21, the thickness of the fine line is shown by the mark H2 in Fig. 21, and the thickness of the base line is shown by the mark H1 in Fig. 21. The chip is fast and requires fast data transmission. However, if the traditional manufacturing process is used, the space of the chip itself limits the number of connection points. The line width of the connection is too wide to limit the connection density, thus limiting the inter-chip. The number of transmission channels limits the speed of data transmission. The method of the present invention can use a fine connection with a line width of less than 10 micrometers to directly connect the two chips, thereby obtaining a higher connection density and a denser connection point, thereby increasing the number of transmission channels between the chips. To improve the chip transfer speed; in other areas, the area where the data transfer speed is not required to be such a high area is wider than the fine line width, and a simpler process can be used to make the basic connection, and the basic connection The line and the fine line have no influence on each other, thereby increasing production efficiency.

Wherein, the line width of the basic connection is greater than 10 micrometers or the thickness of the basic connection is greater than 10 micrometers. In some cases, the connection may be realized by a basic connection with a large line width and a large thickness, for example, some high-power lines, or The area of the weld. Alternatively, the chip can be electrically connected to the basic connection. For example, the chip can be powered by the basic connection. Since the line width of the fine connection is small, it is not suitable to withstand a large current, so that a basic line with a large line width and a large thickness can be set. Chip powered.

3. Set the chip on the carrier board, and set the package layer so that the chip is located between the package layer and the carrier board. After the package layer fixes the chip package, the carrier board is removed from the chip. The chip is packaged and fixed by the encapsulation layer under the support of the carrier board, which can provide better positioning of the chip and limit the displacement of the chip. And when the chip or package layer is very thin, or when it is made on a large flat level (greater than 300mm*300mm), The mounting itself does not provide support and the carrier can provide support for the encapsulation layer. Preferably, the carrier plate supports the package layer and the chip in a flat manner. After the carrier board is removed from the chip, the surface of the package layer and the chip contacting the carrier board is flat, which facilitates the fabrication of the fine connection and facilitates the implementation of the chip and the fine connection. The electrical connection between the wires enables precise alignment of the fine wires and the chip even in the case where the line width of the fine wires is small.

The chip is provided with a chip pin, and the chip pin is facing the carrier board. After the carrier board is removed from the chip, the chip pin is exposed, and the chip pin is electrically connected with the fine wire. The encapsulation layer does not shield the chip pins, and the fine wiring pattern is designed according to the reference marks of the two chips, so that the fine wiring is electrically connected to the chip pins. Chip pin bare refers to all or at least part of the chip pins not insulated by the package layer. The chip pins can be electrically connected. It should not be understood that the chip pins protrude from the package layer.

Moreover, it is optional to make a basic connection on the chip or/and the encapsulation layer after removing the carrier from the chip, the line width of the basic connection is greater than or equal to the line width of the fine connection, or the thickness of the basic connection Greater than or equal to the thickness of the fine wire. It may be that the line width of the base connection is greater than 10 microns, or the thickness of the base connection is greater than 10 microns. The whole circuit is divided into fine areas and common areas. Fine lines with small line widths are produced by precise design of measurement and patterns in fine areas, and line width ratio fine lines are made in a common area in a fast and low cost manner. Wide base connection, comprehensively improve the efficiency of circuit production, while controlling costs. The base connection can be selected to be electrically connected or not connected to the chip.

4. Set the medium layer on the carrier board, set the chip on the medium layer, set the package layer so that the chip is located between the package layer and the media layer, and after the package layer fixes the chip package, the carrier board or/and the media layer are removed from the chip. Remove. The media layer can assist in setting up the chip on the carrier board. The media layer fixes or fixes the chip. When the media layer fixes the chip, the relative displacement and misalignment of the chip when the encapsulation layer is cured is further reduced. Alternatively, the media layer is provided with a card slot of the chip, the chip card is placed on the card slot of the media layer, and the chip is restricted by the card position to move. It is also possible to select the media layer itself as a pasting material, and the media layer pastes the chip into the use carrier plate to limit the displacement during the package fixing process.

The chip is provided with chip pins, the chip pins are facing the carrier board, and after the carrier board or/and the media layer are removed from the chip, the chip pins are exposed, and the chip pins are electrically connected with the fine wiring. The line width of the base connection is greater than 10 microns or the thickness of the base connection is greater than 10 microns. The chip is electrically connected or not connected to the underlying connection.

Removing the carrier or/and the media layer from the chip, either removing the carrier individually or simultaneously The media layer is removed. After removal, a basic connection is made on the chip or/and the encapsulation layer. The line width of the basic connection is larger than the line width of the fine connection or the thickness of the basic connection is greater than the thickness of the fine connection, and the basic connection is electrically connected to the chip. . If the media layer is not removed, this allows the chip and fine wire connections to be made by opening holes in the media layer.

5. Making a basic connection on the medium layer, the line width of the basic connection is larger than the line width of the fine connection or the thickness of the basic connection is greater than the thickness of the fine connection, and the encapsulation layer is provided so that the chip and the basic connection are located in the encapsulation layer and Between the media layers, the encapsulation layer co-packages the base wiring and the chip, and removes the carrier or/and the media layer from the chip and the basic connection. The media layer can assist in making the basic connection, and the basic connection can be electrically connected or not connected to the chip. First set the basic connection, and then use the encapsulation layer to fix the basic connection and the chip package. Since the line width of the basic connection is larger than the line width of the fine connection or the thickness of the basic connection is larger than the thickness of the fine connection, the basic connection itself The line width can compensate for the displacement misalignment generated during the package fixing process to a certain extent. After the package is fixed, the relative position of the basic connection and the chip is limited, and the fabrication of the fine connection is not affected.

6. The encapsulation layer is a resin, and the resin needs to be cured to fix the chip. A flexible material can also be used as the encapsulation layer. After the chip is packaged, the package layer and the chip are integrally flexible and bendable, and can be applied to a wearable device.

7. The thickness of the fine connection is less than 10 micrometers. Because the line width of the fine connection is very narrow, the thickness of the fine connection is too high to cause adhesion, and the thickness of the fine connection is reduced to improve the yield and reliability. The method of the invention can be used. A fine connection with a small line width and a thin thickness is obtained, and the connection density between the chips is increased. Or the gap of the fine connection is less than 10 micrometers. With the method of the invention, since the pattern of the finely wired trace layout can be accurately designed, the fine connection and the chip are accurately docked, and the chip displacement is not required to be compensated by expanding the gap of the fine connection. The misplacement is brought about, so the fine lines can be densely arranged to increase the density of the fine lines.

8. In addition to the chip, electronic components can be disposed, and the package layer encapsulates the electronic components together with the chip. The chip can be electrically connected to the electronic component through a fine wire or a basic wire.

Electronic components include passive components, active devices, or crystals, including but not limited to dies or packaged chips.

9. The optical switching device includes a DMD (digital micro-mirror device) chip, and the DMD chip can make fine wiring on the micrometer or nanometer level. The controller controls the DMD chip to generate fine wiring pattern information, so that the light emitted by the light source exposes the fine wiring pattern through a predetermined area of the DMD chip, and then makes a fine connection according to the obtained pattern.

10. The controller includes a pattern system, the pattern system detects position information of the reference mark, and designs a fine connection pattern according to the position information of the reference mark measured by the position sensor. After the chip position is detected by the pattern system, the fine connection pattern between the chips is accurately designed to ensure the precise connection between the fine connection and the chip.

Preferably, the pattern system comprises a relative position sensor and a pattern design system, the position sensor detects position information of the reference mark, and the pattern design system designs a fine line pattern according to the position information of the reference mark measured by the position sensor.

Preferably, the chip electrically connected to the fine winding is provided with a chip pin, and the chip pin is electrically connected with the fine wire. The controller includes a pattern system, and the pattern system detects the position information of each chip pin, and according to the chip pin The location information is designed to be carefully connected to the pattern.

11. The spacing between the two chips electrically connected to each other by the fine winding is less than or equal to 100 micrometers, so that the gap between the two chips can be combined with the method of the present invention to make the line width of the fine wiring less than or equal to 10 micrometers. The area occupied by the fine wiring can be greatly reduced, and the density of the chip can be increased. If more than three chips are electrically connected to each other through a fine wire, the gap between any two chips is less than or equal to 100 micrometers.

DRAWINGS

1 is a schematic diagram of a package on a carrier board according to an embodiment of the present invention;

2 is a schematic view of the embodiment of the present invention after removing the carrier;

3 is a schematic view showing a photoresist set according to an embodiment of the present invention;

4 is a top view of a fine wiring pattern according to an embodiment of the present invention;

Figure 5 is a cross-sectional view taken along line A-A of Figure 4;

Figure 6 is a cross-sectional view taken along line B-B of Figure 5;

FIG. 7 is a top view showing the fabrication of a fine connection according to an embodiment of the present invention; FIG.

Figure 8 is a cross-sectional view taken along line C-C of Figure 7;

Figure 9 is a cross-sectional view taken along line D-D of Figure 8;

10 is a top plan view of an additional encapsulation layer according to an embodiment of the present invention;

Figure 11 is a cross-sectional view taken along line E-E of Figure 10;

Figure 12 is a cross-sectional view taken along line F-F of Figure 11;

FIG. 13 is a schematic diagram of a package on a carrier board according to Embodiment 2 of the present invention; FIG.

Figure 14 is a schematic view of the second embodiment of the present invention after removing the carrier;

15 is a schematic view showing a photoresist set according to Embodiment 2 of the present invention;

Figure 16 is a cross-sectional view taken along line G-G of Figure 15;

17 is a schematic diagram of fabricating a basic connection according to Embodiment 2 of the present invention;

Figure 18 is a cross-sectional view taken along line H-H of Figure 17;

FIG. 19 is a schematic diagram of making a fine connection according to Embodiment 2 of the present invention; FIG.

Figure 20 is a cross-sectional view taken along line K-K of Figure 19;

Figure 21 is a cross-sectional view of J in Figure 20;

FIG. 22 is a schematic diagram of fabricating a 3D circuit according to Embodiment 2 of the present invention.

Description of the reference signs:

100, carrier board, 110, media layer, 200, package layer, 210, additional package layer, 300, chip, 310, fiducial mark, 330, electronic parts, 410, fine connection, 420, basic connection, 430, outside Contact pin, 500, photoresist, 510, basic wiring pattern, 520, fine wiring pattern, 610, first circuit layer, 620, second circuit layer.

detailed description

The present invention will be further described in detail below, but embodiments of the invention are not limited thereto.

Embodiment 1

As shown in FIG. 1, a dielectric layer 110 is disposed on the carrier 100, and a chip 300 is disposed on the dielectric layer 110. The chip 300 is provided with chip pins, and the chip pins are directed toward the carrier 100. The media layer 110 can assist in the carrier board The chip 300 is disposed on the 100, and the medium layer 110 can be selected to fix or not fix the chip 300. The chip 300 is provided with a fiducial mark 310 that faces the carrier 100.

The encapsulation layer 200 is disposed such that the chip 300 is positioned between the encapsulation layer 200 and the dielectric layer 110, and the cured encapsulation layer 200 encapsulates the chip 300. The at least two chips 300 are packaged and fixed by the encapsulation layer 200, defining the relative positions of the chips 300 and limiting the relative movement between the chips 300. After the encapsulation layer 200 encapsulates the chip 300, the carrier 100 and the dielectric layer 110 are removed from the chip 300 and the encapsulation layer 200. As shown in FIG. 2, after the carrier 100 and the dielectric layer 110 are removed from the chip 300, The chip pins are bare and the fiducial mark 310 bare can be detected. Preferably, the carrier 100 supports the encapsulation layer 200 and the chip 300 in a flat manner. After the carrier 100 is removed from the chip 300, the surface of the encapsulation layer 200 and the chip 300 in contact with the carrier 100 is flat, which facilitates the fine connection 420. The fabrication and facilitating the electrical connection between the chip 300 and the fine wiring 420 enables the fine wiring 420 to be accurately aligned with the chip 300 even when the line width of the fine wiring 420 is small.

After the carrier 100 and the dielectric layer 110 are removed from the chip 300 and the encapsulation layer 200, fine lines and basic lines are formed on the plane formed by the chip 300 and the encapsulation layer 200, and the line width of the basic connection is greater than or equal to the fine The line width of the wire, or the thickness of the base wire is greater than or equal to the thickness of the fine wire:

(1) Making fine connections:

The fine wiring pattern 520 between the chips 300 is precisely designed according to the reference mark 310 of the two chips 300 by the MEMS, and the fine wiring 420 is made to electrically connect the fine wiring 420 and the chip pins. The relative displacement between the chips 300 may be caused during the encapsulation process of the encapsulation layer 200. At this time, the relative displacement information between the chips 300 and the current position information of the chip 300 may be obtained according to the reference mark 310 on the chip 300, and the displacement information includes The panning information and the rotation information can be designed according to the displacement information between the chips 300 or the current position information of the chip 300, and the orientation and layout of the fine wires 420 between the chips 300 can be designed, thereby obtaining the fine wiring pattern 520.

The MEMS system includes a light source, a controller, and an optical switching device that interfaces with the controller, the controller includes a pattern system, the pattern system includes an opposite position sensor and a pattern design system, and the optical switching device includes a DMD (digital micro-mirror device) Chips, DMD chips can make fine connections 420 on the micron or nanoscale. The position sensor detects the position information of the reference mark 310, and the pattern The design system accurately designs the fine wiring pattern 520 between the chips 300 according to the position information of the reference mark 310 measured by the position sensor, and obtains the fine connection pattern 520 to ensure the precise connection of the fine connection 420 and the chip 300. As shown in FIGS. 3 to 6, a photoresist 500 is disposed on the surface of the chip 300 and the encapsulation layer 200 (not limited to the illustration, the photoresist 500 may be positive or reverse), and the light source emits light, and the light may be irradiated through the DMD chip. The photoresist 500, the controller controls the DMD chip to display the fine wiring pattern 520 information, thereby exposing the fine wiring pattern 520 in a predetermined area, and then fabricating the fine wiring 420 according to the obtained fine wiring pattern 520, as shown in FIGS. 7 to 9. The fine wiring 420 is electrically connected to the chip pins, and at least two chips 300 are directly electrically connected through the fine wiring 420. The method of the present invention has a line width 420 having a line width of less than 10 microns, since the DMD chip can control the light path on the micro or nano level to exhibit a fine line pattern 520 on the micron level. Wherein, the line width of the fine connection 420 is less than 10 micrometers, and the line width of the fine connection 420 is reduced, so as to set as many connections as possible in the same space, and increase the transmission channel between the chips 300 to increase the transmission speed; The conventional manufacturing process can only compensate for the misalignment caused by the displacement of the chip 300 by increasing the line width of the connection, limits the width of the connection, and cannot obtain the fine connection 420 having a line width of less than 10 μm in the present invention. In the present invention, by using the micro-electromechanical system to fabricate the fine wiring 420, the fine wiring 420 having a line width of less than 10 micrometers can be obtained, thereby increasing the wiring density and increasing the transmission speed between the chips 300. The line width of the base line is shown with reference to the mark D1 in Fig. 21, and the line width of the fine line is shown with reference to the mark D2 in Fig. 21.

The method is not limited to the above method, and the pattern system detects the position information of the chip pins, and designs a fine connection pattern according to the position information of the chip pins. The pattern system completes the detection of the chip position information (or the position information of the chip pins) and the design of the fine wiring pattern, and then introduces the pattern of the fine wiring 420 into the DMD chip for exposure. The pattern of the fine connection 420 exposed by the DMD chip is designed according to the actual position of the chip 300 after the package is fixed, and the positional interference of the package process on the chip 300 is eliminated, and there is no theoretical error to ensure the correct connection of the chip pins.

The traditional method is to make a connection and then complete the package, and use a set of templates of a fixed specification to make a connection between the chips 300. The accurate calculation design of the connection patterns between the chips 300 cannot be performed. The line width of the connection is increased to ensure that the connection can be electrically connected to the chip 300. However, in the present invention, the fine wiring pattern 520 between the chips 300 is re-corrected to accurately calculate the fine wiring 420. The routing layout allows the fine wiring 420 to be accurately interfaced with the chip 300, so that a fine wiring 420 having a narrow line width can be produced to increase the density of the wiring without using a method of increasing the line width. Moreover, the conventional method is to provide a circuit layer on the substrate, mount the chip 300 on the circuit layer, and finally package the chip 300 on the substrate with an insulating material, so that the displacement of the chip 300 caused by the final packaging step cannot be avoided and cannot be compensated. However, in the present invention, the chip 300 is first packaged and fixed by the encapsulation layer 200, and the displacement of the chip 300 caused by the encapsulation process can be compensated for by the subsequent fine connection of the design, so that the fine line width 420 with a narrow line width can be designed. Further increase the density of contacts.

In this embodiment, the thickness of the fine connection 420 is less than 10 micrometers. Since the line width of the fine connection 420 is narrow, the thickness of the fine connection 420 is too high to cause adhesion, and the thickness of the fine connection 420 is reduced to improve the yield and reliability. The fine wiring 420 having a small line width and a small thickness can be obtained by the method of the present invention, and the connection density between the chips 300 can be improved. The thickness of the fine wiring is shown with reference to the mark H2 in Fig. 21, and the thickness of the basic wiring is shown with reference to the mark H1 in Fig. 21. Or the gap of the fine connection 420 is less than 10 micrometers. With the method of the present invention, since the pattern of the trace layout of the fine connection 420 can be accurately designed, the fine connection 420 and the chip 300 are accurately docked without expanding the fine connection 420. The gap compensates for the misalignment caused by the displacement of the chip 300, so the fine wiring 420 can be densely arranged to increase the density of the fine wiring 420.

(2) Making the basic connection:

The basic wiring is made outside the fine winding area, and the chip is electrically connected to the basic wiring.

Meanwhile, as shown in FIGS. 10 to 12, the base wiring 410 may be formed on the chip 300 and the encapsulation layer 200, and then the additional encapsulation layer 210 is disposed such that the chip 300, the basic wiring 410, and the fine wiring 420 are located in the additional encapsulation layer 210. Between the encapsulation layer 200 and the encapsulation layer 200, the additional encapsulation layer 210 and the encapsulation layer 200 together fix and provide protection for the chip 300, the basic connection 410 and the fine connection 420, and an external contact leg 430 electrically connected to the basic connection 410. . In this embodiment, the thickness of the basic connection 410 is equal to the thickness of the fine connection 420. The metal layer can be disposed on the chip 300 and the encapsulation layer 200 to form the fine connection 420 and the basic connection 410, for example, as shown in FIGS. As shown, an additional light source can be selected to expose the base wiring pattern 510 on the photoresist 500, and the base wiring 410 can be made synchronously according to the basic wiring pattern 510, which can improve production efficiency. However, it is not limited thereto, and the line width of the basic connection 410 can be selected. The line width at or equal to the fine line 420, or the thickness of the base line 410 is greater than or equal to the thickness of the fine line 420. The chip 300 is electrically or not connected to the base connection 410. The chip 300 has a fast calculation speed and requires a fast data transmission speed. However, if a conventional manufacturing process is employed, on the one hand, the space of the chip 300 itself limits the number of connection points, and the line width of the connection is too wide to limit the connection density, thereby limiting the chip. The number of transmission channels between 300 limits the data transmission speed. The method of the present invention can thus use the fine connection 420 with a line width of less than 10 micrometers to directly connect the two chips 300, thereby obtaining a higher connection density and a denser connection point, thereby increasing the connection between the chips 300. The number of transmission channels increases the transmission speed of the chip 300; in other areas, the area where the data transmission speed is not required to be so high is wider than the fine connection 420 line width of the basic connection 410, and a simpler process can be used to make the basis. The line 410 is connected, and the base line 410 and the fine line 420 have no influence on each other, thereby improving production efficiency.

In this embodiment, the line width of the basic connection line 410 is greater than the line width of the fine connection line 420. For example, the line width of the basic connection line 410 is greater than 10 micrometers, and some high-power lines or lines requiring thermal processing such as soldering may pass through the basic connection. Line 410 is electrically coupled to chip 300. For example, the chip 300 can be powered by the base connection 410. Since the line width of the fine connection 420 is small and it is not suitable to withstand a large current, the base line 410 having a large line width or a large thickness can be provided to supply power to the chip 300.

Among them, a resin may be selected as the encapsulating layer 200, and it is necessary to cure the resin to fix the chip 300. A flexible material may also be used as the encapsulation layer 200. After the package chip 300 is packaged, the encapsulation layer 200 and the chip 300 are integrally formed to be flexible and bendable, and may be applied to a wearable device.

In this embodiment, the carrier 100 is made of glass or metal. The glass and metal have a good flatness as the carrier 100 and are small in thermal deformation, which is advantageous in maintaining a reliable connection between the base circuit layer and the chip 300. The metal material is preferably made of stainless steel to provide a high degree of flatness on the stainless steel surface. The medium layer 110 is a photosensitive adhesive medium, and the carrier board 100 is made of a light-transmissive glass material. The light-transmissive glass is used to prepare the carrier board 100. The light-transmitting property of the glass material can be adjusted from one side of the carrier board 100. The light of the photosensitive adhesive medium removes the carrier 100 from the chip 300 and the encapsulation layer 200; or the dielectric layer 110 is a heat-sensitive adhesive medium, and the carrier 100 is made of a metal material, and the heat is adjusted from one side of the carrier 100. The temperature of the adhesive medium is removed, and the carrier 100 is removed from the chip 300 and the encapsulation layer 200. The metal has good thermal conductivity. It is advantageous to use a heat-sensitive bonding material, and the metal has high strength and is not easy to be worn. For example, the carrier plate 100 can be made of stainless steel to prevent rust. When the medium layer 110 is a photosensitive adhesive medium or a heat sensitive adhesive medium, the chip 300 is placed. When the medium layer 110 is placed on the medium layer 110, the medium layer 110 affixes the chip 300 to the carrier 100, which can reduce the package. The relative displacement and misalignment of the chip 300 when the layer 200 is cured. However, the present invention is not limited to the embodiment, and the medium layer 110 may be selected to fix or not fix the chip 300. The medium layer 110 is provided with the card position of the chip 300, the chip 300 is stuck on the card position of the medium layer 110, and the chip 300 is limited by the card position. mobile. Alternatively, the dielectric layer 110 itself may be a bonding material, and the dielectric layer 110 affixes the chip 300 to the carrier 100 to limit the displacement during the package fixing process.

As described above, the present embodiment divides the entire circuit into a fine area, a common area, and measures the reference mark 310 of the chip 300 in the fine area, and precisely designs the fine wiring pattern 520 to create a fine line width. The connection line 420 increases the connection density of the fine connection 420 between the chips 300; in the normal area, the base line 410 with a line width wider than the fine connection line 420 is formed in a fast and low-cost manner, and the manufacturing efficiency of the integrated lifting circuit is improved. While controlling costs.

In this embodiment, after the dielectric layer 110 is disposed on the carrier 100, the chip 300 is mounted on the dielectric layer 110. However, the chip 300 is directly disposed on the carrier 100, and then the package layer 200 is disposed to make the chip 300. Between the encapsulation layer 200 and the carrier 100, after the encapsulation layer 200 encapsulates the chip 300, the carrier 100 is removed from the chip 300. After the carrier 100 is removed from the chip 300, a base connection 410 is formed on the chip 300 or/and the encapsulation layer 200, and then an additional encapsulation layer 210 is disposed, so that the chip 300, the fine connection 420, and the base connection 410 are attached. Between the encapsulation layer 210 and the encapsulation layer 200, the additional encapsulation layer 210 and the encapsulation layer 200 form a common package protection for the chip 300, the fine wiring 420, and the basic connection 410.

Embodiment 2

The difference between the second embodiment and the first embodiment is:

As shown in FIG. 13, in addition to the chip 300, an electronic component 330 may be disposed on the dielectric layer 110. The encapsulation layer 200 is provided to cause the encapsulation layer 200 to package and secure the electronic component 330 together with the chip 300. As shown in FIG. 14, the carrier 100 and the dielectric layer 110 are disposed on the chip 300, the electronic component 330, and the encapsulation layer 200. Removal, as shown in FIGS. 15 and 16, first, a photoresist 500 is disposed on the chip 300, the electronic component 330, and the encapsulation layer 200, and the photoresist 500 protects a region where the fine wiring 420 is to be formed, in the photoresist 500. The basic connection pattern 510 is fabricated and the basic connection 410 is formed. As shown in FIGS. 17 and 18, the basic connection 410 is electrically connected to the chip 300 or electrically connected to the electronic component 330. The photoresist 500 is disposed in the region of the fine wiring 420, and the fine wiring 420 is fabricated by using the microelectromechanical system with the DMD chip described in the first embodiment to directly electrically connect at least two chips 300 through the fine wiring 420. , as shown in Figures 19 to 21. Specifically, the position sensor detects the position information of the reference mark 310, and the pattern design system accurately designs the fine connection pattern 520 between the chips 300 according to the position information of the reference mark 310 measured by the position sensor, and obtains the fine connection pattern 520. To ensure the precise connection of the fine connection 420 to the chip 300. After the basic connection 410 and the fine connection 420 are completed, the first circuit layer 610, the second circuit layer 620, and the external contact pins 430 electrically connected to the chip 300 or the basic connection 410 are continuously stacked to form a 3D circuit board, such as Figure 22 shows.

The chip 300 can be electrically connected to the electronic component 330 through the fine connection 420 or the basic connection 410. Electronic component 330 includes a passive device or crystal.

In this embodiment, in the embodiment, the thickness of the basic connection 410 is greater than the thickness of the fine connection 420, and the thickness of the basic connection 410 may be greater than 10 micrometers, and the thickness of the fine connection 420 is less than 10 micrometers. The basic connection 410 and the fine connection 420 are separately fabricated, the basic connection 410 is first made, and the fine connection 420 is formed. Finally, the additional package layer 210 is provided to protect the fine connection 420, and the fine connection 420 is ensured after the fine connection 420 is set. The chip pins are precisely connected and minimize the possibility that the fine wiring 420 is destroyed by subsequent processes.

Embodiment 3

The difference between the third embodiment and the first embodiment is:

A dielectric layer 110 is disposed on the carrier 100, and then a basic connection 410 is formed on the dielectric layer 110. The package layer 200 is disposed such that the chip 300 and the basic connection 410 are located between the encapsulation layer 200 and the dielectric layer 110. After the connection 410 and the chip 300 are packaged and fixed together, the carrier 100 and the dielectric layer 110 are removed from the chip 300 and the base connection 410. The media layer 110 can assist in making the basic connection 410. The base connection 410 can be electrically or not connected to the chip 300. First, the basic connection 410 is set, and then the base connection 410 and the chip 300 are package-fixed by the encapsulation layer 200, because the line width of the basic connection 410 is larger than the line width of the fine connection 420 or the thickness of the basic connection 410 is larger than the fine connection. The thickness of the 420, the line width of the base connection 410 itself can compensate for the displacement displacement caused by the package fixing process to a certain extent, and the relative position of the basic connection 410 and the chip 300 is limited after the package is fixed, and the fine connection 420 is not affected. Production.

First, the basic connection 410 is made, and then the fine connection 420 is formed. Finally, the additional package layer 210 is provided to protect the fine connection 420, ensuring that the fine connection 420 is finely connected to the chip pins after the fine connection 420 is set, and the fine connection is minimized. Line 420 is likely to be destroyed by subsequent processes.

The dielectric layer 110 can be selected to be a dielectric, which facilitates plating a layer of conductive material thereon to form the base wiring 410.

The technical features of the above embodiments may be arbitrarily combined. For the sake of brevity of description, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, It is considered to be the range described in this specification.

The above embodiments are merely illustrative of several embodiments of the present invention, and the description thereof is more specific and detailed, but is not to be construed as limiting the scope of the invention. It should be noted that a number of variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be determined by the appended claims.

Claims

A chip fanout method, comprising:

The chip is provided with a fiducial mark, and at least two of the chip packages are fixed by an encapsulation layer, and after the package, a fine connection and a basic connection are respectively made, and the line width of the basic connection is greater than or equal to the line of the fine connection. Width, or the thickness of the base line is greater than or equal to the thickness of the fine line:

Making a fine connection: designing a fine connection pattern between the chips according to the reference marks of the two chips, the line width of the fine connection is less than 10 micrometers; the fine connection is made by using a microelectromechanical system, The MEMS system includes a light source, a controller, and an optical switching device that interfaces with the controller, and a photoresist is disposed on the surface of the chip or/and the package layer, and the controller controls the optical switch system to engrave the fine wiring on the photoresist Drawing, and fabricating the fine connection according to the fine connection pattern, at least two chips are directly electrically connected through the fine connection;

Making a basic connection: making a basic connection outside the fine winding area, the chip being electrically connected to the basic connection.
The chip fan-out method according to claim 1, wherein the method of fabricating the basic wiring is a maskless exposure method.
The chip fan-out method according to claim 1, wherein the line width of the base line is greater than 10 microns or the thickness of the base line is greater than 10 microns.
The chip fan-out method according to claim 1, wherein the chip is electrically connected to the base connection.
The chip fan-out method according to claim 1, wherein the chip is disposed on a carrier, and the package layer is disposed such that the chip is located between the package layer and the carrier, the package After the layer secures the chip package, the carrier board is removed from the chip.
The chip fan-out method according to claim 5, wherein the chip is provided with a chip pin, the chip pin faces the carrier, and after the carrier is removed from the chip, the The chip pins are bare, and the chip pins are electrically connected to the fine wires.
The chip fan-out method according to claim 5, wherein after the carrier is removed from the chip, a basic connection is made on the chip or/and the package layer, the basis The line width of the line is greater than or equal to the line width of the fine line, or the thickness of the base line is greater than or equal to The thickness of the fine line.
The chip fan-out method according to claim 7, wherein the line width of the base line is greater than 10 microns, or the thickness of the base line is greater than 10 microns.
The chip fanout method according to claim 7, wherein the chip is electrically connected to the base connection.
The chip fan-out method according to claim 5, wherein a carrier layer is disposed on the carrier, the chip is disposed on the dielectric layer, and the package layer is disposed such that the chip is located in the package layer and Between the media layers, after the package layer fixes the chip package, the carrier or/and the dielectric layer are removed from the chip.
The chip fan-out method according to claim 5, wherein a basic connection is formed on the medium layer, a line width of the basic connection is greater than or equal to a line width of the fine connection, or The thickness of the base connection is greater than or equal to the thickness of the fine wiring, and the encapsulation layer is disposed such that the chip and the basic connection are located between the encapsulation layer and the dielectric layer, and the encapsulation layer is After the base connection and the chip are co-packaged, the carrier or/and the dielectric layer are removed from the chip and the base connection.
The chip fan-out method according to claim 10, wherein the chip is provided with a chip lead, the chip pin faces the carrier, and the carrier or/and the dielectric layer are removed from the carrier After the chip is removed, the chip pins are exposed, and the chip pins are electrically connected to the fine wires.
The chip fan-out method according to claim 10, wherein after the carrier or/and the dielectric layer are removed from the chip, a basic connection is formed on the chip or/and the package layer a line having a line width greater than a line width of the fine line or a thickness of the base line being greater than a thickness of the fine line, the base line being electrically connected to the chip.
The chip fan-out method according to claim 13, wherein the line width of the base line is greater than 10 microns or the thickness of the base line is greater than 10 microns.
The chip fanout method according to claim 13, wherein said chip is electrically connected to said base connection.
The chip fanout method according to claim 1, wherein the encapsulation layer is a tree fat.
The chip fan-out method according to any one of claims 1 to 16, wherein the thickness of the fine wiring is less than 10 μm, or the gap of the fine wiring is less than 10 μm.
The chip fan-out method according to any one of claims 1 to 16, further comprising providing an electronic component, the encapsulation layer encapsulating the electronic component together with the chip.
The chip fan-out method according to claim 18, wherein the electronic component comprises a passive device or a crystal.
The chip fan-out method according to any one of claims 1 to 16, wherein the optical switching device comprises a DMD chip.
The chip fan-out method according to any one of claims 1 to 16, wherein the controller comprises a pattern system, the pattern system detects position information of the reference mark, and measures according to the position sensor The position information of the fiducial mark designs the fine wiring pattern.
The chip fan-out method according to claim 21, wherein said pattern system comprises a relative position sensor and a pattern design system, said position sensor detecting position information of said reference mark, said reference mark position The information includes the actual location of the chip, and the pattern design system designs the fine wiring pattern based on the actual position of the chip.
The chip fan-out method according to claim 21, wherein the chip electrically connected to the fine winding is provided with a chip pin, and the chip pin is electrically connected to the fine wire, the controller A pattern system is included, the pattern system detecting location information of each of the chip pins, and designing the fine wiring pattern according to position information of the chip pins.

In the fine winding area, each chip-to-chip pin line is measured by the actual chip position, and the winding pattern of the interconnect line is recalculated.
The chip fan-out method according to any one of claims 1 to 16, characterized in that the distance between the two chips electrically connected to each other by the fine winding is less than or equal to 100 μm.