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WO2018165815A1 - Procédé de sortance de puce - Google Patents

Procédé de sortance de puce Download PDF

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Publication number
WO2018165815A1
WO2018165815A1 PCT/CN2017/076431 CN2017076431W WO2018165815A1 WO 2018165815 A1 WO2018165815 A1 WO 2018165815A1 CN 2017076431 W CN2017076431 W CN 2017076431W WO 2018165815 A1 WO2018165815 A1 WO 2018165815A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
fine
connection
line
layer
Prior art date
Application number
PCT/CN2017/076431
Other languages
English (en)
Chinese (zh)
Inventor
胡川
刘俊军
Original Assignee
深圳修远电子科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳修远电子科技有限公司 filed Critical 深圳修远电子科技有限公司
Priority to PCT/CN2017/076431 priority Critical patent/WO2018165815A1/fr
Publication of WO2018165815A1 publication Critical patent/WO2018165815A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

Definitions

  • a chip fanout method includes: a chip is provided with a fiducial mark, and at least two of the chip packages are fixed by an encapsulation layer; after packaging, a fine connection pattern between the chips is designed according to reference marks of two of the chips
  • the fine line has a line width of less than 10 micrometers;
  • the fine wiring is fabricated by a microelectromechanical system including a light source, a controller, and an optical switching device that interfaces with the controller, on the chip or/and a photoresist is disposed on the surface of the encapsulation layer, and the controller controls the optical switch system to engrave the fine wiring pattern on the photoresist, and the fine connection is made according to the fine wiring pattern, and at least two chips pass through the Fine wiring is directly connected.
  • a basic connection is made on the chip or/and the encapsulation layer, the line width of the basic connection is greater than or equal to the line width of the fine connection, or the basic connection The thickness is greater than or equal to the thickness of the fine line.
  • a dielectric layer is disposed on the carrier, the chip is disposed on the dielectric layer, and the encapsulation layer is disposed such that the chip is located between the encapsulation layer and the dielectric layer, After the encapsulation layer secures the chip package, the carrier or/and the dielectric layer are removed from the chip.
  • the pattern system includes a docking position sensor and a pattern design system, the position sensor detecting position information of the fiducial marker, the pattern design system being responsive to the position sensor
  • the fine line pattern is designed by the position information of the fiducial mark.
  • Figure 14 is a schematic view of the second embodiment of the present invention after removing the carrier
  • Figure 20 is a cross-sectional view taken along line K-K of Figure 19;
  • a photoresist 500 is disposed on the surface of the chip 300 and the encapsulation layer 200 (not limited to the illustration, the photoresist 500 may be positive or reverse), and the light source emits light, and the light may be irradiated through the DMD chip.
  • the photoresist 500, the controller controls the DMD chip to display the fine wiring pattern 520 information, thereby exposing the fine wiring pattern 520 in a predetermined area, and then fabricating the fine wiring 420 according to the obtained fine wiring pattern 520, as shown in FIGS. 7 to 9.
  • the fine wiring 420 is electrically connected to the chip pins, and at least two chips 300 are directly electrically connected through the fine wiring 420.
  • the line width of the basic connection line 410 is greater than the line width of the fine connection line 420.
  • the line width of the basic connection line 410 is greater than 10 micrometers, and some high-power lines or lines requiring thermal processing such as soldering may pass through the basic connection.
  • Line 410 is electrically coupled to chip 300.
  • the chip 300 can be powered by the base connection 410. Since the line width of the fine connection 420 is small and it is not suitable to withstand a large current, the base line 410 having a large line width or a large thickness can be provided to supply power to the chip 300.
  • the present embodiment divides the entire circuit into a fine area, a common area, and measures the reference mark 310 of the chip 300 in the fine area, and precisely designs the fine wiring pattern 520 to create a fine line width.
  • the connection line 420 increases the connection density of the fine connection 420 between the chips 300; in the normal area, the base line 410 with a line width wider than the fine connection line 420 is formed in a fast and low-cost manner, and the manufacturing efficiency of the integrated lifting circuit is improved. While controlling costs.
  • the basic connection 410 is electrically connected to the chip 300 or electrically connected to the electronic component 330.
  • the photoresist 500 is disposed in the region of the fine wiring 420, and the fine wiring 420 is fabricated by using the microelectromechanical system with the DMD chip described in the first embodiment to directly electrically connect at least two chips 300 through the fine wiring 420. , as shown in Figures 19 to 21.
  • the position sensor detects the position information of the reference mark 310, and the pattern design system accurately designs the fine connection pattern 520 between the chips 300 according to the position information of the reference mark 310 measured by the position sensor, and obtains the fine connection pattern 520. To ensure the precise connection of the fine connection 420 to the chip 300.
  • the first circuit layer 610, the second circuit layer 620, and the external contact pins 430 electrically connected to the chip 300 or the basic connection 410 are continuously stacked to form a 3D circuit board, such as Figure 22 shows.
  • the thickness of the basic connection 410 is greater than the thickness of the fine connection 420, and the thickness of the basic connection 410 may be greater than 10 micrometers, and the thickness of the fine connection 420 is less than 10 micrometers.
  • the basic connection 410 and the fine connection 420 are separately fabricated, the basic connection 410 is first made, and the fine connection 420 is formed. Finally, the additional package layer 210 is provided to protect the fine connection 420, and the fine connection 420 is ensured after the fine connection 420 is set. The chip pins are precisely connected and minimize the possibility that the fine wiring 420 is destroyed by subsequent processes.
  • the basic connection 410 is set, and then the base connection 410 and the chip 300 are package-fixed by the encapsulation layer 200, because the line width of the basic connection 410 is larger than the line width of the fine connection 420 or the thickness of the basic connection 410 is larger than the fine connection.
  • the thickness of the 420, the line width of the base connection 410 itself can compensate for the displacement displacement caused by the package fixing process to a certain extent, and the relative position of the basic connection 410 and the chip 300 is limited after the package is fixed, and the fine connection 420 is not affected. Production.
  • the basic connection 410 is made, and then the fine connection 420 is formed.
  • the additional package layer 210 is provided to protect the fine connection 420, ensuring that the fine connection 420 is finely connected to the chip pins after the fine connection 420 is set, and the fine connection is minimized. Line 420 is likely to be destroyed by subsequent processes.
  • the dielectric layer 110 can be selected to be a dielectric, which facilitates plating a layer of conductive material thereon to form the base wiring 410.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

La présente invention concerne un procédé de sortance de puce, comprenant : des puces comportant des marques de référence, et l'encapsulation et la fixation d'au moins deux puces avec des couches d'encapsulation; après l'encapsulation, selon les marques de référence des deux puces, la conception d'un motif de ligne fine entre les puces, la largeur d'une ligne fine étant inférieure à 10 micromètres; et l'utilisation d'un système micro-électromécanique pour fabriquer la ligne fine, le système micro-électromécanique comprenant une source de lumière, un dispositif de commande, et un dispositif de commutation optique relié bout à bout au dispositif de commande; l'agencement d'une résine photosensible sur des surfaces des puces et/ou des couches d'encapsulation, le dispositif de commande commandant un système de commutation optique pour graver le motif de ligne fine sur la résine photosensible, et la fabrication de la ligne fine selon le motif de ligne fine, les au moins deux puces étant directement reliées au moyen de la ligne fine électriquement. Une ligne fine à haute densité est obtenue, et une vitesse de transmission élevée peut être obtenue en reliant les puces au moyen de la ligne de connexion fine à haute densité.
PCT/CN2017/076431 2017-03-13 2017-03-13 Procédé de sortance de puce WO2018165815A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/076431 WO2018165815A1 (fr) 2017-03-13 2017-03-13 Procédé de sortance de puce

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/076431 WO2018165815A1 (fr) 2017-03-13 2017-03-13 Procédé de sortance de puce

Publications (1)

Publication Number Publication Date
WO2018165815A1 true WO2018165815A1 (fr) 2018-09-20

Family

ID=63521809

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/076431 WO2018165815A1 (fr) 2017-03-13 2017-03-13 Procédé de sortance de puce

Country Status (1)

Country Link
WO (1) WO2018165815A1 (fr)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1385889A (zh) * 2001-05-14 2002-12-18 世界先进积体电路股份有限公司 下埋式微细金属连线的制造方法
CN101609814A (zh) * 2008-06-17 2009-12-23 三星电子株式会社 半导体器件及存储系统的形成方法
CN202528561U (zh) * 2011-12-23 2012-11-14 昆山允升吉光电科技有限公司 一种具有辅助栅线的太阳能电池电极印刷网板
CN103013370A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种各向异性导电胶膜及电子装置
CN105428317A (zh) * 2014-09-12 2016-03-23 中国科学院微电子研究所 半导体器件制造方法
CN105590900A (zh) * 2010-05-20 2016-05-18 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN106098630A (zh) * 2016-08-09 2016-11-09 中芯长电半导体（江阴）有限公司 一种扇出型晶圆级封装方法及封装件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1385889A (zh) * 2001-05-14 2002-12-18 世界先进积体电路股份有限公司 下埋式微细金属连线的制造方法
CN101609814A (zh) * 2008-06-17 2009-12-23 三星电子株式会社 半导体器件及存储系统的形成方法
CN105590900A (zh) * 2010-05-20 2016-05-18 台湾积体电路制造股份有限公司 半导体装置及其制造方法
CN202528561U (zh) * 2011-12-23 2012-11-14 昆山允升吉光电科技有限公司 一种具有辅助栅线的太阳能电池电极印刷网板
CN103013370A (zh) * 2012-12-14 2013-04-03 京东方科技集团股份有限公司 一种各向异性导电胶膜及电子装置
CN105428317A (zh) * 2014-09-12 2016-03-23 中国科学院微电子研究所 半导体器件制造方法
CN106098630A (zh) * 2016-08-09 2016-11-09 中芯长电半导体（江阴）有限公司 一种扇出型晶圆级封装方法及封装件

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