WO2018166264A1

WO2018166264A1 - Packaged chip and packaging method

Info

Publication number: WO2018166264A1
Application number: PCT/CN2017/117764
Authority: WO
Inventors: 李志雄; 庞卫文; 何宏; 胡宏辉
Original assignee: 深圳市江波龙电子有限公司
Priority date: 2017-03-14
Filing date: 2017-12-21
Publication date: 2018-09-20
Also published as: CN107093593B; CN107093593A

Abstract

The present application relates to the technical field of chip packaging. Provided are a packaged chip and a packaging method. The packaged chip comprises a printed circuit board, a chip provided on the upper surface of the printed circuit board, and a packaging encapsulant provided on the surface of the printed circuit board and used for packaging the chip. First solder balls are provided on the lower surface of the printed circuit board and at positions corresponding to the packaging encapsulant. The chip is fixed on the printed circuit board via second solder balls. A via is provided on the printed circuit board. The via is arranged below the chip. In the present application, the via is provided on the printed circuit board at a position corresponding to the chip, during secondary SMT, air between the chip and the printed circuit board is expelled through the via, thus preventing the phenomenon of the second solder balls bursting or the printed circuit board bulging, and increasing the yield of the packaged chip.

Description

Package chip and packaging method

Technical field

The present application relates to the field of chip packaging technology, and more particularly to a packaged chip and a packaging method.

Background technique

The existing BGA (Ball Grid Array) package chip has a solder ball disposed under the BGA chip. Therefore, when molding, the package colloid does not flow under the BGA chip or cannot fill the BGA chip. The space is such that a closed space is formed between the BGA chip and the printed circuit board. When the secondary SMT is performed, the residual air in the closed space is thermally expanded, causing the surrounding solder balls to burst or causing defects such as drums on the printed circuit board. phenomenon. In order to solve this technical problem, it is generally adopted to increase the heat dissipation material inside and outside the chip to dissipate the heat quickly to avoid the air in the enclosed space being thermally expanded. In this way, not only the cost of the chip is increased, but also the volume of the packaged chip is increased.

Application content

The purpose of the present application is to provide a packaged chip and a packaging method, which are intended to solve the problem that the prior art BGA package chip is easy to burst when the secondary SMT is used, or the printed circuit board is easy to produce a bulge.

In order to solve the above technical problem, the technical solution of the present application is to provide a packaged chip, including a printed circuit board, a chip disposed on a surface of the printed circuit board, and a surface of the printed circuit board for encapsulating the a package encapsulant of the chip, a first solder ball is disposed on a lower surface of the printed circuit board and corresponding to the encapsulant, and the chip is fixed on the printed circuit board by a second solder ball, the printed circuit board A through hole is provided, the through hole being located below the chip.

Preferably, the chip is centrally disposed on the printed circuit board, and the through hole is located at a center position below the chip.

Preferably, a surface of the printed circuit board and a baffle is disposed around the chip.

Preferably, the chip is a DRAM chip provided with the second solder ball.

Preferably, the number of the chips is plural, and the number of the through holes is plural, and the through holes are respectively disposed under each of the chips.

Preferably, the number of the through holes is one, and the diameter of the through holes is 1.27±0.05 mm.

Preferably, the number of the through holes is plural, and the plurality of through holes are evenly distributed, and the diameter of each of the through holes is 0.3±0.05 mm.

Preferably, the number of the through holes is nine.

The application also provides a packaging method for a packaged chip, comprising the following steps:

Providing a through hole on the printed circuit board;

Place a chip on the surface of the printed circuit board and above the through hole;

An encapsulant is disposed on the surface of the printed circuit board and the chip is molded therein.

Preferably, when the chip is disposed, a gap between the chip and the printed circuit board is less than 0.1 mm.

Preferably, when the chip is disposed, a baffle is disposed around the chip.

In the present application, a through hole is provided on the printed circuit board and corresponding to the chip, and in the second SMT, air between the chip and the printed circuit board is discharged through the through hole, thereby preventing the second solder ball from bursting or the printed circuit board The phenomenon of bulging is generated, and the yield of the packaged chip is improved.

DRAWINGS

The one or more embodiments are exemplified by the accompanying drawings in the accompanying drawings, and FIG. The figures in the drawings do not constitute a scale limitation unless otherwise stated.

1 is a cross-sectional view of a packaged chip provided by an embodiment of the present application;

2 is a bottom view of a packaged chip provided by an embodiment of the present application;

FIG. 3 is a flowchart of a method for packaging a packaged chip according to an embodiment of the present application.

detailed description

In order to make the objects, technical solutions, and advantages of the present application more comprehensible, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the application and are not intended to be limiting.

It is to be noted that when an element is referred to as being "fixed" or "in" another element, it can be directly on the other element or indirectly. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or indirectly connected to the other element.

It should also be noted that the terms of the left, right, up, and down orientations in this embodiment are merely relative concepts or reference to the normal use state of the product, and should not be considered as limiting.

Referring to FIG. 1 and FIG. 2, an embodiment of the present application provides a packaged chip, including a printed circuit board 10, a chip 20 disposed on an upper surface of the printed circuit board 10, and a surface disposed on the upper surface of the printed circuit board 10 for packaging the chip 20. The first solder ball 40 is disposed on the lower surface of the printed circuit board 10 and corresponding to the encapsulant 30. The chip 20 is fixed on the printed circuit board 10 through the second solder ball 50, and the printed circuit board 10 is provided with a through hole. 11. The through hole 11 is located below the chip 20.

In this embodiment, the through hole 11 is disposed on the printed circuit board 10 and corresponding to the chip 20. In the second SMT, the air between the chip 20 and the printed circuit board 10 is discharged from the through hole 11, thereby avoiding the second The solder ball 50 bursts or the printed circuit board 10 generates a bulging phenomenon, which improves the yield of the packaged chip.

Preferably, in this embodiment, the chip 20 is centrally disposed on the upper surface of the printed circuit board 10, and the through hole 11 is located at a center position below the chip 20, that is, the through hole 11 is located at the center of the chip 20. The through hole 11 is provided here, and in the case of the secondary SMT, the air remaining between the chip 20 and the printed circuit board 10 can be discharged better after being heated.

Further, in this embodiment, a baffle 21 is disposed on the upper surface of the printed circuit board 10 and around the chip 20. When molding, the baffle 21 can block the encapsulant 30, prevent the encapsulant 30 from flowing into the space below the chip 20, and flow into the through hole 11 to block the through hole 11 so that residual air cannot be discharged.

Referring to FIG. 2, in the embodiment, the chip 20 is a DRAM (Dynamic Random Access Memory) provided with a second solder ball 50. With the chip 20, the second tin on the chip 20 is directly used. The ball 50 secures the chip 20 to the printed circuit board 10.

In this embodiment, the number of the chips 20 is one, the number of the through holes 11 is one, and the diameter of the through holes 11 is 1.27±0.05 mm. Alternatively, a plurality of relatively small through holes 11 may be provided, and the plurality of small through holes 11 are evenly distributed, and the diameter of each of the small through holes 11 is 0.3 ± 0.05 mm. Specifically, the number of the through holes 11 can be set to nine.

Alternatively, the number of the chips 20 may be plural, and the number of the through holes 11 is also plural, and the through holes 11 are provided under each of the chips 20 to ensure that each of the chips 20 can be discharged through the through holes 11 below. Internal air.

In the embodiment, the encapsulant 30 is a relatively large encapsulating colloid. The large encapsulating colloid 30 has poor fluidity, so that the encapsulant 30 is difficult to flow under the chip 20 during molding, thereby effectively preventing the encapsulant 30 from flowing into the through hole 11 . Blocking the through hole 11 causes the internal gas to be discharged.

Referring to FIG. 3, an embodiment of the present application further provides a method for packaging a packaged chip, including the following steps:

S1, a through hole 11 is provided on the printed circuit board;

S2, placing the chip 20 on the upper surface of the printed circuit board 10 and above the through hole 11;

S3, an encapsulant 30 is disposed on the upper surface of the printed circuit board 10 and the chip 20 is molded therein.

In the step S1, the chip 20 is disposed at a centered position of the printed circuit board 10 such that the through hole 11 is also disposed at a centered position of the printed circuit board 10 when the through hole 11 is provided. Of course, when the position of the chip 20 is changed, the through hole 11 can also be set according to the position of the chip 20. The setting principle is that when the chip 20 is disposed, the through hole 11 is correspondingly located at the center of the chip 20, so that the air between the chip 20 and the printed circuit board 10 can be effectively discharged.

In this embodiment, a through hole 11 is provided. The diameter of the through hole 11 is 1.27 ± 0.05 mm. Alternatively, a plurality of relatively small through holes 11 may be provided, and the plurality of small through holes 11 are evenly distributed, and the diameter of each of the small through holes 11 is 0.3 ± 0.05 mm. Specifically, the number of the through holes 11 can be set to nine.

In this embodiment, one chip 20 is provided in the step S2. Of course, the number of the chips 20 may be plural, and the number of the through holes 11 is also plural. A through hole 11 is disposed under each of the chips 20 to ensure that each of the chips 20 can discharge the internal air through the through holes 11 below. .

In this embodiment, the chip 20 is a DRAM (Dynamic Random Access Memory) 20 provided with a second solder ball 50. With the chip 20, the second solder ball 50 on the chip 20 is directly used. The chip 20 is attached to the printed circuit board 10.

When the chip 20 is disposed, the gap between the chip 20 and the upper surface of the printed circuit board 10 is as small as possible, and the specific gap may be less than 0.1 mm. At the same time, in step S3, the large particle encapsulant 30 is selected. Such a large-particle encapsulating colloid has poor fluidity, so that it is difficult for the encapsulant 30 to flow under the chip 20 during molding, thereby effectively preventing the encapsulant 30 from flowing into the through-hole 11 and blocking the through-hole 11 so that internal gas cannot be discharged.

In the present embodiment, when the chip 20 is disposed, the shutter 21 is disposed around the chip 20. When molding, the baffle 21 can block the encapsulant 30, and prevent the encapsulant 30 from flowing into the space below the chip 20 and flowing into the through hole 11 to block the through hole 11 so that residual air cannot be discharged.

The above is only the preferred embodiment of the present application, and is not intended to limit the application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application are included in the scope of the present application. Inside.

Claims

A packaged chip comprising a printed circuit board, a chip disposed on a surface of the printed circuit board, and an encapsulant disposed on a surface of the printed circuit board for packaging the chip, the lower surface of the printed circuit board and a first solder ball is disposed at the corresponding portion of the encapsulant, and the chip is fixed on the printed circuit board by a second solder ball, wherein the printed circuit board is provided with a through hole, and the through hole is located Below the chip.
The packaged chip of claim 1 wherein said chip is centrally disposed on said printed circuit board and said via is located at a centered position below said chip.
The packaged chip according to claim 1, wherein a surface of the printed circuit board and a periphery of the chip are provided with a baffle.
The packaged chip of claim 1 wherein said chip is a DRAM chip provided with said second solder ball.
The packaged chip according to claim 1, wherein the number of the chips is plural, and the number of the through holes is plural, and the through holes are respectively disposed under each of the chips.
The packaged chip according to claim 1, wherein the number of the through holes is one, and the diameter of the through holes is 1.27 ± 0.05 mm.
The packaged chip according to claim 1, wherein the number of the through holes is plural, and the plurality of through holes are evenly distributed, and the diameter of each of the through holes is 0.3±0.05 mm.
The packaged chip according to claim 7, wherein the number of the through holes is nine.
A package method for packaging a chip, comprising: the following steps:

Providing a through hole on the printed circuit board;

Place a chip on the surface of the printed circuit board and above the through hole;

An encapsulant is disposed on the surface of the printed circuit board and the chip is molded therein.
The package method of a packaged chip according to claim 9, wherein a gap between the chip and the printed circuit board is less than 0.1 mm when the chip is disposed.
The package method of a packaged chip according to claim 9, wherein a baffle is disposed around the chip when the chip is disposed.