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WO2018166264A1 - Puce encapsulée et procédé d'encapsulation - Google Patents

Puce encapsulée et procédé d'encapsulation Download PDF

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Publication number
WO2018166264A1
WO2018166264A1 PCT/CN2017/117764 CN2017117764W WO2018166264A1 WO 2018166264 A1 WO2018166264 A1 WO 2018166264A1 CN 2017117764 W CN2017117764 W CN 2017117764W WO 2018166264 A1 WO2018166264 A1 WO 2018166264A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
circuit board
printed circuit
holes
disposed
Prior art date
Application number
PCT/CN2017/117764
Other languages
English (en)
Chinese (zh)
Inventor
李志雄
庞卫文
何宏
胡宏辉
Original Assignee
深圳市江波龙电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市江波龙电子有限公司 filed Critical 深圳市江波龙电子有限公司
Publication of WO2018166264A1 publication Critical patent/WO2018166264A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container

Definitions

  • the present application relates to the field of chip packaging technology, and more particularly to a packaged chip and a packaging method.
  • the existing BGA (Ball Grid Array) package chip has a solder ball disposed under the BGA chip. Therefore, when molding, the package colloid does not flow under the BGA chip or cannot fill the BGA chip.
  • the space is such that a closed space is formed between the BGA chip and the printed circuit board.
  • the secondary SMT is performed, the residual air in the closed space is thermally expanded, causing the surrounding solder balls to burst or causing defects such as drums on the printed circuit board. phenomenon.
  • it is generally adopted to increase the heat dissipation material inside and outside the chip to dissipate the heat quickly to avoid the air in the enclosed space being thermally expanded. In this way, not only the cost of the chip is increased, but also the volume of the packaged chip is increased.
  • the purpose of the present application is to provide a packaged chip and a packaging method, which are intended to solve the problem that the prior art BGA package chip is easy to burst when the secondary SMT is used, or the printed circuit board is easy to produce a bulge.
  • the technical solution of the present application is to provide a packaged chip, including a printed circuit board, a chip disposed on a surface of the printed circuit board, and a surface of the printed circuit board for encapsulating the a package encapsulant of the chip, a first solder ball is disposed on a lower surface of the printed circuit board and corresponding to the encapsulant, and the chip is fixed on the printed circuit board by a second solder ball, the printed circuit board A through hole is provided, the through hole being located below the chip.
  • the chip is centrally disposed on the printed circuit board, and the through hole is located at a center position below the chip.
  • a surface of the printed circuit board and a baffle is disposed around the chip.
  • the chip is a DRAM chip provided with the second solder ball.
  • the number of the chips is plural, and the number of the through holes is plural, and the through holes are respectively disposed under each of the chips.
  • the number of the through holes is one, and the diameter of the through holes is 1.27 ⁇ 0.05 mm.
  • the number of the through holes is plural, and the plurality of through holes are evenly distributed, and the diameter of each of the through holes is 0.3 ⁇ 0.05 mm.
  • the number of the through holes is nine.
  • the application also provides a packaging method for a packaged chip, comprising the following steps:
  • An encapsulant is disposed on the surface of the printed circuit board and the chip is molded therein.
  • a gap between the chip and the printed circuit board is less than 0.1 mm.
  • a baffle is disposed around the chip.
  • a through hole is provided on the printed circuit board and corresponding to the chip, and in the second SMT, air between the chip and the printed circuit board is discharged through the through hole, thereby preventing the second solder ball from bursting or the printed circuit board The phenomenon of bulging is generated, and the yield of the packaged chip is improved.
  • FIG. 1 is a cross-sectional view of a packaged chip provided by an embodiment of the present application.
  • FIG. 2 is a bottom view of a packaged chip provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for packaging a packaged chip according to an embodiment of the present application.
  • an embodiment of the present application provides a packaged chip, including a printed circuit board 10, a chip 20 disposed on an upper surface of the printed circuit board 10, and a surface disposed on the upper surface of the printed circuit board 10 for packaging the chip 20.
  • the first solder ball 40 is disposed on the lower surface of the printed circuit board 10 and corresponding to the encapsulant 30.
  • the chip 20 is fixed on the printed circuit board 10 through the second solder ball 50, and the printed circuit board 10 is provided with a through hole. 11. The through hole 11 is located below the chip 20.
  • the through hole 11 is disposed on the printed circuit board 10 and corresponding to the chip 20.
  • the air between the chip 20 and the printed circuit board 10 is discharged from the through hole 11, thereby avoiding the second
  • the solder ball 50 bursts or the printed circuit board 10 generates a bulging phenomenon, which improves the yield of the packaged chip.
  • the chip 20 is centrally disposed on the upper surface of the printed circuit board 10, and the through hole 11 is located at a center position below the chip 20, that is, the through hole 11 is located at the center of the chip 20.
  • the through hole 11 is provided here, and in the case of the secondary SMT, the air remaining between the chip 20 and the printed circuit board 10 can be discharged better after being heated.
  • a baffle 21 is disposed on the upper surface of the printed circuit board 10 and around the chip 20.
  • the baffle 21 can block the encapsulant 30, prevent the encapsulant 30 from flowing into the space below the chip 20, and flow into the through hole 11 to block the through hole 11 so that residual air cannot be discharged.
  • the chip 20 is a DRAM (Dynamic Random Access Memory) provided with a second solder ball 50. With the chip 20, the second tin on the chip 20 is directly used. The ball 50 secures the chip 20 to the printed circuit board 10.
  • DRAM Dynamic Random Access Memory
  • the number of the chips 20 is one
  • the number of the through holes 11 is one
  • the diameter of the through holes 11 is 1.27 ⁇ 0.05 mm.
  • a plurality of relatively small through holes 11 may be provided, and the plurality of small through holes 11 are evenly distributed, and the diameter of each of the small through holes 11 is 0.3 ⁇ 0.05 mm.
  • the number of the through holes 11 can be set to nine.
  • the number of the chips 20 may be plural, and the number of the through holes 11 is also plural, and the through holes 11 are provided under each of the chips 20 to ensure that each of the chips 20 can be discharged through the through holes 11 below. Internal air.
  • the encapsulant 30 is a relatively large encapsulating colloid.
  • the large encapsulating colloid 30 has poor fluidity, so that the encapsulant 30 is difficult to flow under the chip 20 during molding, thereby effectively preventing the encapsulant 30 from flowing into the through hole 11 . Blocking the through hole 11 causes the internal gas to be discharged.
  • an embodiment of the present application further provides a method for packaging a packaged chip, including the following steps:
  • a through hole 11 is provided on the printed circuit board
  • an encapsulant 30 is disposed on the upper surface of the printed circuit board 10 and the chip 20 is molded therein.
  • the chip 20 is disposed at a centered position of the printed circuit board 10 such that the through hole 11 is also disposed at a centered position of the printed circuit board 10 when the through hole 11 is provided.
  • the through hole 11 can also be set according to the position of the chip 20.
  • the setting principle is that when the chip 20 is disposed, the through hole 11 is correspondingly located at the center of the chip 20, so that the air between the chip 20 and the printed circuit board 10 can be effectively discharged.
  • a through hole 11 is provided.
  • the diameter of the through hole 11 is 1.27 ⁇ 0.05 mm.
  • a plurality of relatively small through holes 11 may be provided, and the plurality of small through holes 11 are evenly distributed, and the diameter of each of the small through holes 11 is 0.3 ⁇ 0.05 mm.
  • the number of the through holes 11 can be set to nine.
  • one chip 20 is provided in the step S2.
  • the number of the chips 20 may be plural, and the number of the through holes 11 is also plural.
  • a through hole 11 is disposed under each of the chips 20 to ensure that each of the chips 20 can discharge the internal air through the through holes 11 below. .
  • the chip 20 is a DRAM (Dynamic Random Access Memory) 20 provided with a second solder ball 50. With the chip 20, the second solder ball 50 on the chip 20 is directly used. The chip 20 is attached to the printed circuit board 10.
  • DRAM Dynamic Random Access Memory
  • the gap between the chip 20 and the upper surface of the printed circuit board 10 is as small as possible, and the specific gap may be less than 0.1 mm.
  • the large particle encapsulant 30 is selected.
  • Such a large-particle encapsulating colloid has poor fluidity, so that it is difficult for the encapsulant 30 to flow under the chip 20 during molding, thereby effectively preventing the encapsulant 30 from flowing into the through-hole 11 and blocking the through-hole 11 so that internal gas cannot be discharged.
  • the shutter 21 when the chip 20 is disposed, the shutter 21 is disposed around the chip 20.
  • the baffle 21 can block the encapsulant 30, and prevent the encapsulant 30 from flowing into the space below the chip 20 and flowing into the through hole 11 to block the through hole 11 so that residual air cannot be discharged.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

La présente invention se rapporte au domaine technique d'encapsulation de puce. L'invention concerne une puce encapsulée et un procédé d'encapsulation. La puce encapsulée comprend une carte de circuit imprimé, une puce disposée sur la surface supérieure de la carte de circuit imprimé, et un encapsulant d'encapsulation disposé sur la surface de la carte de circuit imprimé et utilisé pour encapsuler la puce. Des premières perles de soudure sont disposées sur la surface inférieure de la carte de circuit imprimé et à des positions correspondant à l'encapsulant d'encapsulation. La puce est fixée sur la carte de circuit imprimé par l'intermédiaire de secondes perles de soudure. Un trou d'interconnexion est prévu sur la carte de circuit imprimé. Le trou d'interconnexion est disposé au-dessous de la puce. Dans la présente invention, le trou d'interconnexion est disposé sur la carte de circuit imprimé à une position correspondant à la puce, pendant une SMT secondaire, de l'air entre la puce et la carte de circuit imprimé est expulsé par l'intermédiaire du trou d'interconnexion, ce qui permet d'empêcher le phénomène de rupture de la seconde perle de soudure ou de gonflement de la carte de circuit imprimé, et d'augmenter le rendement de la puce encapsulée.
PCT/CN2017/117764 2017-03-14 2017-12-21 Puce encapsulée et procédé d'encapsulation WO2018166264A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710148504.1A CN107093593B (zh) 2017-03-14 2017-03-14 一种封装芯片及封装方法
CN201710148504.1 2017-03-14

Publications (1)

Publication Number Publication Date
WO2018166264A1 true WO2018166264A1 (fr) 2018-09-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/117764 WO2018166264A1 (fr) 2017-03-14 2017-12-21 Puce encapsulée et procédé d'encapsulation

Country Status (2)

Country Link
CN (1) CN107093593B (fr)
WO (1) WO2018166264A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107093593B (zh) * 2017-03-14 2019-08-13 深圳市江波龙电子股份有限公司 一种封装芯片及封装方法
CN107393838A (zh) * 2017-04-20 2017-11-24 北京时代民芯科技有限公司 一种提高陶瓷qfp228封装芯片抗随机振动性能的板级加固方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997001865A1 (fr) * 1995-06-28 1997-01-16 Hitachi, Ltd. Dispositif a semi-conducteurs et son procede de fabrication
US20080157342A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
CN101459155A (zh) * 2007-12-12 2009-06-17 三星电子株式会社 印刷电路板及其形成方法、装置、系统和检测电路的方法
CN101945530A (zh) * 2009-07-09 2011-01-12 佛山市顺德区顺达电脑厂有限公司 焊盘具有排气通孔的印刷电路板
CN107093593A (zh) * 2017-03-14 2017-08-25 深圳市江波龙电子有限公司 一种封装芯片及封装方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201298552Y (zh) * 2008-11-18 2009-08-26 好德科技股份有限公司 球栅阵列封装芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997001865A1 (fr) * 1995-06-28 1997-01-16 Hitachi, Ltd. Dispositif a semi-conducteurs et son procede de fabrication
US20080157342A1 (en) * 2007-01-03 2008-07-03 Advanced Chip Engineering Technology Inc. Package with a marking structure and method of the same
CN101459155A (zh) * 2007-12-12 2009-06-17 三星电子株式会社 印刷电路板及其形成方法、装置、系统和检测电路的方法
CN101945530A (zh) * 2009-07-09 2011-01-12 佛山市顺德区顺达电脑厂有限公司 焊盘具有排气通孔的印刷电路板
CN107093593A (zh) * 2017-03-14 2017-08-25 深圳市江波龙电子有限公司 一种封装芯片及封装方法

Also Published As

Publication number Publication date
CN107093593A (zh) 2017-08-25
CN107093593B (zh) 2019-08-13

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