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WO2018171100A1 - Procédé d'encapsulation pour structure d'encapsulation à puce de transmission de puissance intégrée - Google Patents

Procédé d'encapsulation pour structure d'encapsulation à puce de transmission de puissance intégrée Download PDF

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Publication number
WO2018171100A1
WO2018171100A1 PCT/CN2017/095419 CN2017095419W WO2018171100A1 WO 2018171100 A1 WO2018171100 A1 WO 2018171100A1 CN 2017095419 W CN2017095419 W CN 2017095419W WO 2018171100 A1 WO2018171100 A1 WO 2018171100A1
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WO
WIPO (PCT)
Prior art keywords
chip
power transmission
power
layer
transmission chip
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Application number
PCT/CN2017/095419
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English (en)
Chinese (zh)
Inventor
林章申
林正忠
何志宏
Original Assignee
中芯长电半导体（江阴）有限公司
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Publication of WO2018171100A1 publication Critical patent/WO2018171100A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H10D84/992—Noise prevention, e.g. preventing crosstalk

Definitions

  • the active component comprises a controller and a buck converter
  • the passive component comprises a capacitor, an inductor and a resistor.
  • the method of forming the plastic seal layer includes any one or more of compression molding, transfer molding, liquid sealing molding, vacuum lamination, and spin coating.
  • the method of forming the conductive pillars comprises one or more of electroplating, electroless plating, silk screen printing, wire bonding.
  • the power transmission system of the entire system circuit board is implemented by the power transmission chip, which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • the power transmission chip which includes a controller, a buck converter, a capacitor (CAP (3T)), and an inductor (L (2T) )) and resistors, thus eliminating all passive components on the system board.
  • FIG. 1 is a process flow diagram showing a packaging method of a package structure integrated with a power transmission chip of the present invention.
  • FIG. 3 is a schematic view showing an encapsulation method of a package structure integrated with a power transmission chip of the present invention forming an adhesion layer on the carrier.
  • FIG. 7 is a schematic diagram showing a method of packaging a package structure integrated with a power transmission chip of the present invention to form a rewiring layer of the power transmission chip.
  • FIG. 8 is a diagram showing a packaging method of a package structure integrated with a power transmission chip according to the present invention, which is connected to the rewiring layer by a plurality of first bump structures and filled with the underfill. Schematic diagram of the gap between the electrical chip and the wiring layer.
  • the active component 301 includes a controller and a buck converter;
  • the passive component 302 includes a capacitor 3021, an inductor 3021, and a resistor (not shown).
  • the buck converter can be converted into tens of thousands of low voltages by high voltage, and the low voltage can form a plurality of power supply tracks through the subsequently formed conductive pillars and rewiring layers, and is formed by subsequent The first bump structure is docked with the top power chip.
  • step S3 is performed: forming a plastic sealing layer 304 covering the active component 301 and the passive component 302 on the adhesive layer 2, and grinding the plastic sealing layer to expose the Pad 303 (the thinning process is not shown).
  • the power chip 5 includes, but is not limited to, an ASIC Die.
  • the first bump structure 4 may adopt a mico-bump or other suitable bump structure.
  • the package structure may be combined with the package substrate by using the second bump structure, and the package substrate may be a printed circuit board (PCB) or other suitable package.
  • An external power supply voltage can be applied to the power transmission chip through the package substrate, and converted into a plurality of voltages required by the power chip by the power transmission chip, and the converted voltage is further passed through the power transmission chip A plurality of power supply tracks are applied to the power chip. Since the package structure of the present invention integrates a power transmission chip including passive components, parasitic resistance on a package substrate such as a PCB can be eliminated, thereby improving power transmission efficiency, improving response time of power control, and improving fidelity.
  • the present invention provides a new packaging method for integrating a power chip and a power transmission chip into a package structure using a three-dimensional chip stacking technology, which has the following beneficial effects: (1) using an existing active device The component and the passive component form an active 2.5D interposer, and then the electrical chip is integrated on the active 2.5D interposer through the microbump or other bump structure to obtain a three-dimensional stacked structure; wherein the electrical chip can be It is an Application Specific Integrated Circuit (ASIC). (2) In the three-dimensional stack structure, the active 2.5D interposer acts as a power transmission power chip, which is tightly integrated under the power chip, solving the problem of power transmission.
  • ASIC Application Specific Integrated Circuit

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

L'invention concerne un procédé d'encapsulation pour une structure d'encapsulation avec une puce de transmission de puissance intégrée (3). La structure d'encapsulation comprend une puce électrique (5) et la puce de transmission de puissance (3) connectée au-dessous de la puce électrique (5). La puce de transmission de puissance (3) est utilisée pour convertir une tension d'une source d'alimentation externe en une pluralité de tensions requises pour la puce électrique (5) et pour fournir une pluralité de rails d'alimentation électrique s'amarrant à la puce électrique (5). Dans le procédé d'encapsulation, la puce de transmission de puissance (3) est utilisée en tant que plaque intermédiaire de 2,5 D active et la puce électrique (5) est intégrée sur la plaque intermédiaire de 2,5D active au moyen d'une micro-bosse ou d'autres structures de bosse, de façon à obtenir une structure tridimensionnelle d'empilement de puces. Un système de transmission de puissance de toute la carte de circuit de système est réalisé grâce à la puce de transmission de puissance (3) et une résistance parasite sur un substrat d'encapsulation peut être éliminée, de sorte que l'efficacité de transmission de puissance peut être améliorée, le temps de réponse pour la commande de puissance peut être amélioré et la fidélité est améliorée.
PCT/CN2017/095419 2017-03-22 2017-08-01 Procédé d'encapsulation pour structure d'encapsulation à puce de transmission de puissance intégrée WO2018171100A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710172468.2A CN106887393B (zh) 2017-03-22 2017-03-22 集成有功率传输芯片的封装结构的封装方法
CN201710172468.2 2017-03-22

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Cited By (1)

* Cited by examiner, † Cited by third party
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US11387182B2 (en) * 2018-01-29 2022-07-12 Anhui Anuki Technologies Co., Ltd. Module structure and method for manufacturing the module structure

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CN106887393B (zh) * 2017-03-22 2018-10-19 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法
CN108133931B (zh) * 2018-01-29 2023-11-07 安徽安努奇科技有限公司 一种模组结构及其制作方法
US11315831B2 (en) 2019-07-22 2022-04-26 International Business Machines Corporation Dual redistribution layer structure
WO2021081943A1 (fr) * 2019-10-31 2021-05-06 华为技术有限公司 Structure d'encapsulation d'empilement de puces, son procédé d'encapsulation et dispositif électronique
CN115104179A (zh) * 2020-03-02 2022-09-23 华为技术有限公司 封装结构及封装结构的制作方法
CN112289743A (zh) * 2020-11-20 2021-01-29 中芯长电半导体（江阴）有限公司 一种晶圆系统级扇出型封装结构及其制作方法
CN113990843B (zh) * 2021-10-25 2023-06-27 上海壁仞智能科技有限公司 芯片组及其制造方法
CN116153795A (zh) * 2023-04-20 2023-05-23 广东赛昉科技有限公司 一种多芯片封装方法

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US20160372446A1 (en) * 2015-06-18 2016-12-22 Qualcomm Incorporated Low profile integrated circuit (ic) package comprising a plurality of dies
CN106887393A (zh) * 2017-03-22 2017-06-23 中芯长电半导体（江阴）有限公司 集成有功率传输芯片的封装结构的封装方法

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CN102157393A (zh) * 2011-03-22 2011-08-17 南通富士通微电子股份有限公司 扇出高密度封装方法
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CN106887393B (zh) 2018-10-19

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