WO2018176490A1

WO2018176490A1 - Cmos image sensor with xy address exposure control

Info

Publication number: WO2018176490A1
Application number: PCT/CN2017/079357
Authority: WO
Inventors: Makoto Monoi
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-04-01
Filing date: 2017-04-01
Publication date: 2018-10-04
Anticipated expiration: 2019-10-01
Also published as: CN110462831A; CN110462831B

Abstract

The present invention provides a CMOS image sensor. The CMOS image sensor includes: pixel circuits which are arranged in two dimensional manner, wherein each pixel circuit includes: a switching transistor (SW), a gate of which is connected to one of a horizontal pulse line and a vertical address line, a source of which is connected to the other of the horizontal pulse line and the vertical address line, and a drain of which is connected to a gate of a transfer gate (TG); the TG, the gate of which is connected to a drain of the SW, and a source of which is connected to a cathode of a photodiode (PD); and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG. The present invention achieves to control exposure time more finely and make the pixel size smaller.

Description

CMOS IMAGE SENSOR WITH XY ADDRESS EXPOSURE CONTROL

TECHNICAL FIELD

The present invention relates to an image sensor, in particular, a high dynamic range complementary metal oxide semiconductor (CMOS) image sensor.

BACKGROUND

Fig. 1 shows a circuit diagram of a pixel circuit of prior art of a general CMOS image sensor. The meaning of the abbreviations are as follows: PD: a photodiode where light is converted to signal electron, TG: a transfer gate that transfers signal charge to FD, FD: a floating diffusion where signal charge is converted to signal voltage, Cfd: capacitance of FD, RS: a reset gate that sets the voltage of FD, AMP: an amplifier transistor that converts signal voltage of FD to a low impedance output signal, SL: a selector transistor, ADC: an analog digital converter. The PD converts light into an electrical signal. The electrical signal is selectively transmitted to the FD via the TG. The FD is connected to a gate of the AMP, and an output signal is transmitted to the signal line via the SL. Accordingly, if gates of the TG and the SL are turned on, the output signal corresponding to the electrical signal from the PD is obtained on the signal line. The RS selectively resets an electrical charge accumulated in the FD.

Fig. 2 shows another circuit diagram of a pixel circuit of prior art of a general CMOS image sensor, Fig. 3 shows a top view of this pixel circuit arranged on a surface of a silicon substrate, Fig. 4 shows a cross sectional view of this pixel circuit arranged on the silicon substrate along an arrow in Fig. 3, and Fig. 5 shows a pulse timing chart for this pixel circuit. Referring to Fig. 2, eight PDs (for exmpla, PD_n, m, PD_n, m+1, PD_n+1, m, PD_n+1, m+1, PD_n+2, m, PD_n+2, m+1, PD_n+3, m, and PD_n+3, m+1) share one output circuit that consists of SL, AMP, RS, and FD. Assuming that m is 0, 4, 8, …, but not limited thereto, even-numbered PDs and odd-numbered PDs in the first row (PD_n, m and PD_n, m+1) are connected to TG pulse lines (VTGHe_n, VTGHo_n) , respectively. “VTGHe _n” is n-th VTGH line for TGs connected to even-numbered PDs in n-th row, and “VTGHo_n” is n-th VTGH line for TGs connected to odd-numbered PDs in n-th row. “VTG” denotes a gate of TG. For example, in Fig. 2, topmost PDs in columns m and m+2 are connected to VTGHe_n via TGs, and topmost PDs in columns m+1 and m+3 are connected to VTGHo_n via TGs. The pixel circuit including above-mentioned eight PDs and output circuit is repeated in the horizontal direction and the vertical direction, and forms an imaging area of an image sensor. Referring to Fig. 5, even-numbered PDs or odd-numbered PDs in a row of an image sensor are driven simultaneously and each pixel in the row has the same signal integration period (Tint) . When both VTGHe_n and RS are high, signal charge at PD_n, m is cleared. Tint starts at t1 (the falling edge of the first pulse of VTGHe_n) and ends at t3 (the falling edge of the second pulse of VTGHe_n) . Around t2, the signal charge is stored in the PD. As a wavy line is shown in Fig. 5, the time period between t1 and t2 is much longer than the time period between t2 and t3. At the falling edge of the third pulse of RS (the pulse of RS after t2 and before t3) , an FD voltage is set to a baseline level.

Fig. 6 shows the amount of signal on an imaging area of an image sensor. Generally, the incident light intensity into an image sensor decreases according to the distance from the center due to its optics characteristics. For example, the intensity at the corner decreases to 30％of that at the center. The amount of signal decreases in the edge and corner areas, and SNR (Signal to Noise Ratio) at these areas drops.

Prior art, for example, Japanese Unexamined Patent Application, First Publication No. 2015-171135 discloses a method to increase the amount of signal at the edge or corner area. By dividing TG pulse lines, integration period at the corner area is set longer than that at the center area. Thus, the amount of signal at the corner area increases.

In the prior art, additional TG lines in a row are required and a permissible number of TG lines is limited, so there is a difference of the amount of signal at the border between adjacent blocks. The SNR difference according to the difference of the amount of signal at the border is a problem of image quality.

Japanese Unexamined Patent Application, First Publication No. 2015-171135 discloses another method to control exposure time more finely but the embodiment is not enough.

SUMMARY

Pixel structures of high dynamic range CMOS image sensors in which exposure periods of pixels can be independently and locally controlled is disclosed.

According to a first aspect, a CMOS image sensor is provided The CMOS image sensor includes: pixel circuits which are arranged in two dimensional manner. Each pixel circuit includes: a switching transistor (SW) , a gate of which is connected to one of a horizontal pulse line and a vertical address line, a source of which is connected to the other of the horizontal pulse line and the vertical address line, and a drain of which is connected to a gate of a transfer gate (TG) ； the TG, the gate of which is connected to a drain of the SW, and a source of which is connected to a cathode of a photodiode (PD) ； and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG. In this constitution, because a switching device is one transistor and it is located in vertical line, XY address exposure control is achievable in small pixel size sensor.

In a first possible implementation manner of the first aspect, each pixel circuit further includes: a floating diffusion (FD) , a source of which is connected to the TG, and a drain of which is connected to a reset gate (RS) ； the RS, a source of which is connected to a power source voltage, and a drain of which is connected to the FD of said pixel circuit； and an amplifier transistor (AMP) , a gate of which is connected to the FD of said pixel circuit, and a source of which is connected to the power source voltage. A pulse is applied to the gate and the source of the SW and the gate of the RS, then a pulse is applied to the gate of the RS, and then a pulse is applied to the gate and the source of the SW.

With reference to the first aspect or the first possible implementation manner of the first aspect, in a second possible implementation manner of the first aspect, the CMOS image sensor includes a plurality of the TGs, the gates of which are connected to the drain of one SW.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the CMOS image sensor includes two or four or eight TGs, the gates of which are connected to the drain of one SW.

With reference to the second or the third possible implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, each pixel circuit further includes: a reset gate (RS) , a source of which is connected to a power source voltage, and a drain of which is connected to the FDs of said pixel circuit； and an amplifier transistor (AMP) , a gate of which is connected to the FDs of said pixel circuit, and a source of which is connected to the power source voltage. A pulse is applied to the gate and the source of the SW and the gate of the RS, then a pulse is applied to the gate of the RS, and then a pulse is applied to the gate and the source of the SW.

With reference to any of the first aspect or the first to fourth possible implementation manner of the first aspect, in a fifth possible implementation manner of the second aspect, the low level of the horizontal pulse line and/or the vertical address line is lower than 0V, and the SW is a PMOS transistor.

With reference to any of the first aspect or the first to fifth possible implementation manner of the second aspect, in a sixth possible implementation manner of the second aspect, some of the RS, AMP, and SW of each pixel circuit are arranged in one row in the horizontal direction, and the other are arranged in one row in the vertical direction.

With reference to any of the first aspect or the first to sixth possible implementation manner of the second aspect, in a seventh possible implementation manner of the second aspect, any of the TG, FD, SW, and RS is stacked on the PD.

With reference to any of the first aspect or the first to seventh possible implementation manner of the second aspect, in an eighth possible implementation manner of the second aspect, the CMOS image sensor further comprises a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.

A CMOS image sensor is provided according to the various implementation manners to control exposure time more finely and make the pixel size smaller.

BRIEF DESCRIPTION OF DRAWINGS

To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

FIG. 1 shows a circuit diagram of a pixel circuit of prior art of a general CMOS image sensor；

FIG. 2 shows another circuit diagram of a pixel circuit of prior art of a general CMOS image sensor；

FIG. 3 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；

FIG. 4 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 3；

FIG. 5 shows a pulse timing chart for the pixel circuit in Fig. 2；

FIG. 6 shows the amount of signal on an imaging area of an image sensor；

FIG. 7 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention；

FIG. 8 shows a top view of the pixel units arranged on a surface of a silicon substrate；

FIG. 9 shows a pulse timing chart for the pixel circuit in Fig. 7；

FIG. 10 shows another pulse timing chart for the pixel circuit in Fig. 7；

FIG. 11 shows a pixel circuit according to another embodiment of the present invention；

FIG. 12 shows a top view of the pixel circuit arranged on a surface of a silicon substrate；

FIG. 13 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 12；

FIG. 14 shows a pulse timing chart for the pixel circuit in Fig. 11；

FIG. 15 shows a circuit diagram of a pixel circuit according to yet another embodiment of the present invention；

FIG. 16 shows a top view of the pixel circuit arranged on a surface of a silicon substrate； and

FIG. 17 shows a pulse timing chart for the pixel circuit in Fig. 15.

DESCRIPTION OF EMBODIMENTS

The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are merely some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

Fig. 7 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention. An image sensor includes a plurality of pixel circuits. AMP, SL, Vsig line, and ADC, which are not shown in Fig. 7, are connected to FD in the same way as Fig. 2. VTGHe_n and VTGHo_n in Fig. 2 are replaced with a horizontal pulse line (VTGH_n) , a vertical address line (VTGV_m) , and a switching transistor (SW) .

The pixel circuit in Fig. 7 includes eight pixel units. A pixel unit is provided for each combination of four horizontal pulse lines (VTGH_n, VTGH_n+1, VTGH_n+2, and VTGH_n+3) and two vertical address lines (VTGV_m and VTGV_m+1) . Each pixel unit includes an SW, a gate of which is connected to a horizontal pulse line, a source of which is connected to a vertical address line, and a drain of which is connected to a gate of a TG； the TG, the gate of which is connected to a drain of the SW, a source of which is connected to a cathode of a PD, and a drain of which is connected to the FD； and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG. The gate of the SW may be connected to a horizontal pulse line, and the source of the SW may be connected to a vertical address line.

Fig. 8 shows a top view of the pixel units arranged on a surface of a silicon substrate. SWs are NMOS transistors and located in vertical lines in Fig. 8. The left half of the pixel circuit shown in Fig. 8 correspond to the pixel circuit shown in Fig. 7. In Fig. 8, four SWs are provided at the left side of four PDs. In order to put SW, PD areas decrease.

The horizontal pulse lines in Fig. 7 are split into groups, a floating diffusion (FD) is provided for each group of the horizontal pulse lines, and the pixel units connected to any of the horizontal pulse lines in each group are connected to the FD of each group. In one embodiment, every two horizontal pulse lines constitute one group. In Fig. 7, VTGH_n and VTGH_n+1 constitute one group, and VTGH_n+2 and VTGH_n+3 constitute one group. In Fig. 8, one FD (asmall black square shown in Fig. 8) is provided for every four PDs, the upper left FD and the lower left FD are connected to the left RS, and the upper right FD and the lower right FD are connected to the right RS. In other word, the FDs are split into two groups.

Each pixel circuit further includes: an RS, a source of which is connected to a power source voltage, and a drain of which is connected to all the FDs of said pixel circuit； an AMP (not shown in Fig. 7) , a gate of which is connected to all the FDs of said pixel circuit, a source of which is connected to the power source voltage, and a drain of which is connected to a source of an SL (not shown in Fig. 7) ； and the SL, the source of which is connected to a drain of the AMP, and a drain of which is connected to a signal line (not shown in Fig. 7) .

The function of SW in the pixel unit where a gate of TG (VTG_n, m) connects to a drain of SW, a gate of SW connects to a horizontal pulse line (VTGH_n) , and a source of SW connects to a vertical pulse line (VTGV_m) is explained here. In this example, SW is n-type MOS transistor and its threshold voltage is higher than 0. When VTGH_n and VTGV_m are high, VTG_n, m becomes high. When VTGH_n is high and VTGV_m is low (0) , VTG_n, m becomes low. When VTGH_n is low, VTG_n, m is floating and keeps its status regardless of the status of VTGV_m.

Fig. 9 shows a pulse timing chart for the pixel circuit in Fig. 7. Referring to Figs. 7 and Fig. 9, when both VTGH_n and VTGV_m are high, TG is ON and signal charge at PD_n, m (Fig. 7) is cleared. From t1 (the falling edge of the first pulse applied to VTG_n, m) , integration of signal charge starts and at t3 (the rising edge of the second pulse applied to VTG_n, m) , VTG_n, m is again ON and signal charge is transferred to FD. Integration period (Tint) is from t1 to t3 (from the falling edge of the first pulse to the falling edge of the second pulse applied to VTG_n, m) .

Fig. 10 shows another pulse timing chart for the pixel circuit in Fig. 7. In Fig. 9, VTGH is normally low except that TG is ON, and the gate of TG is normally floating. In Fig. 10, VTGH is normally high except that TG is ON, and the gate of TG is normally low. This means gate voltage is more stable.

Because a switching device is one transistor and it is located in vertical line, XY address exposure control is achievable in small pixel size sensor. Different from the pixel circuit in Fig. 2, the exposure period of the pixel in each column can be independently controlled.

Fig. 11 shows a pixel circuit according to another embodiment of the present invention. SWs are PMOS transistors. There is a case where low level of VTG_n, m is negative. In this case, SWs should be PMOS transistors. Other pixel transistors, AMP, RS, and SL are NMOS and located in a Pwell. But a PMOS transistor requires a Nwell region and a larger area.

Fig. 12 shows a top view of the pixel circuit arranged on a surface of a silicon substrate, and Fig. 13 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 12. In Fig. 13, one PD is adjacent to FD and located on PD2, and another PD is at the right end and located on PD2. TGs go through these PDs downward. PD2 extends from the inside to the back of the substrate, TG extends from the surface of the substrate to PD2, and charge moves from PD2 to TG. The long rectangle areas under FD and Nwell are p-type areas thicker than P-well, and narrow spaces are provided between these areas and PD2. SW and its Nwell are located between the PDs in the horizontal direction in Fig. 13, and AMP, SL, and RS transistors are located in the vertical direction in Fig. 12. In order to enlarge transistor area, transistors are stacked on photodiodes (PD2) . In order to transfer signal charge from PD2 to FD, TG extends in the vertical direction in Fig. 13. This enables charge transfer from a deep PD2 region to an FD area on the surface through a narrow width channel. In Fig. 4, most of the signal charge is stored in the PD region. The signal charge in PD2 is difficult to move to FD because PD2 is far from FD. The PD region in Fig. 13 is much smaller than that in Fig. 4 and can store much less signal charge. So, most of signal charge is stored in the PD2 region. Charge transfer from PD2 to FD is improved by the vertically extended TG.

Fig. 14 shows a pulse timing chart for the pixel circuit in Fig. 11. Low level of VTG_n, m, VTGH_n, and VTGV_m is negative. When VTGH_n is low and VTGV_m is high, TG is ON.

Fig. 15 shows a circuit diagram of a pixel circuit according to yet another embodiment of the present invention. An image sensor includes a plurality of pixel circuits. AMP, SL, Vsig line, and ADC, which are not shown in Fig. 15, are connected to FD in the same way as Fig. 2.

Referring to Fig. 15, the pixel circuit includes 32 pixel units. A pixel unit includes one PD and one TG (VTG in Fig. 15) , and is provided for each combination of four pairs of horizontal address lines ( (VTGHe_n, VTGHo_n) , (VTGHe_n+1, VTGHo_n+1) , (VTGHe_n+2, VTGHo_n+2) , and (VTGHe_n+3, VTGHo_n+3) ) and eight columns (m, m+1, m+2, m+3, m+4, m+5, m+6, and m+7) . m may be 0, 8, 16, …, but not limited to them. First and second SW are provided for each pair of horizontal address lines.

The pairs of the horizontal address lines are split into groups. In Fig. 15, every two pairs of the horizontal address lines constitute one group. An FD is provided for each two columns and for each group of pairs of horizontal address lines, and the pixel units connected to any of the pairs of horizontal pulse lines in each group among the pixel units corresponding to said two columns are connected to said FD.

A gate of the first SW is connected to one horizontal address line of the pair of the horizontal address lines (or a vertical address line) , a source of the first SW is connected to a vertical address line (or one horizontal address line of the pair of the horizontal address lines) , and a drain of the first SW is connected to the first pixel unit in said each two columns among the pixel units corresponding to the pair of the horizontal address lines to which the horizontal address line connected to the first SW belongs, and a gate of the second SW is connected to the other horizontal address line of the pair of the horizontal address lines (or a vertical address line) , a source of the second SW is connected to a vertical address line (or the other horizontal address line of the pair of the horizontal address lines) , and a drain of the second SW is connected to the second pixel unit in said each two columns among the pixel units corresponding to the pair of the horizontal address lines to which the horizontal address line connected to the second SW belongs.

Each pixel unit includes: a TG, a gate of which is connected to a drain of the SW connected to corresponding horizontal address line, a source of which is connected to a cathode of a PD, and a drain of which is connected to the FD； and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG.

In Fig. 15, each pixel circuit further includes: an RS, a source of which is connected to a power source voltage, and a drain of which is connected to all the FDs of said pixel circuit； an AMP (not shown in Fig. 15) , a gate of which is connected to all the FDs of said pixel circuit, a source of which is connected to the power source voltage, and a drain of which is connected to a source of an SL (not shown in Fig. 15) ； and the SL, the source of which is connected to the drain of the AMP, and a drain of which is connected to a signal line (not shown in Fig. 15) .

Fig. 16 shows a top view of the pixel circuit arranged on a surface of a silicon substrate. One SW is provided for four photodiodes. In Fig. 16, the SW can be put between RSs and between AMP/SLs in horizontal direction without narrowing the photodiode areas.

Fig. 17 shows a pulse timing chart for the pixel circuit in Fig. 15. As shown in Fig. 17, the same voltage is applied to four TGs of PD_n, m, PD_n, m+2, PD_n, m+4, and PD_n, m+6. Exposure control is not pixel by pixel, but group of four pixels is small enough for small difference of exposure time between adjacent blocks.

What is disclosed above is merely exemplary embodiments of the present invention, and certainly is not intended to limit the scope of protection scope of the present invention. A person of ordinary skill in the art may understand that all or some of the processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

A complementary metal oxide semiconductor (CMOS) image sensor, comprising:

pixel circuits which are arranged in two dimensional manner,

wherein each pixel circuit comprises:

a switching transistor (SW) , a gate of which is connected to one of a horizontal pulse line and a vertical address line, a source of which is connected to the other of the horizontal pulse line and the vertical address line, and a drain of which is connected to a gate of a transfer gate (TG) ；

the TG, the gate of which is connected to a drain of the SW, and a source of which is connected to a cathode of a photodiode (PD) ； and

the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG.
The CMOS image sensor according to claim 1, wherein each pixel circuit further comprises:

a floating diffusion (FD) , a source of which is connected to the TG, and a drain of which is connected to a reset gate (RS) ；

the RS, a source of which is connected to a power source voltage, and a drain of which is connected to the FD of said pixel circuit； and

an amplifier transistor (AMP) , a gate of which is connected to the FD of said pixel circuit, and a source of which is connected to the power source voltage,

wherein a pulse is applied to the gate and the source of the SW and the gate of the RS, then a pulse is applied to the gate of the RS, and then a pulse is applied to the gate and the source of the SW.
The CMOS image sensor according to claim 1 or 2, comprising a plurality of the TGs, the gates of which are connected to the drain of one SW.
The CMOS image sensor according to claim 3, comprising two or four or eight TGs, the gates of which are connected to the drain of one SW.
The CMOS image sensor according to claim 3 or 4, wherein each pixel circuit further comprises:

a reset gate (RS) , a source of which is connected to a power source voltage, and a drain of which is connected to the FDs of said pixel circuit； and

an amplifier transistor (AMP) , a gate of which is connected to the FDs of said pixel circuit, and a source of which is connected to the power source voltage,

wherein a pulse is applied to the gate and the source of the SW and the gate of the RS, then a pulse is applied to the gate of the RS, and then a pulse is applied to the gate and the source of the SW.
The CMOS image sensor according to any one of claims 1 to 5, wherein the low level of the horizontal pulse line and/or the vertical address line is lower than 0V, and the SW is a PMOS transistor.
The CMOS image sensor according to any one of claims 1 to 6, wherein some of the RS, AMP, and SW of each pixel circuit are arranged in one row in the horizontal direction, and the other are arranged in one row in the vertical direction.
The CMOS image sensor according to any one of claims 1 to 7, wherein any of the TG, FD, SW, and RS is stacked on the PD.
The CMOS image sensor according to any one of claims 1 to 8, further comprising a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.