[go: up one dir, main page]

WO2018176490A1 - Capteur d'image cmos ayant une commande d'exposition d'adresse xy - Google Patents

Capteur d'image cmos ayant une commande d'exposition d'adresse xy Download PDF

Info

Publication number
WO2018176490A1
WO2018176490A1 PCT/CN2017/079357 CN2017079357W WO2018176490A1 WO 2018176490 A1 WO2018176490 A1 WO 2018176490A1 CN 2017079357 W CN2017079357 W CN 2017079357W WO 2018176490 A1 WO2018176490 A1 WO 2018176490A1
Authority
WO
WIPO (PCT)
Prior art keywords
gate
source
image sensor
pixel circuit
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2017/079357
Other languages
English (en)
Inventor
Makoto Monoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to PCT/CN2017/079357 priority Critical patent/WO2018176490A1/fr
Priority to CN201780088776.5A priority patent/CN110462831B/zh
Publication of WO2018176490A1 publication Critical patent/WO2018176490A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/61—Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4"
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/803—Pixels having integrated switching, control, storage or amplification elements
    • H10F39/8037—Pixels having integrated switching, control, storage or amplification elements the integrated elements comprising a transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/813—Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels

Definitions

  • the present invention relates to an image sensor, in particular, a high dynamic range complementary metal oxide semiconductor (CMOS) image sensor.
  • CMOS complementary metal oxide semiconductor
  • Fig. 1 shows a circuit diagram of a pixel circuit of prior art of a general CMOS image sensor.
  • the meaning of the abbreviations are as follows: PD: a photodiode where light is converted to signal electron, TG: a transfer gate that transfers signal charge to FD, FD: a floating diffusion where signal charge is converted to signal voltage, Cfd: capacitance of FD, RS: a reset gate that sets the voltage of FD, AMP: an amplifier transistor that converts signal voltage of FD to a low impedance output signal, SL: a selector transistor, ADC: an analog digital converter.
  • the PD converts light into an electrical signal. The electrical signal is selectively transmitted to the FD via the TG.
  • the FD is connected to a gate of the AMP, and an output signal is transmitted to the signal line via the SL. Accordingly, if gates of the TG and the SL are turned on, the output signal corresponding to the electrical signal from the PD is obtained on the signal line.
  • the RS selectively resets an electrical charge accumulated in the FD.
  • Fig. 2 shows another circuit diagram of a pixel circuit of prior art of a general CMOS image sensor
  • Fig. 3 shows a top view of this pixel circuit arranged on a surface of a silicon substrate
  • Fig. 4 shows a cross sectional view of this pixel circuit arranged on the silicon substrate along an arrow in Fig. 3
  • Fig. 5 shows a pulse timing chart for this pixel circuit.
  • VTGHe _n is n-th VTGH line for TGs connected to even-numbered PDs in n-th row
  • VTGHo_n is n-th VTGH line for TGs connected to odd-numbered PDs in n-th row
  • “VTG” denotes a gate of TG.
  • topmost PDs in columns m and m+2 are connected to VTGHe_n via TGs
  • topmost PDs in columns m+1 and m+3 are connected to VTGHo_n via TGs.
  • the pixel circuit including above-mentioned eight PDs and output circuit is repeated in the horizontal direction and the vertical direction, and forms an imaging area of an image sensor.
  • Fig. 6 shows the amount of signal on an imaging area of an image sensor.
  • the incident light intensity into an image sensor decreases according to the distance from the center due to its optics characteristics. For example, the intensity at the corner decreases to 30%of that at the center.
  • the amount of signal decreases in the edge and corner areas, and SNR (Signal to Noise Ratio) at these areas drops.
  • Japanese Unexamined Patent Application, First Publication No. 2015-171135 discloses another method to control exposure time more finely but the embodiment is not enough.
  • Pixel structures of high dynamic range CMOS image sensors in which exposure periods of pixels can be independently and locally controlled is disclosed.
  • a CMOS image sensor includes: pixel circuits which are arranged in two dimensional manner.
  • Each pixel circuit includes: a switching transistor (SW) , a gate of which is connected to one of a horizontal pulse line and a vertical address line, a source of which is connected to the other of the horizontal pulse line and the vertical address line, and a drain of which is connected to a gate of a transfer gate (TG) ; the TG, the gate of which is connected to a drain of the SW, and a source of which is connected to a cathode of a photodiode (PD) ; and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG.
  • a switching device is one transistor and it is located in vertical line, XY address exposure control is achievable in small pixel size sensor.
  • each pixel circuit further includes: a floating diffusion (FD) , a source of which is connected to the TG, and a drain of which is connected to a reset gate (RS) ; the RS, a source of which is connected to a power source voltage, and a drain of which is connected to the FD of said pixel circuit; and an amplifier transistor (AMP) , a gate of which is connected to the FD of said pixel circuit, and a source of which is connected to the power source voltage.
  • FD floating diffusion
  • RS reset gate
  • AMP amplifier transistor
  • the CMOS image sensor includes a plurality of the TGs, the gates of which are connected to the drain of one SW.
  • the CMOS image sensor includes two or four or eight TGs, the gates of which are connected to the drain of one SW.
  • each pixel circuit further includes: a reset gate (RS) , a source of which is connected to a power source voltage, and a drain of which is connected to the FDs of said pixel circuit; and an amplifier transistor (AMP) , a gate of which is connected to the FDs of said pixel circuit, and a source of which is connected to the power source voltage.
  • RS reset gate
  • AMP amplifier transistor
  • the low level of the horizontal pulse line and/or the vertical address line is lower than 0V
  • the SW is a PMOS transistor.
  • some of the RS, AMP, and SW of each pixel circuit are arranged in one row in the horizontal direction, and the other are arranged in one row in the vertical direction.
  • any of the TG, FD, SW, and RS is stacked on the PD.
  • the CMOS image sensor further comprises a second PD which extends from the inside to the back of the substrate, the TG extends from the surface of the substrate to the second PD, and charge moves from the second PD to the TG.
  • a CMOS image sensor is provided according to the various implementation manners to control exposure time more finely and make the pixel size smaller.
  • FIG. 1 shows a circuit diagram of a pixel circuit of prior art of a general CMOS image sensor
  • FIG. 2 shows another circuit diagram of a pixel circuit of prior art of a general CMOS image sensor
  • FIG. 3 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 4 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 3;
  • FIG. 5 shows a pulse timing chart for the pixel circuit in Fig. 2;
  • FIG. 6 shows the amount of signal on an imaging area of an image sensor
  • FIG. 7 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention.
  • FIG. 8 shows a top view of the pixel units arranged on a surface of a silicon substrate
  • FIG. 9 shows a pulse timing chart for the pixel circuit in Fig. 7;
  • FIG. 10 shows another pulse timing chart for the pixel circuit in Fig. 7;
  • FIG. 11 shows a pixel circuit according to another embodiment of the present invention.
  • FIG. 12 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • FIG. 13 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 12;
  • FIG. 14 shows a pulse timing chart for the pixel circuit in Fig. 11;
  • FIG. 15 shows a circuit diagram of a pixel circuit according to yet another embodiment of the present invention.
  • FIG. 16 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • FIG. 17 shows a pulse timing chart for the pixel circuit in Fig. 15.
  • Fig. 7 shows a circuit diagram of a pixel circuit according to an embodiment of the present invention.
  • An image sensor includes a plurality of pixel circuits.
  • AMP, SL, Vsig line, and ADC, which are not shown in Fig. 7, are connected to FD in the same way as Fig. 2.
  • VTGHe_n and VTGHo_n in Fig. 2 are replaced with a horizontal pulse line (VTGH_n) , a vertical address line (VTGV_m) , and a switching transistor (SW) .
  • the pixel circuit in Fig. 7 includes eight pixel units.
  • a pixel unit is provided for each combination of four horizontal pulse lines (VTGH_n, VTGH_n+1, VTGH_n+2, and VTGH_n+3) and two vertical address lines (VTGV_m and VTGV_m+1) .
  • Each pixel unit includes an SW, a gate of which is connected to a horizontal pulse line, a source of which is connected to a vertical address line, and a drain of which is connected to a gate of a TG; the TG, the gate of which is connected to a drain of the SW, a source of which is connected to a cathode of a PD, and a drain of which is connected to the FD; and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG.
  • the gate of the SW may be connected to a horizontal pulse line, and the source of the SW may be connected to a vertical address line.
  • Fig. 8 shows a top view of the pixel units arranged on a surface of a silicon substrate.
  • SWs are NMOS transistors and located in vertical lines in Fig. 8.
  • the left half of the pixel circuit shown in Fig. 8 correspond to the pixel circuit shown in Fig. 7.
  • four SWs are provided at the left side of four PDs. In order to put SW, PD areas decrease.
  • the horizontal pulse lines in Fig. 7 are split into groups, a floating diffusion (FD) is provided for each group of the horizontal pulse lines, and the pixel units connected to any of the horizontal pulse lines in each group are connected to the FD of each group.
  • every two horizontal pulse lines constitute one group.
  • VTGH_n and VTGH_n+1 constitute one group
  • VTGH_n+2 and VTGH_n+3 constitute one group.
  • one FD (asmall black square shown in Fig. 8) is provided for every four PDs, the upper left FD and the lower left FD are connected to the left RS, and the upper right FD and the lower right FD are connected to the right RS.
  • the FDs are split into two groups.
  • Each pixel circuit further includes: an RS, a source of which is connected to a power source voltage, and a drain of which is connected to all the FDs of said pixel circuit; an AMP (not shown in Fig. 7) , a gate of which is connected to all the FDs of said pixel circuit, a source of which is connected to the power source voltage, and a drain of which is connected to a source of an SL (not shown in Fig. 7) ; and the SL, the source of which is connected to a drain of the AMP, and a drain of which is connected to a signal line (not shown in Fig. 7) .
  • SW is n-type MOS transistor and its threshold voltage is higher than 0.
  • VTG_n When VTGH_n and VTGV_m are high, VTG_n, m becomes high.
  • VTGH_n When VTGH_n is high and VTGV_m is low (0) , VTG_n, m becomes low.
  • VTG_n, m When VTGH_n is low, VTG_n, m is floating and keeps its status regardless of the status of VTGV_m.
  • Fig. 9 shows a pulse timing chart for the pixel circuit in Fig. 7.
  • TG is ON and signal charge at PD_n, m (Fig. 7) is cleared.
  • t1 the falling edge of the first pulse applied to VTG_n, m
  • integration of signal charge starts and at t3 (the rising edge of the second pulse applied to VTG_n, m)
  • VTG_n, m is again ON and signal charge is transferred to FD.
  • Integration period (Tint) is from t1 to t3 (from the falling edge of the first pulse to the falling edge of the second pulse applied to VTG_n, m) .
  • Fig. 10 shows another pulse timing chart for the pixel circuit in Fig. 7.
  • VTGH is normally low except that TG is ON, and the gate of TG is normally floating.
  • VTGH is normally high except that TG is ON, and the gate of TG is normally low. This means gate voltage is more stable.
  • a switching device is one transistor and it is located in vertical line, XY address exposure control is achievable in small pixel size sensor. Different from the pixel circuit in Fig. 2, the exposure period of the pixel in each column can be independently controlled.
  • Fig. 11 shows a pixel circuit according to another embodiment of the present invention.
  • SWs are PMOS transistors. There is a case where low level of VTG_n, m is negative. In this case, SWs should be PMOS transistors.
  • Other pixel transistors, AMP, RS, and SL are NMOS and located in a Pwell. But a PMOS transistor requires a Nwell region and a larger area.
  • Fig. 12 shows a top view of the pixel circuit arranged on a surface of a silicon substrate
  • Fig. 13 shows a cross sectional view of the pixel circuit arranged on the silicon substrate along an arrow in Fig. 12.
  • one PD is adjacent to FD and located on PD2, and another PD is at the right end and located on PD2.
  • TGs go through these PDs downward.
  • PD2 extends from the inside to the back of the substrate, TG extends from the surface of the substrate to PD2, and charge moves from PD2 to TG.
  • the long rectangle areas under FD and Nwell are p-type areas thicker than P-well, and narrow spaces are provided between these areas and PD2.
  • SW and its Nwell are located between the PDs in the horizontal direction in Fig. 13, and AMP, SL, and RS transistors are located in the vertical direction in Fig. 12.
  • transistors are stacked on photodiodes (PD2) .
  • PD2 photodiodes
  • TG extends in the vertical direction in Fig. 13. This enables charge transfer from a deep PD2 region to an FD area on the surface through a narrow width channel.
  • most of the signal charge is stored in the PD region.
  • the signal charge in PD2 is difficult to move to FD because PD2 is far from FD.
  • the PD region in Fig. 13 is much smaller than that in Fig. 4 and can store much less signal charge. So, most of signal charge is stored in the PD2 region. Charge transfer from PD2 to FD is improved by the vertically extended TG.
  • Fig. 14 shows a pulse timing chart for the pixel circuit in Fig. 11.
  • Low level of VTG_n, m, VTGH_n, and VTGV_m is negative.
  • VTGH_n is low and VTGV_m is high, TG is ON.
  • Fig. 15 shows a circuit diagram of a pixel circuit according to yet another embodiment of the present invention.
  • An image sensor includes a plurality of pixel circuits.
  • AMP, SL, Vsig line, and ADC, which are not shown in Fig. 15, are connected to FD in the same way as Fig. 2.
  • the pixel circuit includes 32 pixel units.
  • a pixel unit includes one PD and one TG (VTG in Fig. 15) , and is provided for each combination of four pairs of horizontal address lines ( (VTGHe_n, VTGHo_n) , (VTGHe_n+1, VTGHo_n+1) , (VTGHe_n+2, VTGHo_n+2) , and (VTGHe_n+3, VTGHo_n+3) ) and eight columns (m, m+1, m+2, m+3, m+4, m+5, m+6, and m+7) .
  • m may be 0, 8, 16, ..., but not limited to them.
  • First and second SW are provided for each pair of horizontal address lines.
  • the pairs of the horizontal address lines are split into groups.
  • every two pairs of the horizontal address lines constitute one group.
  • An FD is provided for each two columns and for each group of pairs of horizontal address lines, and the pixel units connected to any of the pairs of horizontal pulse lines in each group among the pixel units corresponding to said two columns are connected to said FD.
  • a gate of the first SW is connected to one horizontal address line of the pair of the horizontal address lines (or a vertical address line) , a source of the first SW is connected to a vertical address line (or one horizontal address line of the pair of the horizontal address lines) , and a drain of the first SW is connected to the first pixel unit in said each two columns among the pixel units corresponding to the pair of the horizontal address lines to which the horizontal address line connected to the first SW belongs, and a gate of the second SW is connected to the other horizontal address line of the pair of the horizontal address lines (or a vertical address line) , a source of the second SW is connected to a vertical address line (or the other horizontal address line of the pair of the horizontal address lines) , and a drain of the second SW is connected to the second pixel unit in said each two columns among the pixel units corresponding to the pair of the horizontal address lines to which the horizontal address line connected to the second SW belongs.
  • Each pixel unit includes: a TG, a gate of which is connected to a drain of the SW connected to corresponding horizontal address line, a source of which is connected to a cathode of a PD, and a drain of which is connected to the FD; and the PD, an anode of which is connected to a ground, and the cathode of which is connected to a source of the TG.
  • each pixel circuit further includes: an RS, a source of which is connected to a power source voltage, and a drain of which is connected to all the FDs of said pixel circuit; an AMP (not shown in Fig. 15) , a gate of which is connected to all the FDs of said pixel circuit, a source of which is connected to the power source voltage, and a drain of which is connected to a source of an SL (not shown in Fig. 15) ; and the SL, the source of which is connected to the drain of the AMP, and a drain of which is connected to a signal line (not shown in Fig. 15) .
  • Fig. 16 shows a top view of the pixel circuit arranged on a surface of a silicon substrate.
  • One SW is provided for four photodiodes.
  • the SW can be put between RSs and between AMP/SLs in horizontal direction without narrowing the photodiode areas.
  • Fig. 17 shows a pulse timing chart for the pixel circuit in Fig. 15. As shown in Fig. 17, the same voltage is applied to four TGs of PD_n, m, PD_n, m+2, PD_n, m+4, and PD_n, m+6. Exposure control is not pixel by pixel, but group of four pixels is small enough for small difference of exposure time between adjacent blocks.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

La présente invention concerne un capteur d'image CMOS. Le capteur d'image CMOS comprend : des circuits de pixel qui sont agencés de manière bidimensionnelle, chaque circuit de pixel comprenant : un transistor de commutation (SW), dont une grille est connectée à une ligne d'impulsion horizontale ou à une ligne d'adresse verticale, dont une source est connectée à l'autre de la ligne d'impulsion horizontale et de la ligne d'adresse verticale, et dont un drain est connecté à une grille d'une grille de transfert (TG) ; la grille TG dont la grille est connectée à un drain du transistor SW, et dont une source est connectée à une cathode d'une photodiode (PD) ; et la photodiode, dont une anode est connectée à une masse, et dont la cathode est connectée à une source de la grille TG. La présente invention permet de réguler le temps d'exposition de manière plus fine et de rendre la taille de pixel plus petite.
PCT/CN2017/079357 2017-04-01 2017-04-01 Capteur d'image cmos ayant une commande d'exposition d'adresse xy Ceased WO2018176490A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2017/079357 WO2018176490A1 (fr) 2017-04-01 2017-04-01 Capteur d'image cmos ayant une commande d'exposition d'adresse xy
CN201780088776.5A CN110462831B (zh) 2017-04-01 2017-04-01 控制xy地址曝光的cmos图像传感器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2017/079357 WO2018176490A1 (fr) 2017-04-01 2017-04-01 Capteur d'image cmos ayant une commande d'exposition d'adresse xy

Publications (1)

Publication Number Publication Date
WO2018176490A1 true WO2018176490A1 (fr) 2018-10-04

Family

ID=63674091

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/079357 Ceased WO2018176490A1 (fr) 2017-04-01 2017-04-01 Capteur d'image cmos ayant une commande d'exposition d'adresse xy

Country Status (2)

Country Link
CN (1) CN110462831B (fr)
WO (1) WO2018176490A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858839A (zh) * 2005-05-02 2006-11-08 株式会社半导体能源研究所 显示装置的驱动方法
CN101192370A (zh) * 2006-12-01 2008-06-04 索尼株式会社 显示装置
CN103139496A (zh) * 2013-02-27 2013-06-05 天津大学 基于深亚微米cmos工艺适用于大规模像素阵列的像素结构

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040246355A1 (en) * 2003-06-06 2004-12-09 Ji Ung Lee Storage capacitor array for a solid state radiation imager
JP2011015219A (ja) * 2009-07-02 2011-01-20 Toshiba Corp 固体撮像装置
CN203813866U (zh) * 2014-04-30 2014-09-03 北京思比科微电子技术股份有限公司 高灵敏度cmos图像传感器共享型像素结构
US9706142B2 (en) * 2015-09-23 2017-07-11 Semiconductor Components Industries, Llc High dynamic range and global shutter image sensor pixels having charge overflow signal detecting structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1858839A (zh) * 2005-05-02 2006-11-08 株式会社半导体能源研究所 显示装置的驱动方法
CN101192370A (zh) * 2006-12-01 2008-06-04 索尼株式会社 显示装置
CN103139496A (zh) * 2013-02-27 2013-06-05 天津大学 基于深亚微米cmos工艺适用于大规模像素阵列的像素结构

Also Published As

Publication number Publication date
CN110462831A (zh) 2019-11-15
CN110462831B (zh) 2021-11-26

Similar Documents

Publication Publication Date Title
US11683601B2 (en) Imaging device and electronic apparatus
US9602750B2 (en) Image sensor pixels having built-in variable gain feedback amplifier circuitry
US10332928B2 (en) Solid-state imaging device, method for manufacturing solid-state imaging device, and electronic apparatus
US8471310B2 (en) Image sensor pixels with back-gate-modulated vertical transistor
CN107112334B (zh) 光传感器及其信号读出方法、以及固体摄像装置及其信号读出方法
CN205159323U (zh) 图像传感器像素电路及处理器系统
US7964929B2 (en) Method and apparatus providing imager pixels with shared pixel components
US8817151B2 (en) Solid-state imaging device and method for solid-state imaging device for transferring charge from a photoelectric conversion portion to a floating diffusion
CN103140926B (zh) 固态成像装置
US9641778B2 (en) Imaging device and method for driving the same
WO2007027517A2 (fr) Procede et appareil a grille de stockage partage a deux voies sur un pixel partage a quatre voies
US8710420B2 (en) Image sensor pixels with junction gate photodiodes
US9391102B2 (en) Imaging device
WO2020059580A1 (fr) Dispositif d'imagerie à semi-conducteur et appareil électronique
KR100820520B1 (ko) 고체촬상장치
US11031430B2 (en) Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same
JP7198675B2 (ja) 固体撮像素子、その駆動回路および撮像装置
WO2018176490A1 (fr) Capteur d'image cmos ayant une commande d'exposition d'adresse xy
US8587041B2 (en) Solid-state imaging device and method of manufacturing the same
JP2017011300A (ja) 固体撮像装置およびカメラ
WO2018165832A1 (fr) Capteur d'image cmos
JP2014179640A (ja) 光電変換装置
JP2011054880A (ja) 固体撮像装置及びその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17903427

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17903427

Country of ref document: EP

Kind code of ref document: A1