WO2018101480A1 - Puce semiconductrice pour authentification individuelle, support d'authentification individuel et procédé d'authentification individuelle - Google Patents
Puce semiconductrice pour authentification individuelle, support d'authentification individuel et procédé d'authentification individuelle Download PDFInfo
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- WO2018101480A1 WO2018101480A1 PCT/JP2017/043388 JP2017043388W WO2018101480A1 WO 2018101480 A1 WO2018101480 A1 WO 2018101480A1 JP 2017043388 W JP2017043388 W JP 2017043388W WO 2018101480 A1 WO2018101480 A1 WO 2018101480A1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
- B42D—BOOKS; BOOK COVERS; LOOSE LEAVES; PRINTED MATTER CHARACTERISED BY IDENTIFICATION OR SECURITY FEATURES; PRINTED MATTER OF SPECIAL FORMAT OR STYLE NOT OTHERWISE PROVIDED FOR; DEVICES FOR USE THEREWITH AND NOT OTHERWISE PROVIDED FOR; MOVABLE-STRIP WRITING OR READING APPARATUS
- B42D25/00—Information-bearing cards or sheet-like structures characterised by identification or security features; Manufacture thereof
- B42D25/30—Identification or security features, e.g. for preventing forgery
- B42D25/324—Reliefs
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B42—BOOKBINDING; ALBUMS; FILES; SPECIAL PRINTED MATTER
- B42D—BOOKS; BOOK COVERS; LOOSE LEAVES; PRINTED MATTER CHARACTERISED BY IDENTIFICATION OR SECURITY FEATURES; PRINTED MATTER OF SPECIAL FORMAT OR STYLE NOT OTHERWISE PROVIDED FOR; DEVICES FOR USE THEREWITH AND NOT OTHERWISE PROVIDED FOR; MOVABLE-STRIP WRITING OR READING APPARATUS
- B42D25/00—Information-bearing cards or sheet-like structures characterised by identification or security features; Manufacture thereof
- B42D25/40—Manufacture
- B42D25/405—Marking
- B42D25/43—Marking by removal of material
- B42D25/445—Marking by removal of material using chemical means, e.g. etching
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/10—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols with particular housing, physical features or manual controls
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Definitions
- the present invention relates to an individual authentication semiconductor chip, an individual authentication medium, and an individual authentication method.
- Biometric information is information that includes physical features such as fingerprints and veins, behavioral features such as voice and handwriting, etc., for user authentication of mobile phones and bank cash cards, authentication of computer login authority, etc. It's being used.
- development of an artefact metrics technique for authenticating an artifact having unique information similar to such biometric information using the unique information has been promoted.
- Artifact metrics technology is a promising technology for enhancing safety and reliability in transactions using artifacts such as certificates and credit cards.
- artifact metrics technology granular light reflection patterns, magnetic fiber magnetic patterns, randomly recorded magnetic patterns, random magnetic patterns of magnetic stripes, random charges of memory cells, incorporated in a medium such as a credit card
- Patent Document 1 An artificial pattern with extremely low reproducibility such as a quantity pattern and a resonance pattern of a conductive fiber is used as unique information.
- Patent Document 2 based on an image of a fine concavo-convex pattern, which is an artificial pattern with extremely low reproducibility, a technique for authenticating an individual by matching processing using the image has been proposed (see Patent Document 2).
- Patent Document 1 The various artificial patterns described in Patent Document 1 can be used as unique information for authenticating an artificial object, but it is difficult to make an extremely small chip, and it is difficult to incorporate it into an IC card or the like. There is a problem that.
- Patent Document 2 Although the artificial pattern described in Patent Document 2 can be easily made into a very small chip, it is necessary to use an image captured by an electron microscope or an optical microscope for individual authentication. There is a problem that the miniaturization of this is an obstacle to practical use.
- the present invention provides an individual authentication semiconductor chip having individual specific information, an individual authentication medium, and an individual authentication method capable of individual authentication using a small individual authentication device. Objective.
- the present invention provides a semiconductor chip used for authenticating an individual, a semiconductor substrate having a first surface and a second surface opposite thereto, and the first surface of the semiconductor substrate.
- An individual authentication having a fine concavo-convex structure unique to the individual formed between the drain region and the source region formed on the side and the drain region and the source region on the first surface of the semiconductor substrate;
- the minimum pattern interval of the fine concavo-convex structure is less than 10 nm (Invention 2).
- the fine concavo-convex structure is formed by using a resist structure formed by deforming at least part of a resist pattern formed on the first surface of the semiconductor substrate as a mask.
- the first surface side is formed by etching (Invention 3).
- the present invention also provides an individual authentication medium comprising the base and the semiconductor chip for individual authentication according to the above inventions (Inventions 1 to 3) incorporated in the base (Invention 4). .
- the present invention is a method for authenticating an individual using the individual authentication medium according to the above invention (invention 4), wherein a source-drain voltage is applied between the source electrode and the drain electrode in the individual authentication semiconductor chip.
- a source / drain current measurement step of measuring the source / drain current between the source electrode and the drain electrode, which is applied while changing, and individual authentication for authenticating the individual based on the measured source / drain current An individual authentication method characterized by including a process (Invention 5).
- the source / drain current specific to the fine concavo-convex structure of the semiconductor chip for individual authentication which is measured in advance, and the source / drain current measurement step are measured. It is preferable to authenticate the individual by comparing the source / drain current (Invention 6).
- the source / drain current inherent to the fine concavo-convex structure is obtained by applying a predetermined gate voltage to a selected gate electrode arbitrarily selected from the plurality of elongated gate electrodes. In the state where the source / drain voltage is applied between the source electrode and the drain electrode while changing, the source / drain voltage is measured in advance. It is preferable to measure the source / drain current in a state where a predetermined gate voltage is applied to the selection gate electrode selected when the source / drain current is measured in advance (Invention 7).
- the present invention it is possible to provide a semiconductor chip for individual authentication having individual unique information, an individual authentication medium, and an individual authentication method that can be used for individual authentication using a small individual authentication device.
- FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor chip for individual authentication according to an embodiment of the present invention.
- FIG. 2 is a perspective view showing a schematic configuration of a semiconductor chip for individual authentication according to an embodiment of the present invention.
- FIG. 3A is a cross-sectional view showing one step in the method for manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3B is a cross-sectional view showing one step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3C is a cross-sectional view showing a step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3A is a cross-sectional view showing one step in the method for manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3B is a cross-sectional view showing one step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3C is
- FIG. 3D is a cross-sectional view showing a step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3E is a cross-sectional view showing a step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3F is a cross-sectional view showing a step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 3G is a cross-sectional view showing one step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 4A is a cross-sectional view showing a step in the method for manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 4B is a cross-sectional view showing one step in the method for manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 4C is a cross-sectional view showing a step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 4D is a cross-sectional view showing one step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 4E is a cross-sectional view showing one step in the method of manufacturing an individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 4F is a cross-sectional view showing one step in the method of manufacturing a semiconductor chip for individual authentication according to one embodiment of the present invention.
- FIG. 5E are process flow diagrams showing the respective steps in the method for manufacturing the individual authentication structure (fine concavo-convex structure) according to one embodiment of the present invention in cross-sectional views.
- FIG. 6A to FIG. 6D are process flow diagrams showing each step in another aspect of the method for producing the individual authentication structure (fine concavo-convex structure) according to one embodiment of the present invention in a cross-sectional view.
- FIG. 7A is a plan view showing a schematic configuration of the individual authentication medium in one embodiment of the present invention
- FIG. 7B is a back view showing a schematic configuration of the individual authentication medium in one embodiment of the present invention.
- FIG. 8 is a schematic diagram for explaining the operation principle of the individual authentication semiconductor chip according to the embodiment of the present invention.
- FIG. 9A to FIG. 9C are process flow diagrams showing the respective steps in the method for manufacturing an individual authentication semiconductor chip according to another embodiment of the present invention in cross-sectional views.
- FIG. 10 is a plan view showing a schematic configuration of a multi-gate GaAs nanowire field effect transistor used in the simulation test of Test Example 1.
- FIG. 11A is a graph (No. 1) showing a waveform of a source / drain current measured in a simulation test of Test Example 1; 11B is a graph (No. 2) showing a waveform of a source / drain current measured in a simulation test of Test Example 1.
- FIG. FIG. 11C is a graph (part 3) illustrating a waveform of the source / drain current measured in the simulation test of Test Example 1.
- FIG. 11D is a graph (No. 4) illustrating waveforms of source / drain currents measured in the simulation test of Test Example 1.
- FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor chip for individual authentication according to this embodiment
- FIG. 2 is a perspective view showing a schematic configuration of a semiconductor chip for individual authentication according to this embodiment.
- the semiconductor chip 10 for individual authentication includes a semiconductor substrate 11 having a first surface 11 a and a second surface 11 b facing the first surface 11 a, and a first surface 11 a of the semiconductor substrate 11.
- An individual authentication structure 12 provided thereon, a gate insulating film 13 provided on the individual authentication structure 12, and a plurality of elongated gate electrodes 14G provided on the gate insulating film 13;
- the drain region 15D and the source region 15S formed on the first surface 11a of the semiconductor substrate 11 near the both end portions 141 and 142 of the gate electrode 14G are electrically connected to the drain region 15D and the source region 15S, respectively.
- a drain electrode 16D and a source electrode 16S connected to each other.
- the semiconductor substrate 11 is not particularly limited.
- a p-type or n-type silicon substrate, a ZnO substrate, a diamond substrate, or the like can be used. Of these, it is preferable to use a p-type silicon substrate. .
- the semiconductor substrate 11 has a mesa region 111 provided with the individual authentication structure 12 located substantially at the center of the first surface 11a, and an alignment mark 112 located near the periphery of the first surface 11a.
- the thickness of the semiconductor substrate 11 is not particularly limited, and is, for example, about 0.1 to 0.8 mm.
- the size of the semiconductor substrate 11 (size in plan view) is not particularly limited, and is, for example, about 100 to 2000 ⁇ m. Since the size of the semiconductor chip for individual authentication 10 is determined by the size of the semiconductor substrate 11 (size in plan view), the semiconductor chip for individual authentication can be reduced by reducing the size of the semiconductor substrate 11 as much as possible. Ten miniaturizations can be achieved.
- the gate insulating film 13 is provided so as to cover the individual authentication structure 12 (the fine concavo-convex structure 121), and has a silicon oxide film, silicon nitride film, silicon oxynitride film, aluminum oxide film or the like having a thickness of about 2 to 10 nm. It is comprised by the single layer film or laminated film.
- a plurality of elongated gate electrode 14G is applied configured to be able to gate voltage V G substantially has parallel in parallel, independently of each gate electrode 14G with each other.
- a predetermined gate voltage V G for example, threshold voltage V T
- An inversion layer 15C that continues between the drain region 15D and the source region 15S is formed on the first surface 11a of the semiconductor substrate 11 immediately below (between the drain region 15D and the source region 15S).
- each gate electrode 14G of the gate voltage V G is applied Different shapes.
- the individual authentication semiconductor chip 10 by applying a gate voltage V G to the gate electrode 14G that is arbitrarily selected, to obtain the waveform of the specific source-drain current I DS, the specific source-drain The individual can be authenticated based on the waveform of the current IDS .
- Width W 14G in the transverse direction of the gate electrode 14G is, for example, about 0.01 ⁇ 1.0 .mu.m, and preferably about 0.05 ⁇ 0.5 [mu] m.
- the length L 14G in the longitudinal direction of the gate electrode 14G is, for example, about 0.5 to 5 ⁇ m, preferably about 1 to 2 ⁇ m.
- the thickness (film thickness) T 14G of the gate electrode 14G is, for example, about 50 to 500 nm, preferably about 100 to 200 nm.
- the pitch of the plurality of gate electrodes 14G (the length between the centers of adjacent gate electrodes 14G in the short direction) P 14G is, for example, about 0.02 to 2.0 ⁇ m, preferably about 0.1 to 1.0 ⁇ m. .
- the conductive material constituting the gate electrode 14G is not particularly limited, and examples thereof include aluminum, an aluminum alloy, metal silicide, and polysilicon.
- the drain region 15D and the source region 15S are formed on the first surface 11a side of the semiconductor substrate 11 in the vicinity of both end portions 141, 142 in the longitudinal direction of the gate electrode 14G.
- the drain region 15D and the source region 15S are formed on the first surface 11a side of the semiconductor substrate 11 by doping a p-type or n-type dopant (impurity) by an ion implantation method, a thermal diffusion method, or the like with the gate electrode 14G interposed therebetween. P-type or n-type semiconductor layer.
- Each of the drain electrode 16D and the source electrode 16S is provided on each of the drain region 15D and the source region 15S, and preferably provided so as not to overlap the gate electrode 14G in the thickness direction.
- the thickness (film thickness) of the drain electrode 16D and the source electrode 16S is, for example, about 50 to 500 nm, and preferably about 100 to 200 nm.
- the conductive material constituting the drain electrode 16D and the source electrode 16S is not particularly limited, and examples thereof include aluminum, aluminum alloy, metal silicide, and polysilicon.
- FIGS. 3A to 3G and FIGS. 4A to 4F are process flow diagrams showing the respective steps in the method for manufacturing the individual authentication semiconductor chip according to the present embodiment in cross-sectional views.
- a semiconductor substrate 11 having a first surface 11a and a second surface 11b opposite to the first surface 11a is prepared, and a resist pattern 21 corresponding to the mesa region 111 and a resist corresponding to the alignment mark 112 are formed on the first surface 11a of the semiconductor substrate 11.
- a pattern 22 is formed (see FIG. 3A).
- the resist material constituting the resist patterns 21 and 22 is not particularly limited, and known resist materials used in various lithography can be used.
- the first surface 11a of the semiconductor substrate 11 is etched using the resist patterns 21 and 22 as a mask, and the resist patterns 21 and 22 are removed to form the mesa region 111 and the alignment mark 112 on the first surface 11a of the semiconductor substrate 11. (See FIG. 3B).
- the individual authentication structure 12 (fine concavo-convex structure 121) is formed on the mesa region 111 of the first surface 11a of the semiconductor substrate 11 (see FIG. 3C).
- FIG. 5A to FIG. 5E are process flow diagrams showing the respective steps in the method for producing the individual authentication structure (fine concavo-convex structure) in the present embodiment in cross-sectional views.
- An energy ray sensitive resist is applied on the mesa region 111 of the semiconductor substrate 11 to form a resist layer 30 (see FIG. 5A).
- a known negative or positive resist material that can react by irradiation with a desired energy beam such as an electron beam, an X-ray, or an ultraviolet ray is used.
- the negative type is International Publication 2009.
- Examples of the resist composition described in Japanese Patent No. 060869 resist composition containing a calix resorcinarene derivative having a predetermined structure, an acid generator and a crosslinking agent), and ZEP520A manufactured by Nippon Zeon Co., Ltd., and the like.
- the thickness of the resist layer 30 can be appropriately set according to the physical strength of the resist material, the shape, dimensions, pitch, etc. of the resist pattern, and can be set to about 10 to 500 nm, for example.
- a latent image 31 of a resist pattern is formed by irradiating a desired portion of the resist layer 30 (a portion where the individual authentication structure 12 (fine concavo-convex structure 121) is to be formed) with an energy beam (see FIG. 5B).
- the energy ray is appropriately selected according to the type of resist material.
- the resist layer 30 is developed to form a resist pattern 32 (see FIG. 5C), and by applying an external force to the resist pattern 32, the resist having at least a part of the resist deformed portion 41 in which the resist pattern 32 is deformed.
- a structure 40 is formed (see FIG. 5D).
- the resist pattern 32 before applying the external force is a pillar-shaped pattern such as a substantially circular shape or a substantially rectangular shape in a plan view, a line-and-space pattern, or a combination of these patterns. It is possible to form a resist structure 40 in which at least a part of the deformed portion 41 includes a resist 32 that is irregularly (randomly) deformed (deformed such as inclination, collapse, or slip). In the resist deformation portion 41, the minimum distance between the resist patterns 32 is preferably 10 nm or less, and particularly preferably 5 nm or less.
- the external force applied to the resist pattern 32 for example, the surface tension of the rinse treatment liquid in the drying process of the rinse treatment performed after the development processing, the electrostatic force generated by charging by charged particle beam irradiation, the fluid pressure by fluid ejection, Examples include vibration pressure of sonic vibration, and at least one of these external forces is applied to the resist pattern 32.
- the resist pattern 32 can be easily deformed, and the resist structure 40 having randomness and fineness of a pattern that is extremely difficult to reproduce artificially is obtained. Can be formed.
- the semiconductor substrate 11 is etched by etching the first surface 11a of the semiconductor substrate 11 using the resist structure 40 as a mask (for example, dry etching such as reactive ion etching and reactive gas etching; physical etching such as ion milling).
- the individual authentication structure 12 (fine concavo-convex structure 121) is formed on the mesa region 111 of the first surface 11a (see FIG. 5E).
- the fine concavo-convex structure 121 having various shapes and dimensions can be formed, and the minimum pattern of the fine concavo-convex structure 121 can be formed.
- the interval can be preferably 10 nm or less, particularly preferably 5 nm or less.
- a gate insulating film 13 covering the first surface 11a of the semiconductor substrate 11 is formed with a thickness of about 2 to 10 nm (see FIG. 3D).
- the method for forming the gate insulating film 13 is not particularly limited.
- the surface thermal oxidation method of the first surface 11a of the semiconductor substrate 11 or the sputtering of the insulating material (SiO 2 or the like) constituting the gate insulating film 13 is used.
- Method, CVD method, atomic layer deposition (ALD) method, laser ablation method and the like are examples of the gate insulating film 13.
- a substantially uniform gate insulating film 13 may be formed along the fine concavo-convex structure 121 of the first surface 11a of the semiconductor substrate 11, or an insulating material constituting the gate insulating film 13 is formed, and the insulating film
- the gate insulating film 13 may be formed by planarizing the film by CMP or the like.
- a resist pattern 23 having openings corresponding to the drain region 15D and the source region 15S is formed on the gate insulating film 13 (see FIG. 3E), and the resist pattern 23 is used as a mask from the opening.
- the exposed gate insulating film 13 is etched, and the exposed first surface 11a of the semiconductor substrate 11 is doped with a dopant (conductivity type impurity) by ion implantation (see FIG. 3F).
- Examples of the dopant to be doped (conductivity type impurities) include P and As.
- the resist pattern 23 is removed, and an annealing process is performed at a predetermined temperature. Thereby, the doped dopant (conductivity type impurity) is activated, and the drain region 15D and the source region 15S are formed (see FIG. 3G).
- the doped dopant conductivity type impurity
- a thin film 16 having a thickness of about 50 to 500 nm made of a conductive material constituting the drain electrode 16D and the source electrode 16S is formed so as to cover the gate insulating film 13, the drain region 15D, and the source region 15S (see FIG. (See FIG. 4A).
- a resist pattern 24 corresponding to the drain electrode 16D and the source electrode 16S is formed (see FIG. 4B).
- the conductive material thin film 16 is etched using the resist pattern 24 as a mask, and an annealing process is performed at a predetermined temperature, thereby forming the drain electrode 16D and the source electrode 16S (see FIG. 4C).
- a resist pattern 25 having an opening corresponding to the gate electrode 14G is formed (see FIG. 4D).
- a thin film 14 made of a conductive material constituting the gate electrode 14G and having a thickness of about 50 to 500 nm is formed on the resist pattern 25.
- the resist pattern 25 is removed (lifted off) to form the gate electrode 14G (see FIG. 4F). In this way, the individual authentication semiconductor chip 10 according to the present embodiment is manufactured.
- the individual authentication structure 12 (fine concavo-convex structure 121) is formed on the mesa region 111 of the first surface 11a of the semiconductor substrate 11 by the lithography process, but is limited to such an embodiment. It is not something.
- a mold 50 in which a fine uneven structure 51 having irregular (random) unevenness is formed is prepared (see FIG. 6A) and applied onto the mesa region 111 of the semiconductor substrate 11.
- the individual authentication structure 12 (fine concavo-convex structure 121) may be formed (see FIG. 6D).
- FIG. 7A is a plan view showing a schematic configuration of the individual authentication medium in the present embodiment
- FIG. 7B is a rear view thereof.
- a credit card will be described as an example of the individual authentication medium 1.
- the present invention is not limited to this. For example, various personal authentication cards, passports, driver's licenses, various securities, various guarantees. Etc.
- the individual authentication medium 1 in the present embodiment includes a flat base 2 made of an appropriate material such as a resin, and a plurality of structures each having a predetermined function are provided on each of the first surface 2a and the second surface 2b of the base 2. It has been.
- the first surface 2a of the base 2 incorporates an IC chip 3 in which various information such as security information is stored, and the individual authentication semiconductor chip 10 according to the present embodiment.
- On the second surface 2b of the base 2 is provided a magnetic stripe 4 in which various information is stored.
- a method for authenticating an individual using such an individual authentication medium 1 will be described.
- Individual authentication method in this embodiment is applied while varying the source-drain voltage V DS between the drain electrode 16D and source electrode 16S in an individual authentication semiconductor chip 10, the source between the drain electrode 16D and source electrode 16S It includes a source-drain current measuring step of measuring the drain current I DS, based on the measured source-drain current I DS, the individual authentication process to authenticate the individual.
- the drain electrode 16D and the drain electrode 16D are applied while applying a predetermined gate voltage V G to one or more gate electrodes 14G selected from among the plurality of gate electrodes 14G of the individual authentication semiconductor chip 10.
- the source / drain voltage V DS applied between the source electrodes 16S is changed within a predetermined range.
- the individual authentication structure 12 formed immediately below the gate electrode 14G is irregular (random) and has a fine concavo-convex structure 121 having irregularities with extremely low reproducibility. including.
- the gate insulating film 13 formed on the fine concavo-convex structure 121 varies along the longitudinal direction of the gate electrode 14G due to the presence of the fine concavo-convex structure 121, the gate insulating film Due to the variation in the thickness of 13, the distance between the gate electrode 14G and the first surface 11a of the semiconductor substrate 11 varies.
- V G for example, threshold voltage V T
- V G for example, threshold voltage V T
- the variation in the height of the fine concavo-convex structure 121 is as small as several tens to several hundreds of nanometers.
- the charge shielding effect along the shape of the concavo-convex structure 121 is difficult to be achieved, and the inversion layer (channel) 15C conforming to the shape of the fine concavo-convex structure 121 is not formed.
- V G for example, threshold voltage V T .
- the carrier (electron or hole) density has variations along the channel length direction (longitudinal direction of the gate electrode 14G).
- the inversion layer (channel) 15C has a unique carrier (electron or hole) density distribution along the channel length direction (longitudinal direction of the gate electrode 14G) in each individual authentication semiconductor chip 10.
- Each inversion layer 15C formed on the first surface 11a of the semiconductor substrate 11 immediately below each gate electrode 14G in the single individual authentication semiconductor chip 10 also has a unique carrier (electron or hole) density distribution.
- the shift of the pinch-off point appears as a change in the waveform of the measured source / drain current I DS (for example, an irregular change (kink phenomenon) appearing in the waveform of the source / drain current I DS ).
- an irregular change for example, an irregular change (kink phenomenon) appearing in the waveform of the source / drain current I DS .
- the change in intrinsic waveform of the source-drain current I DS appears in an individual authentication semiconductor chip 10 according to, in response to specific carriers (electrons or holes) density distribution of the inversion layer (channel) 15C.
- the source If the source / drain current I DS when the drain voltage V DS is changed (increased) within a predetermined range is measured in advance and the characteristics appearing in the waveform of the source / drain current I DS are registered and stored, and the source-drain current I DS which is measured under predetermined conditions using the individual authentication medium 1, by the matching processing between the registered source-drain current I DS which is registered and stored, it is possible to authenticate the individual.
- a matching processing method between the measured source / drain current I DS and the registered source / drain current I DS for example, a method of performing matching processing with the maximum value of the cross-correlation coefficient, or feature extraction such as eigenvalue / eigenvector, etc. And a method using principal component analysis based on the above.
- the semiconductor chip 10 for individual authentication As described above, according to the semiconductor chip 10 for individual authentication according to this embodiment, it can be easily incorporated into a medium such as a credit card, and individual authentication can be performed with high accuracy by measuring the source / drain current IDS. Therefore, individual authentication can be performed using a small individual authentication device.
- the method for manufacturing the individual authentication semiconductor chip 10, particularly the method for forming the drain region 15 ⁇ / b> D and the source region 15 ⁇ / b> S has been described by taking a method of doping a dopant (conductivity type impurity) by ion implantation as an example.
- a dopant conductivity type impurity
- the present invention is not limited to such an embodiment.
- P, As, or the like as a donor element is contained on a mask (SiO 2 or the like) 26 having a predetermined opening formed on the first surface 11a of the semiconductor substrate 11.
- the n-type diffusion layer forming composition 15 is applied (FIG. 9A), and the drain region 15D and the source region 15S are formed by thermally diffusing the donor element (FIG. 9B), and then finely formed on the mesa region 111.
- the uneven structure 121 may be formed (FIG. 9C).
- Test Example 1 A multi-gate GaAs nanowire field effect transistor (see FIG. 10) in which four Schottky gates G1 to G4 are orthogonal to the GaAs nanowire Nw was prepared. Then, in a state where predetermined gate voltages V G1 to V G4 are applied to the respective Schottky gates G1 to G4 of the multi-gate GaAs nanowire field effect transistor, the source / drain voltage V DS applied to the GaAs nanowire Nw is set to 0 to 3 The source / drain current I DS was measured by changing the voltage within a range of 0.0V. The results are shown in FIGS. 11A to 11D.
- the horizontal axis represents the source / drain voltage V DS
- the vertical axis represents the source / drain current I DS
- Figure 11A is applied to the Schottky gate G2 ⁇ gate voltage V G2 ⁇ V G4 of 0.6V to G4, sweeping the gate voltage V G1 applied to the Schottky gate G1 for each 0.1V in the range of 0 ⁇ 1V
- 0.6V gate voltages V G1 , V G3 and V G4 are applied to Schottky gates G1, G3 and G4, and the gate voltage V G2 applied to Schottky gate G2 is 0 in the range of 0 to 1V. This is a waveform of the source / drain current I DS when swept every 1V.
- FIG. 11C 0.6V gate voltages V G1 , V G2 and V G4 are applied to Schottky gates G1, G2 and G4, and the gate voltage V G3 applied to Schottky gate G3 is 0 in the range of 0 to 1V. This is a waveform of the source / drain current I DS when swept every 1V.
- Figure 11D applies a 0.6V gate voltage V G1 ⁇ V G3 of the Schottky gate G1 ⁇ G3, sweeping the gate voltage V G4 applied to the Schottky gate G4 per 0.1V in the range of 0 ⁇ 1V
- the electron density of the inversion layer immediately below the Schottky gate varies.
- the position of the different parts of the electron density, from the waveform of the specific source-drain current I DS is obtained by irregular (random) fine concavo-convex structure 12, electrons in the semiconductor chip 10 for each individual authentication Density divergent portion is unique, the waveform of the specific source-drain current I DS is the obtained presumed. Therefore, in the individual authentication semiconductor chip 10 to obtain the waveform of the source-drain current I DS, it is considered possible to authenticate the individual by the individual authentication medium 1 to which the individual authentication semiconductor chip 10 is incorporated .
- the present invention is useful in a field where individual authentication using unique features of an artifact is required.
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computer Security & Cryptography (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Software Systems (AREA)
- Signal Processing (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- General Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Drying Of Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
L'invention concerne une puce semiconductrice pour une authentification individuelle 10 ayant des informations uniques d'un individu, pour laquelle l'individu peut être authentifié à l'aide d'un petit dispositif d'authentification individuelle, comprenant : un substrat semiconducteur 11 qui a une première surface 11a et une seconde surface 11b qui fait face en opposition à celle-ci; une région de drain 15D et une région de source 15S formées sur le côté du substrat semiconducteur 11 à proximité de la première surface 11a; une structure d'authentification individuelle 12 ayant une structure d'évidement/projection fine 121 unique à l'individu, ladite structure 12 étant formée entre la région de drain 15D et la région de source 15S; un film d'isolation 13 disposé sur la structure d'authentification individuelle 12; une pluralité d'électrodes de grille allongées 14G disposées sur le film isolant 13 et alignées grossièrement en parallèle l'une par rapport à l'autre; et une électrode de drain 16D et une électrode de source 16S positionnées, respectivement, au voisinage des deux extrémités de la pluralité d'électrodes de grille de forme allongée 14G, et connectées respectivement à la région de drain 15D et à la région de source 15S.
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JP2016234745A JP2018089845A (ja) | 2016-12-02 | 2016-12-02 | 個体認証用半導体チップ、個体認証媒体及び個体認証方法 |
JP2016-234745 | 2016-12-02 |
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WO2018101480A1 true WO2018101480A1 (fr) | 2018-06-07 |
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PCT/JP2017/043388 WO2018101480A1 (fr) | 2016-12-02 | 2017-12-04 | Puce semiconductrice pour authentification individuelle, support d'authentification individuel et procédé d'authentification individuelle |
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Citations (6)
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---|---|---|---|---|
JPH04105359A (ja) * | 1990-08-23 | 1992-04-07 | Sony Corp | 大ゲート面積mosトランジスタ |
JP2001007290A (ja) * | 1999-06-24 | 2001-01-12 | Mitsubishi Electric Corp | 半導体装置、半導体装置の製造方法、および、通信方法 |
JP2002073424A (ja) * | 2000-08-31 | 2002-03-12 | Mitsubishi Electric Corp | 半導体装置、端末装置および通信方法 |
JP2009032905A (ja) * | 2007-07-27 | 2009-02-12 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
JP2014059377A (ja) * | 2012-09-14 | 2014-04-03 | Dainippon Printing Co Ltd | 個体認証用構造体の製造方法 |
JP2015525979A (ja) * | 2012-08-10 | 2015-09-07 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | セキュア・デバイスを製造する方法およびセキュア・デバイス |
-
2016
- 2016-12-02 JP JP2016234745A patent/JP2018089845A/ja not_active Ceased
-
2017
- 2017-12-04 WO PCT/JP2017/043388 patent/WO2018101480A1/fr active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04105359A (ja) * | 1990-08-23 | 1992-04-07 | Sony Corp | 大ゲート面積mosトランジスタ |
JP2001007290A (ja) * | 1999-06-24 | 2001-01-12 | Mitsubishi Electric Corp | 半導体装置、半導体装置の製造方法、および、通信方法 |
JP2002073424A (ja) * | 2000-08-31 | 2002-03-12 | Mitsubishi Electric Corp | 半導体装置、端末装置および通信方法 |
JP2009032905A (ja) * | 2007-07-27 | 2009-02-12 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
JP2015525979A (ja) * | 2012-08-10 | 2015-09-07 | インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation | セキュア・デバイスを製造する方法およびセキュア・デバイス |
JP2014059377A (ja) * | 2012-09-14 | 2014-04-03 | Dainippon Printing Co Ltd | 個体認証用構造体の製造方法 |
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